int.hh File Reference

#include <cassert>
#include "arch/arm/types.hh"
#include "base/logging.hh"
#include "sim/core.hh"

Go to the source code of this file.

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::ArmISA

Typedefs
typedef IntRegIndex	gem5::ArmISA::IntRegMap[NUM_ARCH_INTREGS]

Functions
	gem5::ArmISA::BitUnion32 (PackedIntReg) Bitfield< 31
	gem5::ArmISA::EndBitUnion (PackedIntReg) enum IntRegIndex
static IntRegIndex	gem5::ArmISA::INTREG_USR (unsigned index)
static IntRegIndex	gem5::ArmISA::INTREG_HYP (unsigned index)
static IntRegIndex	gem5::ArmISA::INTREG_SVC (unsigned index)
static IntRegIndex	gem5::ArmISA::INTREG_MON (unsigned index)
static IntRegIndex	gem5::ArmISA::INTREG_ABT (unsigned index)
static IntRegIndex	gem5::ArmISA::INTREG_UND (unsigned index)
static IntRegIndex	gem5::ArmISA::INTREG_IRQ (unsigned index)
static IntRegIndex	gem5::ArmISA::INTREG_FIQ (unsigned index)
static int	gem5::ArmISA::intRegInMode (OperatingMode mode, int reg)
static int	gem5::ArmISA::flattenIntRegModeIndex (int reg)
static IntRegIndex	gem5::ArmISA::makeSP (IntRegIndex reg)
static IntRegIndex	gem5::ArmISA::makeZero (IntRegIndex reg)
static bool	gem5::ArmISA::isSP (IntRegIndex reg)

Variables
	gem5::ArmISA::uh1
Bitfield< 15, 0 >	gem5::ArmISA::uh0
SignedBitfield< 31, 16 >	gem5::ArmISA::sh1
SignedBitfield< 15, 0 >	gem5::ArmISA::sh0
Bitfield< 31, 0 >	gem5::ArmISA::uw
SignedBitfield< 31, 0 >	gem5::ArmISA::sw
const IntRegMap	gem5::ArmISA::IntReg64Map
const IntRegMap	gem5::ArmISA::IntRegUsrMap
const IntRegMap	gem5::ArmISA::IntRegHypMap
const IntRegMap	gem5::ArmISA::IntRegSvcMap
const IntRegMap	gem5::ArmISA::IntRegMonMap
const IntRegMap	gem5::ArmISA::IntRegAbtMap
const IntRegMap	gem5::ArmISA::IntRegUndMap
const IntRegMap	gem5::ArmISA::IntRegIrqMap
const IntRegMap	gem5::ArmISA::IntRegFiqMap
static const unsigned	gem5::ArmISA::intRegsPerMode = NUM_INTREGS
const int	gem5::ArmISA::ReturnValueReg = 0
const int	gem5::ArmISA::ReturnValueReg1 = 1
const int	gem5::ArmISA::ReturnValueReg2 = 2
const int	gem5::ArmISA::NumArgumentRegs = 4
const int	gem5::ArmISA::NumArgumentRegs64 = 8
const int	gem5::ArmISA::ArgumentReg0 = 0
const int	gem5::ArmISA::ArgumentReg1 = 1
const int	gem5::ArmISA::ArgumentReg2 = 2
const int	gem5::ArmISA::ArgumentReg3 = 3
const int	gem5::ArmISA::FramePointerReg = 11
const int	gem5::ArmISA::StackPointerReg = INTREG_SP
const int	gem5::ArmISA::ReturnAddressReg = INTREG_LR
const int	gem5::ArmISA::PCReg = INTREG_PC
const int	gem5::ArmISA::SyscallNumReg = ReturnValueReg
const int	gem5::ArmISA::SyscallPseudoReturnReg = ReturnValueReg
const int	gem5::ArmISA::SyscallSuccessReg = ReturnValueReg