gem5
v21.2.1.1
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#include "arch/riscv/interrupts.hh"
#include "dev/intpin.hh"
#include "dev/io_device.hh"
#include "dev/mc146818.hh"
#include "dev/reg_bank.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/Clint.hh"
#include "sim/system.hh"
Go to the source code of this file.
Classes | |
class | gem5::Clint |
NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive.cdn.prismic.io/sifive/fab000f6- 0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_ full_20G1.03.00_manual.pdf. More... | |
class | gem5::Clint::ClintRegisters |
MMIO Registers 0x0000 - 0x3FFF: msip (write-through to misc reg file) ...: reserved[0] 0x4000 - 0xBFF7: mtimecmp ...: reserved[1] 0xBFF8: mtime (read-only) More... | |
Namespaces | |
gem5 | |
Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |