gem5
v21.2.1.1
|
#include <cassert>
#include <cstddef>
#include <string>
#include "arch/vecregs.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
Go to the source code of this file.
Classes | |
class | gem5::RegClassOps |
class | gem5::DefaultRegClassOps |
class | gem5::RegClass |
class | gem5::RegId |
Register ID: describe an architectural register with its class and index. More... | |
class | gem5::PhysRegId |
Physical register ID. More... | |
struct | std::hash< gem5::RegId > |
Namespaces | |
gem5 | |
Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223. | |
std | |
Overload hash function for BasicBlockRange type. | |
Typedefs | |
using | gem5::PhysRegIdPtr = PhysRegId * |
Enumerations | |
enum | gem5::RegClassType { gem5::IntRegClass, gem5::FloatRegClass, gem5::VecRegClass, gem5::VecElemClass, gem5::VecPredRegClass, gem5::CCRegClass, gem5::MiscRegClass } |
Enumerate the classes of registers. More... | |