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rdy.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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6  Accellera licenses this file to you under the Apache License, Version 2.0
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15  implied. See the License for the specific language governing
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18  *****************************************************************************/
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20 /*****************************************************************************
21 
22  rdy.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 #include "systemc.h"
39 
40 /******************************************************************************/
41 /*************************** rdy Function **********************/
42 /******************************************************************************/
43 
44 SC_MODULE( RDY )
45 {
46  SC_HAS_PROCESS( RDY );
47 
48  sc_in_clk clk;
49 
50  /*** Input and Output Ports ***/
51  sc_signal<bool>& data;
52 
53  /*** Constructor ***/
54  RDY ( sc_module_name NAME,
55  sc_clock& TICK_N,
56  sc_signal<bool>& DATA )
57 
58  :
59  data (DATA)
60 
61  {
62  clk (TICK_N);
63  SC_CTHREAD( entry, clk.neg() );
64  }
65 
66  /*** Call to Process Functionality ***/
67  void entry();
68 
69 };
70 
71 void
72 RDY::entry()
73 {
74  // int a;
75  int a = 0;
76 
77  cout << "\nSTART OF SIM -- CLOCK AT NEGEDGE (10,30,50,...) " << endl;
78  cout << sc_time_stamp() << " : "
79  << " ready[S] = " << data
80  << " a[V] = " << a
81  << endl;
82 
83  a = 0; cout << "\t\t\t a = 0 " << endl;
84  cout << sc_time_stamp() << " : "
85  << " ready[S] = " << data
86  << " a[V] = " << a
87  << endl;
88  data.write(0); cout << " ready = 0 " << endl;
89  cout << sc_time_stamp() << " : "
90  << " ready[S] = " << data
91  << " a[V] = " << a
92  << endl;
93  wait(); cout << "\nCLK " << endl;
94  cout << sc_time_stamp() << " : "
95  << " ready[S] = " << data
96  << " a[V] = " << a
97  << endl;
98 
99  a = 1; cout << "\t\t a = 1 " << endl;
100  cout << sc_time_stamp() << " : "
101  << " ready[S] = " << data
102  << " a[V] = " << a
103  << endl;
104  data.write(1); cout << " ready = 1 " << endl;
105  cout << sc_time_stamp() << " : "
106  << " ready[S] = " << data
107  << " a[V] = " << a
108  << endl;
109  wait(); cout << "\nCLK " << endl;
110  cout << sc_time_stamp() << " : "
111  << " ready[S] = " << data
112  << " a[V] = " << a
113  << endl;
114 
115  a = 0; cout << "\t\t a = 0 " << endl;
116  cout << sc_time_stamp() << " : "
117  << " ready[S] = " << data
118  << " a[V] = " << a
119  << endl;
120  data.write(0); cout << " ready = 0 " << endl;
121  cout << sc_time_stamp() << " : "
122  << " ready[S] = " << data
123  << " a[V] = " << a
124  << endl;
125  wait(); cout << "\nCLK " << endl;
126  cout << sc_time_stamp() << " : "
127  << " ready[S] = " << data
128  << " a[V] = " << a
129  << endl;
130 
131  a = 1; cout << "\t\t a = 1 " << endl;
132  cout << sc_time_stamp() << " : "
133  << " ready[S] = " << data
134  << " a[V] = " << a
135  << endl;
136  data.write(1); cout << " ready = 1 " << endl;
137  cout << sc_time_stamp() << " : "
138  << " ready[S] = " << data
139  << " a[V] = " << a
140  << endl;
141  wait(); cout << "\nCLK " << endl;
142  cout << sc_time_stamp() << " : "
143  << " ready[S] = " << data
144  << " a[V] = " << a
145  << endl;
146 
147  halt();
148 }
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:66
gem5::MipsISA::halt
Bitfield< 26 > halt
Definition: dt_constants.hh:47
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
sc_core::wait
void wait()
Definition: sc_module.cc:653
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:301
SC_MODULE
SC_MODULE(RDY)
Definition: rdy.h:44
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:323
sc_core::sc_time_stamp
const sc_time & sc_time_stamp()
Definition: sc_main.cc:127
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