apic.hh File Reference

#include "base/bitunion.hh"

Go to the source code of this file.

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::X86ISA
	This is exposed globally, independent of the ISA.

Enumerations
enum	gem5::X86ISA::ApicRegIndex {   gem5::X86ISA::APIC_ID, gem5::X86ISA::APIC_VERSION, gem5::X86ISA::APIC_TASK_PRIORITY, gem5::X86ISA::APIC_ARBITRATION_PRIORITY,   gem5::X86ISA::APIC_PROCESSOR_PRIORITY, gem5::X86ISA::APIC_EOI, gem5::X86ISA::APIC_LOGICAL_DESTINATION, gem5::X86ISA::APIC_DESTINATION_FORMAT,   gem5::X86ISA::APIC_SPURIOUS_INTERRUPT_VECTOR, gem5::X86ISA::APIC_IN_SERVICE_BASE, gem5::X86ISA::APIC_TRIGGER_MODE_BASE = APIC_IN_SERVICE_BASE + 16, gem5::X86ISA::APIC_INTERRUPT_REQUEST_BASE = APIC_TRIGGER_MODE_BASE + 16,   gem5::X86ISA::APIC_ERROR_STATUS = APIC_INTERRUPT_REQUEST_BASE + 16, gem5::X86ISA::APIC_INTERRUPT_COMMAND_LOW, gem5::X86ISA::APIC_INTERRUPT_COMMAND_HIGH, gem5::X86ISA::APIC_LVT_TIMER,   gem5::X86ISA::APIC_LVT_THERMAL_SENSOR, gem5::X86ISA::APIC_LVT_PERFORMANCE_MONITORING_COUNTERS, gem5::X86ISA::APIC_LVT_LINT0, gem5::X86ISA::APIC_LVT_LINT1,   gem5::X86ISA::APIC_LVT_ERROR, gem5::X86ISA::APIC_INITIAL_COUNT, gem5::X86ISA::APIC_CURRENT_COUNT, gem5::X86ISA::APIC_DIVIDE_CONFIGURATION,   gem5::X86ISA::APIC_INTERNAL_STATE, gem5::X86ISA::NUM_APIC_REGS }

Functions
static ApicRegIndex	gem5::X86ISA::APIC_IN_SERVICE (int index)
static ApicRegIndex	gem5::X86ISA::APIC_TRIGGER_MODE (int index)
static ApicRegIndex	gem5::X86ISA::APIC_INTERRUPT_REQUEST (int index)
	gem5::X86ISA::BitUnion32 (InterruptCommandRegLow) Bitfield< 7
	gem5::X86ISA::EndBitUnion (InterruptCommandRegLow) BitUnion32(InterruptCommandRegHigh) Bitfield< 31

Variables
Bitfield< 12 >	gem5::X86ISA::deliveryStatus
Bitfield< 19, 18 >	gem5::X86ISA::destShorthand