| _status | gem5::BaseSimpleCPU | protected |
| activeThreads | gem5::BaseSimpleCPU | |
| advancePC(const Fault &fault) | gem5::BaseSimpleCPU | |
| amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) | gem5::BaseSimpleCPU | inlinevirtual |
| BaseSimpleCPU(const BaseSimpleCPUParams ¶ms) | gem5::BaseSimpleCPU | |
| branchPred | gem5::BaseSimpleCPU | protected |
| checker | gem5::BaseSimpleCPU | |
| checkForInterrupts() | gem5::BaseSimpleCPU | |
| checkPcEventQueue() | gem5::BaseSimpleCPU | protected |
| countInst() | gem5::BaseSimpleCPU | |
| curMacroStaticInst | gem5::BaseSimpleCPU | |
| curStaticInst | gem5::BaseSimpleCPU | |
| curThread | gem5::BaseSimpleCPU | protected |
| DcacheRetry enum value | gem5::BaseSimpleCPU | protected |
| DcacheWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| DcacheWaitSwitch enum value | gem5::BaseSimpleCPU | protected |
| DTBWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| Faulting enum value | gem5::BaseSimpleCPU | protected |
| haltContext(ThreadID thread_num) override | gem5::BaseSimpleCPU | |
| IcacheRetry enum value | gem5::BaseSimpleCPU | protected |
| IcacheWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| IcacheWaitSwitch enum value | gem5::BaseSimpleCPU | protected |
| Idle enum value | gem5::BaseSimpleCPU | protected |
| initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) | gem5::BaseSimpleCPU | inlinevirtual |
| initiateMemMgmtCmd(Request::Flags flags)=0 | gem5::BaseSimpleCPU | pure virtual |
| initiateMemRead(Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) | gem5::BaseSimpleCPU | inlinevirtual |
| ITBWaitResponse enum value | gem5::BaseSimpleCPU | protected |
| postExecute() | gem5::BaseSimpleCPU | |
| preExecute() | gem5::BaseSimpleCPU | |
| preExecuteTempPC | gem5::BaseSimpleCPU | protected |
| readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) | gem5::BaseSimpleCPU | inlinevirtual |
| resetStats() override | gem5::BaseSimpleCPU | |
| Running enum value | gem5::BaseSimpleCPU | protected |
| serializeThread(CheckpointOut &cp, ThreadID tid) const override | gem5::BaseSimpleCPU | |
| serviceInstCountEvents() | gem5::BaseSimpleCPU | |
| setupFetchRequest(const RequestPtr &req) | gem5::BaseSimpleCPU | |
| Status enum name | gem5::BaseSimpleCPU | protected |
| swapActiveThread() | gem5::BaseSimpleCPU | protected |
| threadInfo | gem5::BaseSimpleCPU | |
| totalInsts() const override | gem5::BaseSimpleCPU | |
| totalOps() const override | gem5::BaseSimpleCPU | |
| traceData | gem5::BaseSimpleCPU | |
| traceFault() | gem5::BaseSimpleCPU | protected |
| unserializeThread(CheckpointIn &cp, ThreadID tid) override | gem5::BaseSimpleCPU | |
| wakeup(ThreadID tid) override | gem5::BaseSimpleCPU | |
| writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable=std::vector< bool >()) | gem5::BaseSimpleCPU | inlinevirtual |
| ~BaseSimpleCPU() | gem5::BaseSimpleCPU | virtual |
