tlbi_op.hh File Reference

#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
#include "cpu/thread_context.hh"

Go to the source code of this file.

Classes
class	gem5::ArmISA::TLBIOp
class	gem5::ArmISA::TLBIALL
	TLB Invalidate All. More...
class	gem5::ArmISA::ITLBIALL
	Instruction TLB Invalidate All. More...
class	gem5::ArmISA::DTLBIALL
	Data TLB Invalidate All. More...
class	gem5::ArmISA::TLBIALLEL
	Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions. More...
class	gem5::ArmISA::TLBIVMALL
	Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions. More...
class	gem5::ArmISA::TLBIASID
	TLB Invalidate by ASID match. More...
class	gem5::ArmISA::ITLBIASID
	Instruction TLB Invalidate by ASID match. More...
class	gem5::ArmISA::DTLBIASID
	Data TLB Invalidate by ASID match. More...
class	gem5::ArmISA::TLBIALLN
	TLB Invalidate All, Non-Secure. More...
class	gem5::ArmISA::TLBIMVAA
	TLB Invalidate by VA, All ASID. More...
class	gem5::ArmISA::TLBIMVA
	TLB Invalidate by VA. More...
class	gem5::ArmISA::ITLBIMVA
	Instruction TLB Invalidate by VA. More...
class	gem5::ArmISA::DTLBIMVA
	Data TLB Invalidate by VA. More...
class	gem5::ArmISA::TLBIIPA
	TLB Invalidate by Intermediate Physical Address. More...

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::ArmISA

Detailed Description

The file contains the definition of a set of TLB Invalidate Instructions. Those are the ISA interface for TLB flushing operations.

Definition in file tlbi_op.hh.