| ►Ngem5 | Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223 |
| ►NArmISA | |
| CDecoder | |
| ►CArmFault | |
| CFaultVals | |
| CArmFaultVals | |
| CReset | |
| CUndefinedInstruction | |
| CSupervisorCall | |
| CSecureMonitorCall | |
| CSupervisorTrap | |
| CSecureMonitorTrap | |
| CHypervisorCall | |
| CHypervisorTrap | |
| CAbortFault | |
| CPrefetchAbort | |
| CDataAbort | |
| CVirtualDataAbort | |
| CInterrupt | |
| CVirtualInterrupt | |
| CFastInterrupt | |
| CVirtualFastInterrupt | |
| CPCAlignmentFault | PC alignment fault (AArch64 only) |
| CSPAlignmentFault | Stack pointer alignment fault (AArch64 only) |
| CSystemError | System error (AArch64 only) |
| CSoftwareBreakpoint | Software Breakpoint (AArch64 only) |
| CHardwareBreakpoint | |
| CWatchpoint | |
| CSoftwareStepFault | |
| CArmSev | |
| CIllegalInstSetStateFault | Illegal Instruction Set State fault (AArch64 only) |
| CFsFreebsd | |
| ►CEmuFreebsd | |
| CBaseSyscallABI | |
| CSyscallABI32 | |
| CSyscallABI64 | |
| CSkipFunc | |
| CFsWorkload | |
| CHTMCheckpoint | |
| CBranchImm | |
| CBranchImmCond | |
| CBranchReg | |
| CBranchRegCond | |
| CBranchRegReg | |
| CBranchImmReg | |
| CBranchImm64 | |
| CBranchImmCond64 | |
| CBranchRegReg64 | |
| CBranchReg64 | |
| CBranchRet64 | |
| CBranchRetA64 | |
| CBranchEret64 | |
| CBranchEretA64 | |
| CBranchImmReg64 | |
| CBranchImmImmReg64 | |
| CCrypto | |
| CDataXImmOp | |
| CDataXImmOnlyOp | |
| CDataXSRegOp | |
| CDataXERegOp | |
| CDataX1RegOp | |
| CDataX1RegImmOp | |
| CDataX1Reg2ImmOp | |
| CDataX2RegOp | |
| CDataX2RegImmOp | |
| CDataX3RegOp | |
| CDataXCondCompImmOp | |
| CDataXCondCompRegOp | |
| CDataXCondSelOp | |
| CMicroOp | Base class for Memory microops |
| CMicroOpX | |
| CMicroNeonMemOp | Microops for Neon loads/stores |
| CMicroNeonMixOp | Microops for Neon load/store (de)interleaving |
| CMicroNeonMixLaneOp | |
| CMicroNeonMixOp64 | Microops for AArch64 NEON load/store (de)interleaving |
| CMicroNeonMixLaneOp64 | |
| CVldMultOp64 | Base classes for microcoded AArch64 NEON memory instructions |
| CVstMultOp64 | |
| CVldSingleOp64 | |
| CVstSingleOp64 | |
| CMicroSetPCCPSR | Microops of the form PC = IntRegA CPSR = IntRegB |
| CMicroIntMov | Microops of the form IntRegA = IntRegB |
| CMicroIntImmOp | Microops of the form IntRegA = IntRegB op Imm |
| CMicroIntImmXOp | |
| CMicroIntOp | Microops of the form IntRegA = IntRegB op IntRegC |
| CMicroIntRegXOp | |
| CMicroIntRegOp | Microops of the form IntRegA = IntRegB op shifted IntRegC |
| CMicroMemOp | Memory microops which use IntReg + Imm addressing |
| CMicroMemPairOp | |
| CMacroMemOp | Base class for microcoded integer memory instructions |
| CPairMemOp | Base class for pair load/store instructions |
| CBigFpMemImmOp | |
| CBigFpMemPostOp | |
| CBigFpMemPreOp | |
| CBigFpMemRegOp | |
| CBigFpMemLitOp | |
| CVldMultOp | Base classes for microcoded integer memory instructions |
| CVldSingleOp | |
| CVstMultOp | Base class for microcoded integer memory instructions |
| CVstSingleOp | |
| CMacroVFPMemOp | Base class for microcoded floating point memory instructions |
| CMightBeMicro | |
| CRfeOp | |
| CSrsOp | |
| CMemory | |
| CMemoryImm | |
| CMemoryExImm | |
| CMemoryDImm | |
| CMemoryExDImm | |
| CMemoryReg | |
| CMemoryDReg | |
| CMemoryOffset | |
| CMemoryPreIndex | |
| CMemoryPostIndex | |
| CSysDC64 | |
| CMightBeMicro64 | |
| CMemory64 | |
| CMemoryImm64 | |
| CMemoryDImm64 | |
| CMemoryDImmEx64 | |
| CMemoryPreIndex64 | |
| CMemoryPostIndex64 | |
| CMemoryReg64 | |
| CMemoryRaw64 | |
| CMemoryEx64 | |
| CMemoryLiteral64 | |
| CMemoryAtomicPair64 | |
| CMult3 | Base class for multipy instructions using three registers |
| CMult4 | Base class for multipy instructions using four registers |
| CVReg | 128-bit NEON vector register |
| CPredOp | Base class for predicated integer operations |
| CPredImmOp | Base class for predicated immediate operations |
| CPredIntOp | Base class for predicated integer operations |
| CDataImmOp | |
| CDataRegOp | |
| CDataRegRegOp | |
| CPredMacroOp | Base class for predicated macro-operations |
| CPredMicroop | Base class for predicated micro-operations |
| CArmStaticInst | |
| CSveIndexIIOp | Index generation instruction, immediate operands |
| CSveIndexIROp | |
| CSveIndexRIOp | |
| CSveIndexRROp | |
| CSvePredCountOp | |
| CSvePredCountPredOp | |
| CSveWhileOp | While predicate generation SVE instruction |
| CSveCompTermOp | Compare and terminate loop SVE instruction |
| CSveUnaryPredOp | Unary, constructive, predicated (merging) SVE instruction |
| CSveUnaryUnpredOp | Unary, constructive, unpredicated SVE instruction |
| CSveUnaryWideImmUnpredOp | Unary with wide immediate, constructive, unpredicated SVE instruction |
| CSveUnaryWideImmPredOp | Unary with wide immediate, constructive, predicated SVE instruction |
| CSveBinImmUnpredConstrOp | Binary with immediate, destructive, unpredicated SVE instruction |
| CSveBinImmPredOp | Binary with immediate, destructive, predicated (merging) SVE instruction |
| CSveBinWideImmUnpredOp | Binary with wide immediate, destructive, unpredicated SVE instruction |
| CSveBinDestrPredOp | Binary, destructive, predicated (merging) SVE instruction |
| CSveBinConstrPredOp | Binary, constructive, predicated SVE instruction |
| CSveBinUnpredOp | Binary, unpredicated SVE instruction with indexed operand |
| CSveBinIdxUnpredOp | Binary, unpredicated SVE instruction |
| CSvePredLogicalOp | Predicate logical instruction |
| CSvePredBinPermOp | Predicate binary permute instruction |
| CSveCmpOp | SVE compare instructions, predicated (zeroing) |
| CSveCmpImmOp | SVE compare-with-immediate instructions, predicated (zeroing) |
| CSveTerPredOp | Ternary, destructive, predicated (merging) SVE instruction |
| CSveTerImmUnpredOp | Ternary with immediate, destructive, unpredicated SVE instruction |
| CSveReducOp | SVE reductions |
| CSveOrdReducOp | SVE ordered reductions |
| CSvePtrueOp | PTRUE, PTRUES |
| CSveIntCmpOp | Integer compare SVE instruction |
| CSveIntCmpImmOp | Integer compare with immediate SVE instruction |
| CSveAdrOp | ADR |
| CSveElemCountOp | Element count SVE instruction |
| CSvePartBrkOp | Partition break SVE instruction |
| CSvePartBrkPropOp | Partition break with propagation SVE instruction |
| CSveSelectOp | Scalar element select SVE instruction |
| CSveUnaryPredPredOp | SVE unary operation on predicate (predicated) |
| CSveTblOp | SVE table lookup/permute using vector of element indices (TBL) |
| CSveUnpackOp | SVE unpack and widen predicate |
| CSvePredTestOp | SVE predicate test |
| CSvePredUnaryWImplicitSrcOp | SVE unary predicate instructions with implicit source operand |
| CSvePredUnaryWImplicitSrcPredOp | SVE unary predicate instructions, predicated, with implicit source operand |
| CSvePredUnaryWImplicitDstOp | SVE unary predicate instructions with implicit destination operand |
| CSveWImplicitSrcDstOp | SVE unary predicate instructions with implicit destination operand |
| CSveBinImmUnpredDestrOp | SVE vector - immediate binary operation |
| CSveBinImmIdxUnpredOp | Binary with immediate index, destructive, unpredicated SVE instruction |
| CSveUnarySca2VecUnpredOp | Unary unpredicated scalar to vector instruction |
| CSveDotProdIdxOp | SVE dot product instruction (indexed) |
| CSveDotProdOp | SVE dot product instruction (vectors) |
| CSveComplexOp | SVE Complex Instructions (vectors) |
| CSveComplexIdxOp | SVE Complex Instructions (indexed) |
| CSveLdStructSS | |
| CSveStStructSS | |
| CSveLdStructSI | |
| CSveStStructSI | |
| CSveIndexedMemVI | |
| CSveIndexedMemSV | |
| CSveMemVecFillSpill | |
| CSveMemPredFillSpill | |
| CSveContigMemSS | |
| CSveContigMemSI | |
| CVfpMacroOp | |
| CFpOp | |
| CFpCondCompRegOp | |
| CFpCondSelOp | |
| CFpRegRegOp | |
| CFpRegImmOp | |
| CFpRegRegImmOp | |
| CFpRegRegRegOp | |
| CFpRegRegRegCondOp | |
| CFpRegRegRegRegOp | |
| CFpRegRegRegImmOp | |
| CInterrupts | |
| CISA | |
| CBaseISADevice | Base class for devices that use the MiscReg interfaces |
| CDummyISADevice | Dummy device that prints a warning when it is accessed |
| CSkipFuncLinux32 | |
| CSkipFuncLinux64 | |
| CFsLinux | |
| CDumpStats | |
| CDumpStats64 | |
| CSyscallTable32 | |
| CSyscallTable64 | |
| ►CEmuLinux | |
| CBaseSyscallABI | |
| CSyscallABI32 | |
| CSyscallABI64 | |
| ►CMMU | |
| CCachedState | |
| CStats | |
| CPTE | |
| CPageTableOps | |
| CV7LPageTableOps | |
| CV8PageTableOps4k | |
| CV8PageTableOps16k | |
| CV8PageTableOps64k | |
| ►CTlbEntry | |
| CLookup | |
| ►CPMU | Model of an ARM PMU version 3 |
| CCounterState | State of a counter within the PMU |
| CPMUEvent | Event definition base class |
| ►CRegularEvent | |
| CRegularProbe | |
| CSWIncrementEvent | |
| CRegABI32 | |
| CRegABI64 | |
| CIntRegClassOps | |
| CMiscRegLUTEntry | MiscReg metadata |
| CMiscRegLUTEntryInitializer | Metadata table accessible via the value of the register |
| CMiscRegNum32 | |
| CMiscRegNum64 | |
| CMiscRegClassOps | |
| ►CRemoteGDB | |
| ►CAArch32GdbRegCache | |
| CGEM5_PACKED | |
| ►CAArch64GdbRegCache | |
| CGEM5_PACKED | |
| CSEWorkload | |
| CBrkPoint | |
| CWatchPoint | |
| CSoftwareStep | |
| CVectorCatch | |
| CSelfDebug | |
| CStackTrace | |
| CStage2LookUp | |
| ►CTableWalker | |
| CDescriptorBase | |
| CL1Descriptor | |
| CL2Descriptor | Level 2 page table descriptor |
| CLongDescriptor | Long-descriptor format (LPAE) |
| CPort | |
| CStage2Walk | This translation class is used to trigger the data fetch once a timing translation returns the translated physical address |
| CTableWalkerState | |
| CTableWalkerStats | Statistics |
| CWalkerState | |
| CTlbTestInterface | |
| ►CTLB | |
| CTlbStats | |
| CTLBIOp | |
| CTLBIALL | TLB Invalidate All |
| CITLBIALL | Instruction TLB Invalidate All |
| CDTLBIALL | Data TLB Invalidate All |
| CTLBIALLEL | Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions |
| CTLBIVMALL | Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions |
| CTLBIASID | TLB Invalidate by ASID match |
| CITLBIASID | Instruction TLB Invalidate by ASID match |
| CDTLBIASID | Data TLB Invalidate by ASID match |
| CTLBIALLN | TLB Invalidate All, Non-Secure |
| CTLBIMVAA | TLB Invalidate by VA, All ASID |
| CTLBIMVA | TLB Invalidate by VA |
| CITLBIMVA | Instruction TLB Invalidate by VA |
| CDTLBIMVA | Data TLB Invalidate by VA |
| CTLBIIPA | TLB Invalidate by Intermediate Physical Address |
| ►NArmISAInst | |
| CMicroTmeOp | |
| CMicroTmeBasic64 | |
| CTmeImmOp64 | |
| CTmeRegNone64 | |
| CTstart64 | |
| CTtest64 | |
| CTcancel64 | |
| CMicroTfence64 | |
| CMicroTcommit64 | |
| CMacroTmeOp | |
| CTcommit64 | |
| ►Nauxv | |
| CAuxVector | |
| ►Nbitfield_backend | |
| CUnsigned | |
| CSigned | |
| CBitfieldTypes | |
| CBitUnionOperators | |
| CBitUnionBaseType | |
| CBitUnionBaseType< BitUnionType< T > > | |
| ►Nbloom_filter | |
| CBase | |
| CBlock | Simple deletable (with false negatives) bloom filter that extracts bitfields of an address to use as indexes of the filter vector |
| CBulk | Implementation of the bloom filter, as described in "Bulk Disambiguation of
Speculative Threads in Multiprocessors", by Ceze, Luis, et al |
| CH3 | Implementation of the bloom filter as described in "Implementing Signatures
for Transactional Memory", by Sanchez, Daniel, et al |
| CMultiBitSel | The MultiBitSel Bloom Filter associates an address to multiple entries through the use of multiple hash functions |
| CMulti | This BloomFilter has multiple sub-filters, each with its own hashing functionality |
| CPerfect | A perfect bloom filter with no false positives nor false negatives |
| ►Nbranch_prediction | |
| CLocalBP | Implements a local predictor that uses the PC to index into a table of counters |
| ►CBiModeBP | Implements a bi-mode branch predictor |
| CBPHistory | |
| ►CBPredUnit | Basically a wrapper class to hold both the branch predictor and the BTB |
| CBPredUnitStats | |
| CPredictorHistory | |
| ►CDefaultBTB | |
| CBTBEntry | |
| CIndirectPredictor | |
| ►CLoopPredictor | |
| CBranchInfo | |
| CLoopEntry | |
| CLoopPredictorStats | |
| ►CLTAGE | |
| CLTageBranchInfo | |
| ►CMultiperspectivePerceptron | |
| CACYCLIC | |
| CBIAS | |
| CBLURRYPATH | |
| CFilterEntry | Entry of the branch filter |
| CGHIST | Available features |
| CGHISTMODPATH | |
| CGHISTPATH | |
| CHistorySpec | Base class to implement the predictor tables |
| CIMLI | |
| CLOCAL | |
| CLocalHistories | Local history entries, each enty contains the history of directions taken by a given branch |
| CMODHIST | |
| CMODPATH | |
| CMPPBranchInfo | Branch information data |
| CPATH | |
| CRECENCY | |
| CRECENCYPOS | |
| CSGHISTPATH | |
| CThreadData | History data is kept for each thread |
| CMultiperspectivePerceptron64KB | |
| CMultiperspectivePerceptron8KB | |
| ►CMPP_TAGE | |
| CBranchInfo | |
| CMPP_LoopPredictor | |
| ►CMPP_StatisticalCorrector | |
| CBranchInfo | |
| CMPP_SCThreadHistory | |
| ►CMultiperspectivePerceptronTAGE | |
| CMPPTAGEBranchInfo | Branch information data type |
| CMPP_StatisticalCorrector_64KB | |
| CMultiperspectivePerceptronTAGE64KB | |
| CMPP_TAGE_8KB | |
| CMPP_LoopPredictor_8KB | |
| CMPP_StatisticalCorrector_8KB | |
| CMultiperspectivePerceptronTAGE8KB | |
| CReturnAddrStack | Return address stack class, implements a simple RAS |
| ►CSimpleIndirectPredictor | |
| CHistoryEntry | |
| CIPredEntry | |
| CThreadInfo | |
| ►CStatisticalCorrector | |
| CBranchInfo | |
| CSCThreadHistory | |
| CStatisticalCorrectorStats | |
| ►CTAGE | |
| CTageBranchInfo | |
| ►CTAGEBase | |
| CBranchInfo | |
| CFoldedHistory | |
| CTAGEBaseStats | |
| CTageEntry | |
| CThreadHistory | |
| ►CTAGE_SC_L_TAGE | |
| CBranchInfo | |
| CTAGE_SC_L_LoopPredictor | |
| ►CTAGE_SC_L | |
| CTageSCLBranchInfo | |
| CTAGE_SC_L_TAGE_64KB | |
| ►CTAGE_SC_L_64KB_StatisticalCorrector | |
| CSC_64KB_ThreadHistory | |
| CTAGE_SC_L_64KB | |
| CTAGE_SC_L_TAGE_8KB | |
| ►CTAGE_SC_L_8KB_StatisticalCorrector | |
| CSC_8KB_ThreadHistory | |
| CTAGE_SC_L_8KB | |
| ►CTournamentBP | Implements a tournament branch predictor, hopefully identical to the one used in the 21264 |
| CBPHistory | The branch history information that is created upon predicting a branch |
| ►Ncompression | |
| ►Nencoder | |
| CCode | |
| CBase | Base class for encoders |
| ►CHuffman | This encoder builds a Huffman tree using the frequency of each value to be encoded |
| CNode | Node for the Huffman tree |
| CNodeComparator | Entries are not inserted directly into the tree |
| ►CBase | Base cache compressor interface |
| CBaseStats | |
| CCompressionData | |
| ►CBaseDelta | Base class for all base-delta-immediate compressors |
| CPatternM | |
| CPatternX | |
| CBase64Delta8 | |
| CBase64Delta16 | |
| CBase64Delta32 | |
| CBase32Delta8 | |
| CBase32Delta16 | |
| CBase16Delta8 | |
| ►CCPack | |
| CPatternMMMM | |
| CPatternMMMX | |
| CPatternMMXX | |
| CPatternXXXX | |
| CPatternZZZX | |
| CPatternZZZZ | |
| ►CBaseDictionaryCompressor | |
| CDictionaryStats | |
| ►CDictionaryCompressor | A template version of the dictionary compressor that allows to choose the dictionary size |
| CCompData | |
| CDeltaPattern | A pattern that checks whether the difference of the value and the dictionary entries' is below a certain threshold |
| CFactory | Create a factory to determine if input matches a pattern |
| CFactory< Head > | Specialization to end the recursion |
| CLocatedMaskedPattern | A pattern that narrows the MaskedPattern by allowing a only single possible dictionary entry to be matched against |
| CMaskedPattern | A pattern that compares masked values against dictionary entries |
| CMaskedValuePattern | A pattern that compares masked values to a masked portion of a fixed value |
| CPattern | The compressed data is composed of multiple pattern entries |
| CRepeatedValuePattern | A pattern that checks if dictionary entry sized values are solely composed of multiple copies of a single value |
| CSignExtendedPattern | A pattern that checks whether the value is an N bits sign-extended value, that is, all the MSB starting from the Nth are equal to the (N-1)th bit |
| CUncompressedPattern | A pattern containing the original uncompressed data |
| ►CFPC | |
| CFPCCompData | |
| CRepBytes | |
| CSignExtended1Byte | |
| CSignExtended4Bits | |
| CSignExtendedHalfword | |
| CSignExtendedTwoHalfwords | |
| CUncompressed | |
| CZeroPaddedHalfword | |
| CZeroRun | |
| ►CFPCD | |
| CPatternFFFF | |
| CPatternFFXX | |
| CPatternMMMMPenultimate | |
| CPatternMMMMPrevious | |
| CPatternMMMXPenultimate | |
| CPatternMMMXPrevious | |
| CPatternMMXXPenultimate | |
| CPatternMMXXPrevious | |
| CPatternRRRR | |
| CPatternXXXX | |
| CPatternXXZZ | |
| CPatternXZZZ | |
| CPatternZXZX | |
| CPatternZZXX | |
| CPatternZZZX | |
| CPatternZZZZ | |
| ►CFrequentValues | This compressor samples the cache for a while, trying to define the most frequently used values |
| ►CCompData | |
| CCompressedValue | A compressed value contains its encoding, and the compressed data itself |
| CFrequentValuesListener | |
| CVFTEntry | |
| ►CMulti | |
| CMultiCompData | |
| CMultiStats | |
| ►CPerfect | |
| CCompData | |
| ►CRepeatedQwords | |
| CPatternM | |
| CPatternX | |
| ►CZero | |
| CPatternX | |
| CPatternZ | |
| ►Ncopy_engine_reg | |
| CDmaDesc | |
| CReg | |
| ►CRegs | |
| CINTRCTRL | |
| ►CChanRegs | |
| CCHANCMD | |
| CCHANCTRL | |
| CCHANERR | |
| CCHANSTS | |
| ►Ncp | |
| CPrint | |
| CFormat | |
| ►Ndebug | |
| CFlag | |
| CSimpleFlag | |
| CCompoundFlag | |
| CAllFlagsFlag | |
| ►Ndecode_cache | |
| ►CAddrMap | A sparse map from an Addr to a Value, stored in page chunks |
| CCacheChunk | |
| ►Nfastmodel | |
| CAmbaFromTlmBridge64 | |
| CAmbaToTlmBridge64 | |
| CSignalReceiver | |
| CSignalSender | |
| CCortexA76 | |
| CCortexA76Cluster | |
| CScxEvsCortexA76 | |
| CScxEvsCortexA76x1Types | |
| CScxEvsCortexA76x2Types | |
| CScxEvsCortexA76x3Types | |
| CScxEvsCortexA76x4Types | |
| CCortexA76TC | |
| CCortexR52 | |
| CCortexR52Cluster | |
| ►CScxEvsCortexR52 | |
| CCorePins | |
| CScxEvsCortexR52x1Types | |
| CScxEvsCortexR52x2Types | |
| CScxEvsCortexR52x3Types | |
| CScxEvsCortexR52x4Types | |
| CCortexR52TC | |
| ►CSCGIC | |
| CTerminator | |
| CGIC | |
| CPL330 | |
| CFastmodelRemoteGDB | |
| ►CResetControllerExample | |
| CCorePins | |
| CRegisters | |
| ►Nfree_bsd | |
| CThreadInfo | |
| CSkipUDelay | A class to skip udelay() and related calls in the kernel |
| ►NGcn3ISA | Classes that represnt vector/scalar operands in GCN3 ISA |
| CDecoder | |
| CInFmt_DS | |
| CInFmt_DS_1 | |
| CInFmt_EXP | |
| CInFmt_EXP_1 | |
| CInFmt_FLAT | |
| CInFmt_FLAT_1 | |
| CInFmt_INST | |
| CInFmt_MIMG | |
| CInFmt_MIMG_1 | |
| CInFmt_MTBUF | |
| CInFmt_MTBUF_1 | |
| CInFmt_MUBUF | |
| CInFmt_MUBUF_1 | |
| CInFmt_SMEM | |
| CInFmt_SMEM_1 | |
| CInFmt_SOP1 | |
| CInFmt_SOP2 | |
| CInFmt_SOPC | |
| CInFmt_SOPK | |
| CInFmt_SOPP | |
| CInFmt_VINTRP | |
| CInFmt_VOP1 | |
| CInFmt_VOP2 | |
| CInFmt_VOP3 | |
| CInFmt_VOP3_1 | |
| CInFmt_VOP3_SDST_ENC | |
| CInFmt_VOPC | |
| CInFmt_VOP_DPP | |
| CInFmt_VOP_SDWA | |
| CInstFormat | |
| CGPUISA | |
| CStatusReg | |
| CGCN3GPUStaticInst | |
| CInst_SOP2__S_ADD_U32 | |
| CInst_SOP2__S_SUB_U32 | |
| CInst_SOP2__S_ADD_I32 | |
| CInst_SOP2__S_SUB_I32 | |
| CInst_SOP2__S_ADDC_U32 | |
| CInst_SOP2__S_SUBB_U32 | |
| CInst_SOP2__S_MIN_I32 | |
| CInst_SOP2__S_MIN_U32 | |
| CInst_SOP2__S_MAX_I32 | |
| CInst_SOP2__S_MAX_U32 | |
| CInst_SOP2__S_CSELECT_B32 | |
| CInst_SOP2__S_CSELECT_B64 | |
| CInst_SOP2__S_AND_B32 | |
| CInst_SOP2__S_AND_B64 | |
| CInst_SOP2__S_OR_B32 | |
| CInst_SOP2__S_OR_B64 | |
| CInst_SOP2__S_XOR_B32 | |
| CInst_SOP2__S_XOR_B64 | |
| CInst_SOP2__S_ANDN2_B32 | |
| CInst_SOP2__S_ANDN2_B64 | |
| CInst_SOP2__S_ORN2_B32 | |
| CInst_SOP2__S_ORN2_B64 | |
| CInst_SOP2__S_NAND_B32 | |
| CInst_SOP2__S_NAND_B64 | |
| CInst_SOP2__S_NOR_B32 | |
| CInst_SOP2__S_NOR_B64 | |
| CInst_SOP2__S_XNOR_B32 | |
| CInst_SOP2__S_XNOR_B64 | |
| CInst_SOP2__S_LSHL_B32 | |
| CInst_SOP2__S_LSHL_B64 | |
| CInst_SOP2__S_LSHR_B32 | |
| CInst_SOP2__S_LSHR_B64 | |
| CInst_SOP2__S_ASHR_I32 | |
| CInst_SOP2__S_ASHR_I64 | |
| CInst_SOP2__S_BFM_B32 | |
| CInst_SOP2__S_BFM_B64 | |
| CInst_SOP2__S_MUL_I32 | |
| CInst_SOP2__S_BFE_U32 | |
| CInst_SOP2__S_BFE_I32 | |
| CInst_SOP2__S_BFE_U64 | |
| CInst_SOP2__S_BFE_I64 | |
| CInst_SOP2__S_CBRANCH_G_FORK | |
| CInst_SOP2__S_ABSDIFF_I32 | |
| CInst_SOP2__S_RFE_RESTORE_B64 | |
| CInst_SOPK__S_MOVK_I32 | |
| CInst_SOPK__S_CMOVK_I32 | |
| CInst_SOPK__S_CMPK_EQ_I32 | |
| CInst_SOPK__S_CMPK_LG_I32 | |
| CInst_SOPK__S_CMPK_GT_I32 | |
| CInst_SOPK__S_CMPK_GE_I32 | |
| CInst_SOPK__S_CMPK_LT_I32 | |
| CInst_SOPK__S_CMPK_LE_I32 | |
| CInst_SOPK__S_CMPK_EQ_U32 | |
| CInst_SOPK__S_CMPK_LG_U32 | |
| CInst_SOPK__S_CMPK_GT_U32 | |
| CInst_SOPK__S_CMPK_GE_U32 | |
| CInst_SOPK__S_CMPK_LT_U32 | |
| CInst_SOPK__S_CMPK_LE_U32 | |
| CInst_SOPK__S_ADDK_I32 | |
| CInst_SOPK__S_MULK_I32 | |
| CInst_SOPK__S_CBRANCH_I_FORK | |
| CInst_SOPK__S_GETREG_B32 | |
| CInst_SOPK__S_SETREG_B32 | |
| CInst_SOPK__S_SETREG_IMM32_B32 | |
| CInst_SOP1__S_MOV_B32 | |
| CInst_SOP1__S_MOV_B64 | |
| CInst_SOP1__S_CMOV_B32 | |
| CInst_SOP1__S_CMOV_B64 | |
| CInst_SOP1__S_NOT_B32 | |
| CInst_SOP1__S_NOT_B64 | |
| CInst_SOP1__S_WQM_B32 | |
| CInst_SOP1__S_WQM_B64 | |
| CInst_SOP1__S_BREV_B32 | |
| CInst_SOP1__S_BREV_B64 | |
| CInst_SOP1__S_BCNT0_I32_B32 | |
| CInst_SOP1__S_BCNT0_I32_B64 | |
| CInst_SOP1__S_BCNT1_I32_B32 | |
| CInst_SOP1__S_BCNT1_I32_B64 | |
| CInst_SOP1__S_FF0_I32_B32 | |
| CInst_SOP1__S_FF0_I32_B64 | |
| CInst_SOP1__S_FF1_I32_B32 | |
| CInst_SOP1__S_FF1_I32_B64 | |
| CInst_SOP1__S_FLBIT_I32_B32 | |
| CInst_SOP1__S_FLBIT_I32_B64 | |
| CInst_SOP1__S_FLBIT_I32 | |
| CInst_SOP1__S_FLBIT_I32_I64 | |
| CInst_SOP1__S_SEXT_I32_I8 | |
| CInst_SOP1__S_SEXT_I32_I16 | |
| CInst_SOP1__S_BITSET0_B32 | |
| CInst_SOP1__S_BITSET0_B64 | |
| CInst_SOP1__S_BITSET1_B32 | |
| CInst_SOP1__S_BITSET1_B64 | |
| CInst_SOP1__S_GETPC_B64 | |
| CInst_SOP1__S_SETPC_B64 | |
| CInst_SOP1__S_SWAPPC_B64 | |
| CInst_SOP1__S_RFE_B64 | |
| CInst_SOP1__S_AND_SAVEEXEC_B64 | |
| CInst_SOP1__S_OR_SAVEEXEC_B64 | |
| CInst_SOP1__S_XOR_SAVEEXEC_B64 | |
| CInst_SOP1__S_ANDN2_SAVEEXEC_B64 | |
| CInst_SOP1__S_ORN2_SAVEEXEC_B64 | |
| CInst_SOP1__S_NAND_SAVEEXEC_B64 | |
| CInst_SOP1__S_NOR_SAVEEXEC_B64 | |
| CInst_SOP1__S_XNOR_SAVEEXEC_B64 | |
| CInst_SOP1__S_QUADMASK_B32 | |
| CInst_SOP1__S_QUADMASK_B64 | |
| CInst_SOP1__S_MOVRELS_B32 | |
| CInst_SOP1__S_MOVRELS_B64 | |
| CInst_SOP1__S_MOVRELD_B32 | |
| CInst_SOP1__S_MOVRELD_B64 | |
| CInst_SOP1__S_CBRANCH_JOIN | |
| CInst_SOP1__S_ABS_I32 | |
| CInst_SOP1__S_MOV_FED_B32 | |
| CInst_SOP1__S_SET_GPR_IDX_IDX | |
| CInst_SOPC__S_CMP_EQ_I32 | |
| CInst_SOPC__S_CMP_LG_I32 | |
| CInst_SOPC__S_CMP_GT_I32 | |
| CInst_SOPC__S_CMP_GE_I32 | |
| CInst_SOPC__S_CMP_LT_I32 | |
| CInst_SOPC__S_CMP_LE_I32 | |
| CInst_SOPC__S_CMP_EQ_U32 | |
| CInst_SOPC__S_CMP_LG_U32 | |
| CInst_SOPC__S_CMP_GT_U32 | |
| CInst_SOPC__S_CMP_GE_U32 | |
| CInst_SOPC__S_CMP_LT_U32 | |
| CInst_SOPC__S_CMP_LE_U32 | |
| CInst_SOPC__S_BITCMP0_B32 | |
| CInst_SOPC__S_BITCMP1_B32 | |
| CInst_SOPC__S_BITCMP0_B64 | |
| CInst_SOPC__S_BITCMP1_B64 | |
| CInst_SOPC__S_SETVSKIP | |
| CInst_SOPC__S_SET_GPR_IDX_ON | |
| CInst_SOPC__S_CMP_EQ_U64 | |
| CInst_SOPC__S_CMP_LG_U64 | |
| CInst_SOPP__S_NOP | |
| CInst_SOPP__S_ENDPGM | |
| CInst_SOPP__S_BRANCH | |
| CInst_SOPP__S_WAKEUP | |
| CInst_SOPP__S_CBRANCH_SCC0 | |
| CInst_SOPP__S_CBRANCH_SCC1 | |
| CInst_SOPP__S_CBRANCH_VCCZ | |
| CInst_SOPP__S_CBRANCH_VCCNZ | |
| CInst_SOPP__S_CBRANCH_EXECZ | |
| CInst_SOPP__S_CBRANCH_EXECNZ | |
| CInst_SOPP__S_BARRIER | |
| CInst_SOPP__S_SETKILL | |
| CInst_SOPP__S_WAITCNT | |
| CInst_SOPP__S_SETHALT | |
| CInst_SOPP__S_SLEEP | |
| CInst_SOPP__S_SETPRIO | |
| CInst_SOPP__S_SENDMSG | |
| CInst_SOPP__S_SENDMSGHALT | |
| CInst_SOPP__S_TRAP | |
| CInst_SOPP__S_ICACHE_INV | |
| CInst_SOPP__S_INCPERFLEVEL | |
| CInst_SOPP__S_DECPERFLEVEL | |
| CInst_SOPP__S_TTRACEDATA | |
| CInst_SOPP__S_CBRANCH_CDBGSYS | |
| CInst_SOPP__S_CBRANCH_CDBGUSER | |
| CInst_SOPP__S_CBRANCH_CDBGSYS_OR_USER | |
| CInst_SOPP__S_CBRANCH_CDBGSYS_AND_USER | |
| CInst_SOPP__S_ENDPGM_SAVED | |
| CInst_SOPP__S_SET_GPR_IDX_OFF | |
| CInst_SOPP__S_SET_GPR_IDX_MODE | |
| CInst_SMEM__S_LOAD_DWORD | |
| CInst_SMEM__S_LOAD_DWORDX2 | |
| CInst_SMEM__S_LOAD_DWORDX4 | |
| CInst_SMEM__S_LOAD_DWORDX8 | |
| CInst_SMEM__S_LOAD_DWORDX16 | |
| CInst_SMEM__S_BUFFER_LOAD_DWORD | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX2 | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX4 | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX8 | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX16 | |
| CInst_SMEM__S_STORE_DWORD | |
| CInst_SMEM__S_STORE_DWORDX2 | |
| CInst_SMEM__S_STORE_DWORDX4 | |
| CInst_SMEM__S_BUFFER_STORE_DWORD | |
| CInst_SMEM__S_BUFFER_STORE_DWORDX2 | |
| CInst_SMEM__S_BUFFER_STORE_DWORDX4 | |
| CInst_SMEM__S_DCACHE_INV | |
| CInst_SMEM__S_DCACHE_WB | |
| CInst_SMEM__S_DCACHE_INV_VOL | |
| CInst_SMEM__S_DCACHE_WB_VOL | |
| CInst_SMEM__S_MEMTIME | |
| CInst_SMEM__S_MEMREALTIME | |
| CInst_SMEM__S_ATC_PROBE | |
| CInst_SMEM__S_ATC_PROBE_BUFFER | |
| CInst_VOP2__V_CNDMASK_B32 | |
| CInst_VOP2__V_ADD_F32 | |
| CInst_VOP2__V_SUB_F32 | |
| CInst_VOP2__V_SUBREV_F32 | |
| CInst_VOP2__V_MUL_LEGACY_F32 | |
| CInst_VOP2__V_MUL_F32 | |
| CInst_VOP2__V_MUL_I32_I24 | |
| CInst_VOP2__V_MUL_HI_I32_I24 | |
| CInst_VOP2__V_MUL_U32_U24 | |
| CInst_VOP2__V_MUL_HI_U32_U24 | |
| CInst_VOP2__V_MIN_F32 | |
| CInst_VOP2__V_MAX_F32 | |
| CInst_VOP2__V_MIN_I32 | |
| CInst_VOP2__V_MAX_I32 | |
| CInst_VOP2__V_MIN_U32 | |
| CInst_VOP2__V_MAX_U32 | |
| CInst_VOP2__V_LSHRREV_B32 | |
| CInst_VOP2__V_ASHRREV_I32 | |
| CInst_VOP2__V_LSHLREV_B32 | |
| CInst_VOP2__V_AND_B32 | |
| CInst_VOP2__V_OR_B32 | |
| CInst_VOP2__V_XOR_B32 | |
| CInst_VOP2__V_MAC_F32 | |
| CInst_VOP2__V_MADMK_F32 | |
| CInst_VOP2__V_MADAK_F32 | |
| CInst_VOP2__V_ADD_U32 | |
| CInst_VOP2__V_SUB_U32 | |
| CInst_VOP2__V_SUBREV_U32 | |
| CInst_VOP2__V_ADDC_U32 | |
| CInst_VOP2__V_SUBB_U32 | |
| CInst_VOP2__V_SUBBREV_U32 | |
| CInst_VOP2__V_ADD_F16 | |
| CInst_VOP2__V_SUB_F16 | |
| CInst_VOP2__V_SUBREV_F16 | |
| CInst_VOP2__V_MUL_F16 | |
| CInst_VOP2__V_MAC_F16 | |
| CInst_VOP2__V_MADMK_F16 | |
| CInst_VOP2__V_MADAK_F16 | |
| CInst_VOP2__V_ADD_U16 | |
| CInst_VOP2__V_SUB_U16 | |
| CInst_VOP2__V_SUBREV_U16 | |
| CInst_VOP2__V_MUL_LO_U16 | |
| CInst_VOP2__V_LSHLREV_B16 | |
| CInst_VOP2__V_LSHRREV_B16 | |
| CInst_VOP2__V_ASHRREV_I16 | |
| CInst_VOP2__V_MAX_F16 | |
| CInst_VOP2__V_MIN_F16 | |
| CInst_VOP2__V_MAX_U16 | |
| CInst_VOP2__V_MAX_I16 | |
| CInst_VOP2__V_MIN_U16 | |
| CInst_VOP2__V_MIN_I16 | |
| CInst_VOP2__V_LDEXP_F16 | |
| CInst_VOP1__V_NOP | |
| CInst_VOP1__V_MOV_B32 | |
| CInst_VOP1__V_READFIRSTLANE_B32 | |
| CInst_VOP1__V_CVT_I32_F64 | |
| CInst_VOP1__V_CVT_F64_I32 | |
| CInst_VOP1__V_CVT_F32_I32 | |
| CInst_VOP1__V_CVT_F32_U32 | |
| CInst_VOP1__V_CVT_U32_F32 | |
| CInst_VOP1__V_CVT_I32_F32 | |
| CInst_VOP1__V_MOV_FED_B32 | |
| CInst_VOP1__V_CVT_F16_F32 | |
| CInst_VOP1__V_CVT_F32_F16 | |
| CInst_VOP1__V_CVT_RPI_I32_F32 | |
| CInst_VOP1__V_CVT_FLR_I32_F32 | |
| CInst_VOP1__V_CVT_OFF_F32_I4 | |
| CInst_VOP1__V_CVT_F32_F64 | |
| CInst_VOP1__V_CVT_F64_F32 | |
| CInst_VOP1__V_CVT_F32_UBYTE0 | |
| CInst_VOP1__V_CVT_F32_UBYTE1 | |
| CInst_VOP1__V_CVT_F32_UBYTE2 | |
| CInst_VOP1__V_CVT_F32_UBYTE3 | |
| CInst_VOP1__V_CVT_U32_F64 | |
| CInst_VOP1__V_CVT_F64_U32 | |
| CInst_VOP1__V_TRUNC_F64 | |
| CInst_VOP1__V_CEIL_F64 | |
| CInst_VOP1__V_RNDNE_F64 | |
| CInst_VOP1__V_FLOOR_F64 | |
| CInst_VOP1__V_FRACT_F32 | |
| CInst_VOP1__V_TRUNC_F32 | |
| CInst_VOP1__V_CEIL_F32 | |
| CInst_VOP1__V_RNDNE_F32 | |
| CInst_VOP1__V_FLOOR_F32 | |
| CInst_VOP1__V_EXP_F32 | |
| CInst_VOP1__V_LOG_F32 | |
| CInst_VOP1__V_RCP_F32 | |
| CInst_VOP1__V_RCP_IFLAG_F32 | |
| CInst_VOP1__V_RSQ_F32 | |
| CInst_VOP1__V_RCP_F64 | |
| CInst_VOP1__V_RSQ_F64 | |
| CInst_VOP1__V_SQRT_F32 | |
| CInst_VOP1__V_SQRT_F64 | |
| CInst_VOP1__V_SIN_F32 | |
| CInst_VOP1__V_COS_F32 | |
| CInst_VOP1__V_NOT_B32 | |
| CInst_VOP1__V_BFREV_B32 | |
| CInst_VOP1__V_FFBH_U32 | |
| CInst_VOP1__V_FFBL_B32 | |
| CInst_VOP1__V_FFBH_I32 | |
| CInst_VOP1__V_FREXP_EXP_I32_F64 | |
| CInst_VOP1__V_FREXP_MANT_F64 | |
| CInst_VOP1__V_FRACT_F64 | |
| CInst_VOP1__V_FREXP_EXP_I32_F32 | |
| CInst_VOP1__V_FREXP_MANT_F32 | |
| CInst_VOP1__V_CLREXCP | |
| CInst_VOP1__V_CVT_F16_U16 | |
| CInst_VOP1__V_CVT_F16_I16 | |
| CInst_VOP1__V_CVT_U16_F16 | |
| CInst_VOP1__V_CVT_I16_F16 | |
| CInst_VOP1__V_RCP_F16 | |
| CInst_VOP1__V_SQRT_F16 | |
| CInst_VOP1__V_RSQ_F16 | |
| CInst_VOP1__V_LOG_F16 | |
| CInst_VOP1__V_EXP_F16 | |
| CInst_VOP1__V_FREXP_MANT_F16 | |
| CInst_VOP1__V_FREXP_EXP_I16_F16 | |
| CInst_VOP1__V_FLOOR_F16 | |
| CInst_VOP1__V_CEIL_F16 | |
| CInst_VOP1__V_TRUNC_F16 | |
| CInst_VOP1__V_RNDNE_F16 | |
| CInst_VOP1__V_FRACT_F16 | |
| CInst_VOP1__V_SIN_F16 | |
| CInst_VOP1__V_COS_F16 | |
| CInst_VOP1__V_EXP_LEGACY_F32 | |
| CInst_VOP1__V_LOG_LEGACY_F32 | |
| CInst_VOPC__V_CMP_CLASS_F32 | |
| CInst_VOPC__V_CMPX_CLASS_F32 | |
| CInst_VOPC__V_CMP_CLASS_F64 | |
| CInst_VOPC__V_CMPX_CLASS_F64 | |
| CInst_VOPC__V_CMP_CLASS_F16 | |
| CInst_VOPC__V_CMPX_CLASS_F16 | |
| CInst_VOPC__V_CMP_F_F16 | |
| CInst_VOPC__V_CMP_LT_F16 | |
| CInst_VOPC__V_CMP_EQ_F16 | |
| CInst_VOPC__V_CMP_LE_F16 | |
| CInst_VOPC__V_CMP_GT_F16 | |
| CInst_VOPC__V_CMP_LG_F16 | |
| CInst_VOPC__V_CMP_GE_F16 | |
| CInst_VOPC__V_CMP_O_F16 | |
| CInst_VOPC__V_CMP_U_F16 | |
| CInst_VOPC__V_CMP_NGE_F16 | |
| CInst_VOPC__V_CMP_NLG_F16 | |
| CInst_VOPC__V_CMP_NGT_F16 | |
| CInst_VOPC__V_CMP_NLE_F16 | |
| CInst_VOPC__V_CMP_NEQ_F16 | |
| CInst_VOPC__V_CMP_NLT_F16 | |
| CInst_VOPC__V_CMP_TRU_F16 | |
| CInst_VOPC__V_CMPX_F_F16 | |
| CInst_VOPC__V_CMPX_LT_F16 | |
| CInst_VOPC__V_CMPX_EQ_F16 | |
| CInst_VOPC__V_CMPX_LE_F16 | |
| CInst_VOPC__V_CMPX_GT_F16 | |
| CInst_VOPC__V_CMPX_LG_F16 | |
| CInst_VOPC__V_CMPX_GE_F16 | |
| CInst_VOPC__V_CMPX_O_F16 | |
| CInst_VOPC__V_CMPX_U_F16 | |
| CInst_VOPC__V_CMPX_NGE_F16 | |
| CInst_VOPC__V_CMPX_NLG_F16 | |
| CInst_VOPC__V_CMPX_NGT_F16 | |
| CInst_VOPC__V_CMPX_NLE_F16 | |
| CInst_VOPC__V_CMPX_NEQ_F16 | |
| CInst_VOPC__V_CMPX_NLT_F16 | |
| CInst_VOPC__V_CMPX_TRU_F16 | |
| CInst_VOPC__V_CMP_F_F32 | |
| CInst_VOPC__V_CMP_LT_F32 | |
| CInst_VOPC__V_CMP_EQ_F32 | |
| CInst_VOPC__V_CMP_LE_F32 | |
| CInst_VOPC__V_CMP_GT_F32 | |
| CInst_VOPC__V_CMP_LG_F32 | |
| CInst_VOPC__V_CMP_GE_F32 | |
| CInst_VOPC__V_CMP_O_F32 | |
| CInst_VOPC__V_CMP_U_F32 | |
| CInst_VOPC__V_CMP_NGE_F32 | |
| CInst_VOPC__V_CMP_NLG_F32 | |
| CInst_VOPC__V_CMP_NGT_F32 | |
| CInst_VOPC__V_CMP_NLE_F32 | |
| CInst_VOPC__V_CMP_NEQ_F32 | |
| CInst_VOPC__V_CMP_NLT_F32 | |
| CInst_VOPC__V_CMP_TRU_F32 | |
| CInst_VOPC__V_CMPX_F_F32 | |
| CInst_VOPC__V_CMPX_LT_F32 | |
| CInst_VOPC__V_CMPX_EQ_F32 | |
| CInst_VOPC__V_CMPX_LE_F32 | |
| CInst_VOPC__V_CMPX_GT_F32 | |
| CInst_VOPC__V_CMPX_LG_F32 | |
| CInst_VOPC__V_CMPX_GE_F32 | |
| CInst_VOPC__V_CMPX_O_F32 | |
| CInst_VOPC__V_CMPX_U_F32 | |
| CInst_VOPC__V_CMPX_NGE_F32 | |
| CInst_VOPC__V_CMPX_NLG_F32 | |
| CInst_VOPC__V_CMPX_NGT_F32 | |
| CInst_VOPC__V_CMPX_NLE_F32 | |
| CInst_VOPC__V_CMPX_NEQ_F32 | |
| CInst_VOPC__V_CMPX_NLT_F32 | |
| CInst_VOPC__V_CMPX_TRU_F32 | |
| CInst_VOPC__V_CMP_F_F64 | |
| CInst_VOPC__V_CMP_LT_F64 | |
| CInst_VOPC__V_CMP_EQ_F64 | |
| CInst_VOPC__V_CMP_LE_F64 | |
| CInst_VOPC__V_CMP_GT_F64 | |
| CInst_VOPC__V_CMP_LG_F64 | |
| CInst_VOPC__V_CMP_GE_F64 | |
| CInst_VOPC__V_CMP_O_F64 | |
| CInst_VOPC__V_CMP_U_F64 | |
| CInst_VOPC__V_CMP_NGE_F64 | |
| CInst_VOPC__V_CMP_NLG_F64 | |
| CInst_VOPC__V_CMP_NGT_F64 | |
| CInst_VOPC__V_CMP_NLE_F64 | |
| CInst_VOPC__V_CMP_NEQ_F64 | |
| CInst_VOPC__V_CMP_NLT_F64 | |
| CInst_VOPC__V_CMP_TRU_F64 | |
| CInst_VOPC__V_CMPX_F_F64 | |
| CInst_VOPC__V_CMPX_LT_F64 | |
| CInst_VOPC__V_CMPX_EQ_F64 | |
| CInst_VOPC__V_CMPX_LE_F64 | |
| CInst_VOPC__V_CMPX_GT_F64 | |
| CInst_VOPC__V_CMPX_LG_F64 | |
| CInst_VOPC__V_CMPX_GE_F64 | |
| CInst_VOPC__V_CMPX_O_F64 | |
| CInst_VOPC__V_CMPX_U_F64 | |
| CInst_VOPC__V_CMPX_NGE_F64 | |
| CInst_VOPC__V_CMPX_NLG_F64 | |
| CInst_VOPC__V_CMPX_NGT_F64 | |
| CInst_VOPC__V_CMPX_NLE_F64 | |
| CInst_VOPC__V_CMPX_NEQ_F64 | |
| CInst_VOPC__V_CMPX_NLT_F64 | |
| CInst_VOPC__V_CMPX_TRU_F64 | |
| CInst_VOPC__V_CMP_F_I16 | |
| CInst_VOPC__V_CMP_LT_I16 | |
| CInst_VOPC__V_CMP_EQ_I16 | |
| CInst_VOPC__V_CMP_LE_I16 | |
| CInst_VOPC__V_CMP_GT_I16 | |
| CInst_VOPC__V_CMP_NE_I16 | |
| CInst_VOPC__V_CMP_GE_I16 | |
| CInst_VOPC__V_CMP_T_I16 | |
| CInst_VOPC__V_CMP_F_U16 | |
| CInst_VOPC__V_CMP_LT_U16 | |
| CInst_VOPC__V_CMP_EQ_U16 | |
| CInst_VOPC__V_CMP_LE_U16 | |
| CInst_VOPC__V_CMP_GT_U16 | |
| CInst_VOPC__V_CMP_NE_U16 | |
| CInst_VOPC__V_CMP_GE_U16 | |
| CInst_VOPC__V_CMP_T_U16 | |
| CInst_VOPC__V_CMPX_F_I16 | |
| CInst_VOPC__V_CMPX_LT_I16 | |
| CInst_VOPC__V_CMPX_EQ_I16 | |
| CInst_VOPC__V_CMPX_LE_I16 | |
| CInst_VOPC__V_CMPX_GT_I16 | |
| CInst_VOPC__V_CMPX_NE_I16 | |
| CInst_VOPC__V_CMPX_GE_I16 | |
| CInst_VOPC__V_CMPX_T_I16 | |
| CInst_VOPC__V_CMPX_F_U16 | |
| CInst_VOPC__V_CMPX_LT_U16 | |
| CInst_VOPC__V_CMPX_EQ_U16 | |
| CInst_VOPC__V_CMPX_LE_U16 | |
| CInst_VOPC__V_CMPX_GT_U16 | |
| CInst_VOPC__V_CMPX_NE_U16 | |
| CInst_VOPC__V_CMPX_GE_U16 | |
| CInst_VOPC__V_CMPX_T_U16 | |
| CInst_VOPC__V_CMP_F_I32 | |
| CInst_VOPC__V_CMP_LT_I32 | |
| CInst_VOPC__V_CMP_EQ_I32 | |
| CInst_VOPC__V_CMP_LE_I32 | |
| CInst_VOPC__V_CMP_GT_I32 | |
| CInst_VOPC__V_CMP_NE_I32 | |
| CInst_VOPC__V_CMP_GE_I32 | |
| CInst_VOPC__V_CMP_T_I32 | |
| CInst_VOPC__V_CMP_F_U32 | |
| CInst_VOPC__V_CMP_LT_U32 | |
| CInst_VOPC__V_CMP_EQ_U32 | |
| CInst_VOPC__V_CMP_LE_U32 | |
| CInst_VOPC__V_CMP_GT_U32 | |
| CInst_VOPC__V_CMP_NE_U32 | |
| CInst_VOPC__V_CMP_GE_U32 | |
| CInst_VOPC__V_CMP_T_U32 | |
| CInst_VOPC__V_CMPX_F_I32 | |
| CInst_VOPC__V_CMPX_LT_I32 | |
| CInst_VOPC__V_CMPX_EQ_I32 | |
| CInst_VOPC__V_CMPX_LE_I32 | |
| CInst_VOPC__V_CMPX_GT_I32 | |
| CInst_VOPC__V_CMPX_NE_I32 | |
| CInst_VOPC__V_CMPX_GE_I32 | |
| CInst_VOPC__V_CMPX_T_I32 | |
| CInst_VOPC__V_CMPX_F_U32 | |
| CInst_VOPC__V_CMPX_LT_U32 | |
| CInst_VOPC__V_CMPX_EQ_U32 | |
| CInst_VOPC__V_CMPX_LE_U32 | |
| CInst_VOPC__V_CMPX_GT_U32 | |
| CInst_VOPC__V_CMPX_NE_U32 | |
| CInst_VOPC__V_CMPX_GE_U32 | |
| CInst_VOPC__V_CMPX_T_U32 | |
| CInst_VOPC__V_CMP_F_I64 | |
| CInst_VOPC__V_CMP_LT_I64 | |
| CInst_VOPC__V_CMP_EQ_I64 | |
| CInst_VOPC__V_CMP_LE_I64 | |
| CInst_VOPC__V_CMP_GT_I64 | |
| CInst_VOPC__V_CMP_NE_I64 | |
| CInst_VOPC__V_CMP_GE_I64 | |
| CInst_VOPC__V_CMP_T_I64 | |
| CInst_VOPC__V_CMP_F_U64 | |
| CInst_VOPC__V_CMP_LT_U64 | |
| CInst_VOPC__V_CMP_EQ_U64 | |
| CInst_VOPC__V_CMP_LE_U64 | |
| CInst_VOPC__V_CMP_GT_U64 | |
| CInst_VOPC__V_CMP_NE_U64 | |
| CInst_VOPC__V_CMP_GE_U64 | |
| CInst_VOPC__V_CMP_T_U64 | |
| CInst_VOPC__V_CMPX_F_I64 | |
| CInst_VOPC__V_CMPX_LT_I64 | |
| CInst_VOPC__V_CMPX_EQ_I64 | |
| CInst_VOPC__V_CMPX_LE_I64 | |
| CInst_VOPC__V_CMPX_GT_I64 | |
| CInst_VOPC__V_CMPX_NE_I64 | |
| CInst_VOPC__V_CMPX_GE_I64 | |
| CInst_VOPC__V_CMPX_T_I64 | |
| CInst_VOPC__V_CMPX_F_U64 | |
| CInst_VOPC__V_CMPX_LT_U64 | |
| CInst_VOPC__V_CMPX_EQ_U64 | |
| CInst_VOPC__V_CMPX_LE_U64 | |
| CInst_VOPC__V_CMPX_GT_U64 | |
| CInst_VOPC__V_CMPX_NE_U64 | |
| CInst_VOPC__V_CMPX_GE_U64 | |
| CInst_VOPC__V_CMPX_T_U64 | |
| CInst_VINTRP__V_INTERP_P1_F32 | |
| CInst_VINTRP__V_INTERP_P2_F32 | |
| CInst_VINTRP__V_INTERP_MOV_F32 | |
| CInst_VOP3__V_CMP_CLASS_F32 | |
| CInst_VOP3__V_CMPX_CLASS_F32 | |
| CInst_VOP3__V_CMP_CLASS_F64 | |
| CInst_VOP3__V_CMPX_CLASS_F64 | |
| CInst_VOP3__V_CMP_CLASS_F16 | |
| CInst_VOP3__V_CMPX_CLASS_F16 | |
| CInst_VOP3__V_CMP_F_F16 | |
| CInst_VOP3__V_CMP_LT_F16 | |
| CInst_VOP3__V_CMP_EQ_F16 | |
| CInst_VOP3__V_CMP_LE_F16 | |
| CInst_VOP3__V_CMP_GT_F16 | |
| CInst_VOP3__V_CMP_LG_F16 | |
| CInst_VOP3__V_CMP_GE_F16 | |
| CInst_VOP3__V_CMP_O_F16 | |
| CInst_VOP3__V_CMP_U_F16 | |
| CInst_VOP3__V_CMP_NGE_F16 | |
| CInst_VOP3__V_CMP_NLG_F16 | |
| CInst_VOP3__V_CMP_NGT_F16 | |
| CInst_VOP3__V_CMP_NLE_F16 | |
| CInst_VOP3__V_CMP_NEQ_F16 | |
| CInst_VOP3__V_CMP_NLT_F16 | |
| CInst_VOP3__V_CMP_TRU_F16 | |
| CInst_VOP3__V_CMPX_F_F16 | |
| CInst_VOP3__V_CMPX_LT_F16 | |
| CInst_VOP3__V_CMPX_EQ_F16 | |
| CInst_VOP3__V_CMPX_LE_F16 | |
| CInst_VOP3__V_CMPX_GT_F16 | |
| CInst_VOP3__V_CMPX_LG_F16 | |
| CInst_VOP3__V_CMPX_GE_F16 | |
| CInst_VOP3__V_CMPX_O_F16 | |
| CInst_VOP3__V_CMPX_U_F16 | |
| CInst_VOP3__V_CMPX_NGE_F16 | |
| CInst_VOP3__V_CMPX_NLG_F16 | |
| CInst_VOP3__V_CMPX_NGT_F16 | |
| CInst_VOP3__V_CMPX_NLE_F16 | |
| CInst_VOP3__V_CMPX_NEQ_F16 | |
| CInst_VOP3__V_CMPX_NLT_F16 | |
| CInst_VOP3__V_CMPX_TRU_F16 | |
| CInst_VOP3__V_CMP_F_F32 | |
| CInst_VOP3__V_CMP_LT_F32 | |
| CInst_VOP3__V_CMP_EQ_F32 | |
| CInst_VOP3__V_CMP_LE_F32 | |
| CInst_VOP3__V_CMP_GT_F32 | |
| CInst_VOP3__V_CMP_LG_F32 | |
| CInst_VOP3__V_CMP_GE_F32 | |
| CInst_VOP3__V_CMP_O_F32 | |
| CInst_VOP3__V_CMP_U_F32 | |
| CInst_VOP3__V_CMP_NGE_F32 | |
| CInst_VOP3__V_CMP_NLG_F32 | |
| CInst_VOP3__V_CMP_NGT_F32 | |
| CInst_VOP3__V_CMP_NLE_F32 | |
| CInst_VOP3__V_CMP_NEQ_F32 | |
| CInst_VOP3__V_CMP_NLT_F32 | |
| CInst_VOP3__V_CMP_TRU_F32 | |
| CInst_VOP3__V_CMPX_F_F32 | |
| CInst_VOP3__V_CMPX_LT_F32 | |
| CInst_VOP3__V_CMPX_EQ_F32 | |
| CInst_VOP3__V_CMPX_LE_F32 | |
| CInst_VOP3__V_CMPX_GT_F32 | |
| CInst_VOP3__V_CMPX_LG_F32 | |
| CInst_VOP3__V_CMPX_GE_F32 | |
| CInst_VOP3__V_CMPX_O_F32 | |
| CInst_VOP3__V_CMPX_U_F32 | |
| CInst_VOP3__V_CMPX_NGE_F32 | |
| CInst_VOP3__V_CMPX_NLG_F32 | |
| CInst_VOP3__V_CMPX_NGT_F32 | |
| CInst_VOP3__V_CMPX_NLE_F32 | |
| CInst_VOP3__V_CMPX_NEQ_F32 | |
| CInst_VOP3__V_CMPX_NLT_F32 | |
| CInst_VOP3__V_CMPX_TRU_F32 | |
| CInst_VOP3__V_CMP_F_F64 | |
| CInst_VOP3__V_CMP_LT_F64 | |
| CInst_VOP3__V_CMP_EQ_F64 | |
| CInst_VOP3__V_CMP_LE_F64 | |
| CInst_VOP3__V_CMP_GT_F64 | |
| CInst_VOP3__V_CMP_LG_F64 | |
| CInst_VOP3__V_CMP_GE_F64 | |
| CInst_VOP3__V_CMP_O_F64 | |
| CInst_VOP3__V_CMP_U_F64 | |
| CInst_VOP3__V_CMP_NGE_F64 | |
| CInst_VOP3__V_CMP_NLG_F64 | |
| CInst_VOP3__V_CMP_NGT_F64 | |
| CInst_VOP3__V_CMP_NLE_F64 | |
| CInst_VOP3__V_CMP_NEQ_F64 | |
| CInst_VOP3__V_CMP_NLT_F64 | |
| CInst_VOP3__V_CMP_TRU_F64 | |
| CInst_VOP3__V_CMPX_F_F64 | |
| CInst_VOP3__V_CMPX_LT_F64 | |
| CInst_VOP3__V_CMPX_EQ_F64 | |
| CInst_VOP3__V_CMPX_LE_F64 | |
| CInst_VOP3__V_CMPX_GT_F64 | |
| CInst_VOP3__V_CMPX_LG_F64 | |
| CInst_VOP3__V_CMPX_GE_F64 | |
| CInst_VOP3__V_CMPX_O_F64 | |
| CInst_VOP3__V_CMPX_U_F64 | |
| CInst_VOP3__V_CMPX_NGE_F64 | |
| CInst_VOP3__V_CMPX_NLG_F64 | |
| CInst_VOP3__V_CMPX_NGT_F64 | |
| CInst_VOP3__V_CMPX_NLE_F64 | |
| CInst_VOP3__V_CMPX_NEQ_F64 | |
| CInst_VOP3__V_CMPX_NLT_F64 | |
| CInst_VOP3__V_CMPX_TRU_F64 | |
| CInst_VOP3__V_CMP_F_I16 | |
| CInst_VOP3__V_CMP_LT_I16 | |
| CInst_VOP3__V_CMP_EQ_I16 | |
| CInst_VOP3__V_CMP_LE_I16 | |
| CInst_VOP3__V_CMP_GT_I16 | |
| CInst_VOP3__V_CMP_NE_I16 | |
| CInst_VOP3__V_CMP_GE_I16 | |
| CInst_VOP3__V_CMP_T_I16 | |
| CInst_VOP3__V_CMP_F_U16 | |
| CInst_VOP3__V_CMP_LT_U16 | |
| CInst_VOP3__V_CMP_EQ_U16 | |
| CInst_VOP3__V_CMP_LE_U16 | |
| CInst_VOP3__V_CMP_GT_U16 | |
| CInst_VOP3__V_CMP_NE_U16 | |
| CInst_VOP3__V_CMP_GE_U16 | |
| CInst_VOP3__V_CMP_T_U16 | |
| CInst_VOP3__V_CMPX_F_I16 | |
| CInst_VOP3__V_CMPX_LT_I16 | |
| CInst_VOP3__V_CMPX_EQ_I16 | |
| CInst_VOP3__V_CMPX_LE_I16 | |
| CInst_VOP3__V_CMPX_GT_I16 | |
| CInst_VOP3__V_CMPX_NE_I16 | |
| CInst_VOP3__V_CMPX_GE_I16 | |
| CInst_VOP3__V_CMPX_T_I16 | |
| CInst_VOP3__V_CMPX_F_U16 | |
| CInst_VOP3__V_CMPX_LT_U16 | |
| CInst_VOP3__V_CMPX_EQ_U16 | |
| CInst_VOP3__V_CMPX_LE_U16 | |
| CInst_VOP3__V_CMPX_GT_U16 | |
| CInst_VOP3__V_CMPX_NE_U16 | |
| CInst_VOP3__V_CMPX_GE_U16 | |
| CInst_VOP3__V_CMPX_T_U16 | |
| CInst_VOP3__V_CMP_F_I32 | |
| CInst_VOP3__V_CMP_LT_I32 | |
| CInst_VOP3__V_CMP_EQ_I32 | |
| CInst_VOP3__V_CMP_LE_I32 | |
| CInst_VOP3__V_CMP_GT_I32 | |
| CInst_VOP3__V_CMP_NE_I32 | |
| CInst_VOP3__V_CMP_GE_I32 | |
| CInst_VOP3__V_CMP_T_I32 | |
| CInst_VOP3__V_CMP_F_U32 | |
| CInst_VOP3__V_CMP_LT_U32 | |
| CInst_VOP3__V_CMP_EQ_U32 | |
| CInst_VOP3__V_CMP_LE_U32 | |
| CInst_VOP3__V_CMP_GT_U32 | |
| CInst_VOP3__V_CMP_NE_U32 | |
| CInst_VOP3__V_CMP_GE_U32 | |
| CInst_VOP3__V_CMP_T_U32 | |
| CInst_VOP3__V_CMPX_F_I32 | |
| CInst_VOP3__V_CMPX_LT_I32 | |
| CInst_VOP3__V_CMPX_EQ_I32 | |
| CInst_VOP3__V_CMPX_LE_I32 | |
| CInst_VOP3__V_CMPX_GT_I32 | |
| CInst_VOP3__V_CMPX_NE_I32 | |
| CInst_VOP3__V_CMPX_GE_I32 | |
| CInst_VOP3__V_CMPX_T_I32 | |
| CInst_VOP3__V_CMPX_F_U32 | |
| CInst_VOP3__V_CMPX_LT_U32 | |
| CInst_VOP3__V_CMPX_EQ_U32 | |
| CInst_VOP3__V_CMPX_LE_U32 | |
| CInst_VOP3__V_CMPX_GT_U32 | |
| CInst_VOP3__V_CMPX_NE_U32 | |
| CInst_VOP3__V_CMPX_GE_U32 | |
| CInst_VOP3__V_CMPX_T_U32 | |
| CInst_VOP3__V_CMP_F_I64 | |
| CInst_VOP3__V_CMP_LT_I64 | |
| CInst_VOP3__V_CMP_EQ_I64 | |
| CInst_VOP3__V_CMP_LE_I64 | |
| CInst_VOP3__V_CMP_GT_I64 | |
| CInst_VOP3__V_CMP_NE_I64 | |
| CInst_VOP3__V_CMP_GE_I64 | |
| CInst_VOP3__V_CMP_T_I64 | |
| CInst_VOP3__V_CMP_F_U64 | |
| CInst_VOP3__V_CMP_LT_U64 | |
| CInst_VOP3__V_CMP_EQ_U64 | |
| CInst_VOP3__V_CMP_LE_U64 | |
| CInst_VOP3__V_CMP_GT_U64 | |
| CInst_VOP3__V_CMP_NE_U64 | |
| CInst_VOP3__V_CMP_GE_U64 | |
| CInst_VOP3__V_CMP_T_U64 | |
| CInst_VOP3__V_CMPX_F_I64 | |
| CInst_VOP3__V_CMPX_LT_I64 | |
| CInst_VOP3__V_CMPX_EQ_I64 | |
| CInst_VOP3__V_CMPX_LE_I64 | |
| CInst_VOP3__V_CMPX_GT_I64 | |
| CInst_VOP3__V_CMPX_NE_I64 | |
| CInst_VOP3__V_CMPX_GE_I64 | |
| CInst_VOP3__V_CMPX_T_I64 | |
| CInst_VOP3__V_CMPX_F_U64 | |
| CInst_VOP3__V_CMPX_LT_U64 | |
| CInst_VOP3__V_CMPX_EQ_U64 | |
| CInst_VOP3__V_CMPX_LE_U64 | |
| CInst_VOP3__V_CMPX_GT_U64 | |
| CInst_VOP3__V_CMPX_NE_U64 | |
| CInst_VOP3__V_CMPX_GE_U64 | |
| CInst_VOP3__V_CMPX_T_U64 | |
| CInst_VOP3__V_CNDMASK_B32 | |
| CInst_VOP3__V_ADD_F32 | |
| CInst_VOP3__V_SUB_F32 | |
| CInst_VOP3__V_SUBREV_F32 | |
| CInst_VOP3__V_MUL_LEGACY_F32 | |
| CInst_VOP3__V_MUL_F32 | |
| CInst_VOP3__V_MUL_I32_I24 | |
| CInst_VOP3__V_MUL_HI_I32_I24 | |
| CInst_VOP3__V_MUL_U32_U24 | |
| CInst_VOP3__V_MUL_HI_U32_U24 | |
| CInst_VOP3__V_MIN_F32 | |
| CInst_VOP3__V_MAX_F32 | |
| CInst_VOP3__V_MIN_I32 | |
| CInst_VOP3__V_MAX_I32 | |
| CInst_VOP3__V_MIN_U32 | |
| CInst_VOP3__V_MAX_U32 | |
| CInst_VOP3__V_LSHRREV_B32 | |
| CInst_VOP3__V_ASHRREV_I32 | |
| CInst_VOP3__V_LSHLREV_B32 | |
| CInst_VOP3__V_AND_B32 | |
| CInst_VOP3__V_OR_B32 | |
| CInst_VOP3__V_XOR_B32 | |
| CInst_VOP3__V_MAC_F32 | |
| CInst_VOP3__V_ADD_U32 | |
| CInst_VOP3__V_SUB_U32 | |
| CInst_VOP3__V_SUBREV_U32 | |
| CInst_VOP3__V_ADDC_U32 | |
| CInst_VOP3__V_SUBB_U32 | |
| CInst_VOP3__V_SUBBREV_U32 | |
| CInst_VOP3__V_ADD_F16 | |
| CInst_VOP3__V_SUB_F16 | |
| CInst_VOP3__V_SUBREV_F16 | |
| CInst_VOP3__V_MUL_F16 | |
| CInst_VOP3__V_MAC_F16 | |
| CInst_VOP3__V_ADD_U16 | |
| CInst_VOP3__V_SUB_U16 | |
| CInst_VOP3__V_SUBREV_U16 | |
| CInst_VOP3__V_MUL_LO_U16 | |
| CInst_VOP3__V_LSHLREV_B16 | |
| CInst_VOP3__V_LSHRREV_B16 | |
| CInst_VOP3__V_ASHRREV_I16 | |
| CInst_VOP3__V_MAX_F16 | |
| CInst_VOP3__V_MIN_F16 | |
| CInst_VOP3__V_MAX_U16 | |
| CInst_VOP3__V_MAX_I16 | |
| CInst_VOP3__V_MIN_U16 | |
| CInst_VOP3__V_MIN_I16 | |
| CInst_VOP3__V_LDEXP_F16 | |
| CInst_VOP3__V_NOP | |
| CInst_VOP3__V_MOV_B32 | |
| CInst_VOP3__V_CVT_I32_F64 | |
| CInst_VOP3__V_CVT_F64_I32 | |
| CInst_VOP3__V_CVT_F32_I32 | |
| CInst_VOP3__V_CVT_F32_U32 | |
| CInst_VOP3__V_CVT_U32_F32 | |
| CInst_VOP3__V_CVT_I32_F32 | |
| CInst_VOP3__V_MOV_FED_B32 | |
| CInst_VOP3__V_CVT_F16_F32 | |
| CInst_VOP3__V_CVT_F32_F16 | |
| CInst_VOP3__V_CVT_RPI_I32_F32 | |
| CInst_VOP3__V_CVT_FLR_I32_F32 | |
| CInst_VOP3__V_CVT_OFF_F32_I4 | |
| CInst_VOP3__V_CVT_F32_F64 | |
| CInst_VOP3__V_CVT_F64_F32 | |
| CInst_VOP3__V_CVT_F32_UBYTE0 | |
| CInst_VOP3__V_CVT_F32_UBYTE1 | |
| CInst_VOP3__V_CVT_F32_UBYTE2 | |
| CInst_VOP3__V_CVT_F32_UBYTE3 | |
| CInst_VOP3__V_CVT_U32_F64 | |
| CInst_VOP3__V_CVT_F64_U32 | |
| CInst_VOP3__V_TRUNC_F64 | |
| CInst_VOP3__V_CEIL_F64 | |
| CInst_VOP3__V_RNDNE_F64 | |
| CInst_VOP3__V_FLOOR_F64 | |
| CInst_VOP3__V_FRACT_F32 | |
| CInst_VOP3__V_TRUNC_F32 | |
| CInst_VOP3__V_CEIL_F32 | |
| CInst_VOP3__V_RNDNE_F32 | |
| CInst_VOP3__V_FLOOR_F32 | |
| CInst_VOP3__V_EXP_F32 | |
| CInst_VOP3__V_LOG_F32 | |
| CInst_VOP3__V_RCP_F32 | |
| CInst_VOP3__V_RCP_IFLAG_F32 | |
| CInst_VOP3__V_RSQ_F32 | |
| CInst_VOP3__V_RCP_F64 | |
| CInst_VOP3__V_RSQ_F64 | |
| CInst_VOP3__V_SQRT_F32 | |
| CInst_VOP3__V_SQRT_F64 | |
| CInst_VOP3__V_SIN_F32 | |
| CInst_VOP3__V_COS_F32 | |
| CInst_VOP3__V_NOT_B32 | |
| CInst_VOP3__V_BFREV_B32 | |
| CInst_VOP3__V_FFBH_U32 | |
| CInst_VOP3__V_FFBL_B32 | |
| CInst_VOP3__V_FFBH_I32 | |
| CInst_VOP3__V_FREXP_EXP_I32_F64 | |
| CInst_VOP3__V_FREXP_MANT_F64 | |
| CInst_VOP3__V_FRACT_F64 | |
| CInst_VOP3__V_FREXP_EXP_I32_F32 | |
| CInst_VOP3__V_FREXP_MANT_F32 | |
| CInst_VOP3__V_CLREXCP | |
| CInst_VOP3__V_CVT_F16_U16 | |
| CInst_VOP3__V_CVT_F16_I16 | |
| CInst_VOP3__V_CVT_U16_F16 | |
| CInst_VOP3__V_CVT_I16_F16 | |
| CInst_VOP3__V_RCP_F16 | |
| CInst_VOP3__V_SQRT_F16 | |
| CInst_VOP3__V_RSQ_F16 | |
| CInst_VOP3__V_LOG_F16 | |
| CInst_VOP3__V_EXP_F16 | |
| CInst_VOP3__V_FREXP_MANT_F16 | |
| CInst_VOP3__V_FREXP_EXP_I16_F16 | |
| CInst_VOP3__V_FLOOR_F16 | |
| CInst_VOP3__V_CEIL_F16 | |
| CInst_VOP3__V_TRUNC_F16 | |
| CInst_VOP3__V_RNDNE_F16 | |
| CInst_VOP3__V_FRACT_F16 | |
| CInst_VOP3__V_SIN_F16 | |
| CInst_VOP3__V_COS_F16 | |
| CInst_VOP3__V_EXP_LEGACY_F32 | |
| CInst_VOP3__V_LOG_LEGACY_F32 | |
| CInst_VOP3__V_MAD_LEGACY_F32 | |
| CInst_VOP3__V_MAD_F32 | |
| CInst_VOP3__V_MAD_I32_I24 | |
| CInst_VOP3__V_MAD_U32_U24 | |
| CInst_VOP3__V_CUBEID_F32 | |
| CInst_VOP3__V_CUBESC_F32 | |
| CInst_VOP3__V_CUBETC_F32 | |
| CInst_VOP3__V_CUBEMA_F32 | |
| CInst_VOP3__V_BFE_U32 | |
| CInst_VOP3__V_BFE_I32 | |
| CInst_VOP3__V_BFI_B32 | |
| CInst_VOP3__V_FMA_F32 | |
| CInst_VOP3__V_FMA_F64 | |
| CInst_VOP3__V_LERP_U8 | |
| CInst_VOP3__V_ALIGNBIT_B32 | |
| CInst_VOP3__V_ALIGNBYTE_B32 | |
| CInst_VOP3__V_MIN3_F32 | |
| CInst_VOP3__V_MIN3_I32 | |
| CInst_VOP3__V_MIN3_U32 | |
| CInst_VOP3__V_MAX3_F32 | |
| CInst_VOP3__V_MAX3_I32 | |
| CInst_VOP3__V_MAX3_U32 | |
| CInst_VOP3__V_MED3_F32 | |
| CInst_VOP3__V_MED3_I32 | |
| CInst_VOP3__V_MED3_U32 | |
| CInst_VOP3__V_SAD_U8 | |
| CInst_VOP3__V_SAD_HI_U8 | |
| CInst_VOP3__V_SAD_U16 | |
| CInst_VOP3__V_SAD_U32 | |
| CInst_VOP3__V_CVT_PK_U8_F32 | |
| CInst_VOP3__V_DIV_FIXUP_F32 | |
| CInst_VOP3__V_DIV_FIXUP_F64 | |
| CInst_VOP3__V_DIV_SCALE_F32 | |
| CInst_VOP3__V_DIV_SCALE_F64 | |
| CInst_VOP3__V_DIV_FMAS_F32 | |
| CInst_VOP3__V_DIV_FMAS_F64 | |
| CInst_VOP3__V_MSAD_U8 | |
| CInst_VOP3__V_QSAD_PK_U16_U8 | |
| CInst_VOP3__V_MQSAD_PK_U16_U8 | |
| CInst_VOP3__V_MQSAD_U32_U8 | |
| CInst_VOP3__V_MAD_U64_U32 | |
| CInst_VOP3__V_MAD_I64_I32 | |
| CInst_VOP3__V_MAD_F16 | |
| CInst_VOP3__V_MAD_U16 | |
| CInst_VOP3__V_MAD_I16 | |
| CInst_VOP3__V_PERM_B32 | |
| CInst_VOP3__V_FMA_F16 | |
| CInst_VOP3__V_DIV_FIXUP_F16 | |
| CInst_VOP3__V_CVT_PKACCUM_U8_F32 | |
| CInst_VOP3__V_INTERP_P1_F32 | |
| CInst_VOP3__V_INTERP_P2_F32 | |
| CInst_VOP3__V_INTERP_MOV_F32 | |
| CInst_VOP3__V_INTERP_P1LL_F16 | |
| CInst_VOP3__V_INTERP_P1LV_F16 | |
| CInst_VOP3__V_INTERP_P2_F16 | |
| CInst_VOP3__V_ADD_F64 | |
| CInst_VOP3__V_MUL_F64 | |
| CInst_VOP3__V_MIN_F64 | |
| CInst_VOP3__V_MAX_F64 | |
| CInst_VOP3__V_LDEXP_F64 | |
| CInst_VOP3__V_MUL_LO_U32 | |
| CInst_VOP3__V_MUL_HI_U32 | |
| CInst_VOP3__V_MUL_HI_I32 | |
| CInst_VOP3__V_LDEXP_F32 | |
| CInst_VOP3__V_READLANE_B32 | |
| CInst_VOP3__V_WRITELANE_B32 | |
| CInst_VOP3__V_BCNT_U32_B32 | |
| CInst_VOP3__V_MBCNT_LO_U32_B32 | |
| CInst_VOP3__V_MBCNT_HI_U32_B32 | |
| CInst_VOP3__V_LSHLREV_B64 | |
| CInst_VOP3__V_LSHRREV_B64 | |
| CInst_VOP3__V_ASHRREV_I64 | |
| CInst_VOP3__V_TRIG_PREOP_F64 | |
| CInst_VOP3__V_BFM_B32 | |
| CInst_VOP3__V_CVT_PKNORM_I16_F32 | |
| CInst_VOP3__V_CVT_PKNORM_U16_F32 | |
| CInst_VOP3__V_CVT_PKRTZ_F16_F32 | |
| CInst_VOP3__V_CVT_PK_U16_U32 | |
| CInst_VOP3__V_CVT_PK_I16_I32 | |
| CInst_DS__DS_ADD_U32 | |
| CInst_DS__DS_SUB_U32 | |
| CInst_DS__DS_RSUB_U32 | |
| CInst_DS__DS_INC_U32 | |
| CInst_DS__DS_DEC_U32 | |
| CInst_DS__DS_MIN_I32 | |
| CInst_DS__DS_MAX_I32 | |
| CInst_DS__DS_MIN_U32 | |
| CInst_DS__DS_MAX_U32 | |
| CInst_DS__DS_AND_B32 | |
| CInst_DS__DS_OR_B32 | |
| CInst_DS__DS_XOR_B32 | |
| CInst_DS__DS_MSKOR_B32 | |
| CInst_DS__DS_WRITE_B32 | |
| CInst_DS__DS_WRITE2_B32 | |
| CInst_DS__DS_WRITE2ST64_B32 | |
| CInst_DS__DS_CMPST_B32 | |
| CInst_DS__DS_CMPST_F32 | |
| CInst_DS__DS_MIN_F32 | |
| CInst_DS__DS_MAX_F32 | |
| CInst_DS__DS_NOP | |
| CInst_DS__DS_ADD_F32 | |
| CInst_DS__DS_WRITE_B8 | |
| CInst_DS__DS_WRITE_B16 | |
| CInst_DS__DS_ADD_RTN_U32 | |
| CInst_DS__DS_SUB_RTN_U32 | |
| CInst_DS__DS_RSUB_RTN_U32 | |
| CInst_DS__DS_INC_RTN_U32 | |
| CInst_DS__DS_DEC_RTN_U32 | |
| CInst_DS__DS_MIN_RTN_I32 | |
| CInst_DS__DS_MAX_RTN_I32 | |
| CInst_DS__DS_MIN_RTN_U32 | |
| CInst_DS__DS_MAX_RTN_U32 | |
| CInst_DS__DS_AND_RTN_B32 | |
| CInst_DS__DS_OR_RTN_B32 | |
| CInst_DS__DS_XOR_RTN_B32 | |
| CInst_DS__DS_MSKOR_RTN_B32 | |
| CInst_DS__DS_WRXCHG_RTN_B32 | |
| CInst_DS__DS_WRXCHG2_RTN_B32 | |
| CInst_DS__DS_WRXCHG2ST64_RTN_B32 | |
| CInst_DS__DS_CMPST_RTN_B32 | |
| CInst_DS__DS_CMPST_RTN_F32 | |
| CInst_DS__DS_MIN_RTN_F32 | |
| CInst_DS__DS_MAX_RTN_F32 | |
| CInst_DS__DS_WRAP_RTN_B32 | |
| CInst_DS__DS_ADD_RTN_F32 | |
| CInst_DS__DS_READ_B32 | |
| CInst_DS__DS_READ2_B32 | |
| CInst_DS__DS_READ2ST64_B32 | |
| CInst_DS__DS_READ_I8 | |
| CInst_DS__DS_READ_U8 | |
| CInst_DS__DS_READ_I16 | |
| CInst_DS__DS_READ_U16 | |
| CInst_DS__DS_SWIZZLE_B32 | |
| CInst_DS__DS_PERMUTE_B32 | |
| CInst_DS__DS_BPERMUTE_B32 | |
| CInst_DS__DS_ADD_U64 | |
| CInst_DS__DS_SUB_U64 | |
| CInst_DS__DS_RSUB_U64 | |
| CInst_DS__DS_INC_U64 | |
| CInst_DS__DS_DEC_U64 | |
| CInst_DS__DS_MIN_I64 | |
| CInst_DS__DS_MAX_I64 | |
| CInst_DS__DS_MIN_U64 | |
| CInst_DS__DS_MAX_U64 | |
| CInst_DS__DS_AND_B64 | |
| CInst_DS__DS_OR_B64 | |
| CInst_DS__DS_XOR_B64 | |
| CInst_DS__DS_MSKOR_B64 | |
| CInst_DS__DS_WRITE_B64 | |
| CInst_DS__DS_WRITE2_B64 | |
| CInst_DS__DS_WRITE2ST64_B64 | |
| CInst_DS__DS_CMPST_B64 | |
| CInst_DS__DS_CMPST_F64 | |
| CInst_DS__DS_MIN_F64 | |
| CInst_DS__DS_MAX_F64 | |
| CInst_DS__DS_ADD_RTN_U64 | |
| CInst_DS__DS_SUB_RTN_U64 | |
| CInst_DS__DS_RSUB_RTN_U64 | |
| CInst_DS__DS_INC_RTN_U64 | |
| CInst_DS__DS_DEC_RTN_U64 | |
| CInst_DS__DS_MIN_RTN_I64 | |
| CInst_DS__DS_MAX_RTN_I64 | |
| CInst_DS__DS_MIN_RTN_U64 | |
| CInst_DS__DS_MAX_RTN_U64 | |
| CInst_DS__DS_AND_RTN_B64 | |
| CInst_DS__DS_OR_RTN_B64 | |
| CInst_DS__DS_XOR_RTN_B64 | |
| CInst_DS__DS_MSKOR_RTN_B64 | |
| CInst_DS__DS_WRXCHG_RTN_B64 | |
| CInst_DS__DS_WRXCHG2_RTN_B64 | |
| CInst_DS__DS_WRXCHG2ST64_RTN_B64 | |
| CInst_DS__DS_CMPST_RTN_B64 | |
| CInst_DS__DS_CMPST_RTN_F64 | |
| CInst_DS__DS_MIN_RTN_F64 | |
| CInst_DS__DS_MAX_RTN_F64 | |
| CInst_DS__DS_READ_B64 | |
| CInst_DS__DS_READ2_B64 | |
| CInst_DS__DS_READ2ST64_B64 | |
| CInst_DS__DS_CONDXCHG32_RTN_B64 | |
| CInst_DS__DS_ADD_SRC2_U32 | |
| CInst_DS__DS_SUB_SRC2_U32 | |
| CInst_DS__DS_RSUB_SRC2_U32 | |
| CInst_DS__DS_INC_SRC2_U32 | |
| CInst_DS__DS_DEC_SRC2_U32 | |
| CInst_DS__DS_MIN_SRC2_I32 | |
| CInst_DS__DS_MAX_SRC2_I32 | |
| CInst_DS__DS_MIN_SRC2_U32 | |
| CInst_DS__DS_MAX_SRC2_U32 | |
| CInst_DS__DS_AND_SRC2_B32 | |
| CInst_DS__DS_OR_SRC2_B32 | |
| CInst_DS__DS_XOR_SRC2_B32 | |
| CInst_DS__DS_WRITE_SRC2_B32 | |
| CInst_DS__DS_MIN_SRC2_F32 | |
| CInst_DS__DS_MAX_SRC2_F32 | |
| CInst_DS__DS_ADD_SRC2_F32 | |
| CInst_DS__DS_GWS_SEMA_RELEASE_ALL | |
| CInst_DS__DS_GWS_INIT | |
| CInst_DS__DS_GWS_SEMA_V | |
| CInst_DS__DS_GWS_SEMA_BR | |
| CInst_DS__DS_GWS_SEMA_P | |
| CInst_DS__DS_GWS_BARRIER | |
| CInst_DS__DS_CONSUME | |
| CInst_DS__DS_APPEND | |
| CInst_DS__DS_ORDERED_COUNT | |
| CInst_DS__DS_ADD_SRC2_U64 | |
| CInst_DS__DS_SUB_SRC2_U64 | |
| CInst_DS__DS_RSUB_SRC2_U64 | |
| CInst_DS__DS_INC_SRC2_U64 | |
| CInst_DS__DS_DEC_SRC2_U64 | |
| CInst_DS__DS_MIN_SRC2_I64 | |
| CInst_DS__DS_MAX_SRC2_I64 | |
| CInst_DS__DS_MIN_SRC2_U64 | |
| CInst_DS__DS_MAX_SRC2_U64 | |
| CInst_DS__DS_AND_SRC2_B64 | |
| CInst_DS__DS_OR_SRC2_B64 | |
| CInst_DS__DS_XOR_SRC2_B64 | |
| CInst_DS__DS_WRITE_SRC2_B64 | |
| CInst_DS__DS_MIN_SRC2_F64 | |
| CInst_DS__DS_MAX_SRC2_F64 | |
| CInst_DS__DS_WRITE_B96 | |
| CInst_DS__DS_WRITE_B128 | |
| CInst_DS__DS_READ_B96 | |
| CInst_DS__DS_READ_B128 | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_X | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_XY | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_XYZ | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_XYZW | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_X | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_XY | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_XYZ | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_XYZW | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_X | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_X | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_XY | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW | |
| CInst_MUBUF__BUFFER_LOAD_UBYTE | |
| CInst_MUBUF__BUFFER_LOAD_SBYTE | |
| CInst_MUBUF__BUFFER_LOAD_USHORT | |
| CInst_MUBUF__BUFFER_LOAD_SSHORT | |
| CInst_MUBUF__BUFFER_LOAD_DWORD | |
| CInst_MUBUF__BUFFER_LOAD_DWORDX2 | |
| CInst_MUBUF__BUFFER_LOAD_DWORDX3 | |
| CInst_MUBUF__BUFFER_LOAD_DWORDX4 | |
| CInst_MUBUF__BUFFER_STORE_BYTE | |
| CInst_MUBUF__BUFFER_STORE_SHORT | |
| CInst_MUBUF__BUFFER_STORE_DWORD | |
| CInst_MUBUF__BUFFER_STORE_DWORDX2 | |
| CInst_MUBUF__BUFFER_STORE_DWORDX3 | |
| CInst_MUBUF__BUFFER_STORE_DWORDX4 | |
| CInst_MUBUF__BUFFER_STORE_LDS_DWORD | |
| CInst_MUBUF__BUFFER_WBINVL1 | |
| CInst_MUBUF__BUFFER_WBINVL1_VOL | |
| CInst_MUBUF__BUFFER_ATOMIC_SWAP | |
| CInst_MUBUF__BUFFER_ATOMIC_CMPSWAP | |
| CInst_MUBUF__BUFFER_ATOMIC_ADD | |
| CInst_MUBUF__BUFFER_ATOMIC_SUB | |
| CInst_MUBUF__BUFFER_ATOMIC_SMIN | |
| CInst_MUBUF__BUFFER_ATOMIC_UMIN | |
| CInst_MUBUF__BUFFER_ATOMIC_SMAX | |
| CInst_MUBUF__BUFFER_ATOMIC_UMAX | |
| CInst_MUBUF__BUFFER_ATOMIC_AND | |
| CInst_MUBUF__BUFFER_ATOMIC_OR | |
| CInst_MUBUF__BUFFER_ATOMIC_XOR | |
| CInst_MUBUF__BUFFER_ATOMIC_INC | |
| CInst_MUBUF__BUFFER_ATOMIC_DEC | |
| CInst_MUBUF__BUFFER_ATOMIC_SWAP_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_ADD_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_SUB_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_SMIN_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_UMIN_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_SMAX_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_UMAX_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_AND_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_OR_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_XOR_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_INC_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_DEC_X2 | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_X | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_XY | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_X | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_XY | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_XYZ | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_XYZW | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_X | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW | |
| CInst_MIMG__IMAGE_LOAD | |
| CInst_MIMG__IMAGE_LOAD_MIP | |
| CInst_MIMG__IMAGE_LOAD_PCK | |
| CInst_MIMG__IMAGE_LOAD_PCK_SGN | |
| CInst_MIMG__IMAGE_LOAD_MIP_PCK | |
| CInst_MIMG__IMAGE_LOAD_MIP_PCK_SGN | |
| CInst_MIMG__IMAGE_STORE | |
| CInst_MIMG__IMAGE_STORE_MIP | |
| CInst_MIMG__IMAGE_STORE_PCK | |
| CInst_MIMG__IMAGE_STORE_MIP_PCK | |
| CInst_MIMG__IMAGE_GET_RESINFO | |
| CInst_MIMG__IMAGE_ATOMIC_SWAP | |
| CInst_MIMG__IMAGE_ATOMIC_CMPSWAP | |
| CInst_MIMG__IMAGE_ATOMIC_ADD | |
| CInst_MIMG__IMAGE_ATOMIC_SUB | |
| CInst_MIMG__IMAGE_ATOMIC_SMIN | |
| CInst_MIMG__IMAGE_ATOMIC_UMIN | |
| CInst_MIMG__IMAGE_ATOMIC_SMAX | |
| CInst_MIMG__IMAGE_ATOMIC_UMAX | |
| CInst_MIMG__IMAGE_ATOMIC_AND | |
| CInst_MIMG__IMAGE_ATOMIC_OR | |
| CInst_MIMG__IMAGE_ATOMIC_XOR | |
| CInst_MIMG__IMAGE_ATOMIC_INC | |
| CInst_MIMG__IMAGE_ATOMIC_DEC | |
| CInst_MIMG__IMAGE_SAMPLE | |
| CInst_MIMG__IMAGE_SAMPLE_CL | |
| CInst_MIMG__IMAGE_SAMPLE_D | |
| CInst_MIMG__IMAGE_SAMPLE_D_CL | |
| CInst_MIMG__IMAGE_SAMPLE_L | |
| CInst_MIMG__IMAGE_SAMPLE_B | |
| CInst_MIMG__IMAGE_SAMPLE_B_CL | |
| CInst_MIMG__IMAGE_SAMPLE_LZ | |
| CInst_MIMG__IMAGE_SAMPLE_C | |
| CInst_MIMG__IMAGE_SAMPLE_C_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_D | |
| CInst_MIMG__IMAGE_SAMPLE_C_D_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_L | |
| CInst_MIMG__IMAGE_SAMPLE_C_B | |
| CInst_MIMG__IMAGE_SAMPLE_C_B_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_LZ | |
| CInst_MIMG__IMAGE_SAMPLE_O | |
| CInst_MIMG__IMAGE_SAMPLE_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_D_O | |
| CInst_MIMG__IMAGE_SAMPLE_D_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_L_O | |
| CInst_MIMG__IMAGE_SAMPLE_B_O | |
| CInst_MIMG__IMAGE_SAMPLE_B_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_LZ_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_D_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_D_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_L_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_B_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_B_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_LZ_O | |
| CInst_MIMG__IMAGE_GATHER4 | |
| CInst_MIMG__IMAGE_GATHER4_CL | |
| CInst_MIMG__IMAGE_GATHER4_L | |
| CInst_MIMG__IMAGE_GATHER4_B | |
| CInst_MIMG__IMAGE_GATHER4_B_CL | |
| CInst_MIMG__IMAGE_GATHER4_LZ | |
| CInst_MIMG__IMAGE_GATHER4_C | |
| CInst_MIMG__IMAGE_GATHER4_C_CL | |
| CInst_MIMG__IMAGE_GATHER4_C_L | |
| CInst_MIMG__IMAGE_GATHER4_C_B | |
| CInst_MIMG__IMAGE_GATHER4_C_B_CL | |
| CInst_MIMG__IMAGE_GATHER4_C_LZ | |
| CInst_MIMG__IMAGE_GATHER4_O | |
| CInst_MIMG__IMAGE_GATHER4_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_L_O | |
| CInst_MIMG__IMAGE_GATHER4_B_O | |
| CInst_MIMG__IMAGE_GATHER4_B_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_LZ_O | |
| CInst_MIMG__IMAGE_GATHER4_C_O | |
| CInst_MIMG__IMAGE_GATHER4_C_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_C_L_O | |
| CInst_MIMG__IMAGE_GATHER4_C_B_O | |
| CInst_MIMG__IMAGE_GATHER4_C_B_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_C_LZ_O | |
| CInst_MIMG__IMAGE_GET_LOD | |
| CInst_MIMG__IMAGE_SAMPLE_CD | |
| CInst_MIMG__IMAGE_SAMPLE_CD_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD_CL | |
| CInst_MIMG__IMAGE_SAMPLE_CD_O | |
| CInst_MIMG__IMAGE_SAMPLE_CD_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD_CL_O | |
| CInst_EXP__EXP | |
| CInst_FLAT__FLAT_LOAD_UBYTE | |
| CInst_FLAT__FLAT_LOAD_SBYTE | |
| CInst_FLAT__FLAT_LOAD_USHORT | |
| CInst_FLAT__FLAT_LOAD_SSHORT | |
| CInst_FLAT__FLAT_LOAD_DWORD | |
| CInst_FLAT__FLAT_LOAD_DWORDX2 | |
| CInst_FLAT__FLAT_LOAD_DWORDX3 | |
| CInst_FLAT__FLAT_LOAD_DWORDX4 | |
| CInst_FLAT__FLAT_STORE_BYTE | |
| CInst_FLAT__FLAT_STORE_SHORT | |
| CInst_FLAT__FLAT_STORE_DWORD | |
| CInst_FLAT__FLAT_STORE_DWORDX2 | |
| CInst_FLAT__FLAT_STORE_DWORDX3 | |
| CInst_FLAT__FLAT_STORE_DWORDX4 | |
| CInst_FLAT__FLAT_ATOMIC_SWAP | |
| CInst_FLAT__FLAT_ATOMIC_CMPSWAP | |
| CInst_FLAT__FLAT_ATOMIC_ADD | |
| CInst_FLAT__FLAT_ATOMIC_SUB | |
| CInst_FLAT__FLAT_ATOMIC_SMIN | |
| CInst_FLAT__FLAT_ATOMIC_UMIN | |
| CInst_FLAT__FLAT_ATOMIC_SMAX | |
| CInst_FLAT__FLAT_ATOMIC_UMAX | |
| CInst_FLAT__FLAT_ATOMIC_AND | |
| CInst_FLAT__FLAT_ATOMIC_OR | |
| CInst_FLAT__FLAT_ATOMIC_XOR | |
| CInst_FLAT__FLAT_ATOMIC_INC | |
| CInst_FLAT__FLAT_ATOMIC_DEC | |
| CInst_FLAT__FLAT_ATOMIC_SWAP_X2 | |
| CInst_FLAT__FLAT_ATOMIC_CMPSWAP_X2 | |
| CInst_FLAT__FLAT_ATOMIC_ADD_X2 | |
| CInst_FLAT__FLAT_ATOMIC_SUB_X2 | |
| CInst_FLAT__FLAT_ATOMIC_SMIN_X2 | |
| CInst_FLAT__FLAT_ATOMIC_UMIN_X2 | |
| CInst_FLAT__FLAT_ATOMIC_SMAX_X2 | |
| CInst_FLAT__FLAT_ATOMIC_UMAX_X2 | |
| CInst_FLAT__FLAT_ATOMIC_AND_X2 | |
| CInst_FLAT__FLAT_ATOMIC_OR_X2 | |
| CInst_FLAT__FLAT_ATOMIC_XOR_X2 | |
| CInst_FLAT__FLAT_ATOMIC_INC_X2 | |
| CInst_FLAT__FLAT_ATOMIC_DEC_X2 | |
| CBufferRsrcDescriptor | |
| CInst_SOP2 | |
| CInst_SOPK | |
| CInst_SOP1 | |
| CInst_SOPC | |
| CInst_SOPP | |
| CInst_SMEM | |
| CInst_VOP2 | |
| CInst_VOP1 | |
| CInst_VOPC | |
| CInst_VINTRP | |
| CInst_VOP3 | |
| CInst_VOP3_SDST_ENC | |
| CInst_DS | |
| CInst_MUBUF | |
| CInst_MTBUF | |
| CInst_MIMG | |
| CInst_EXP | |
| CInst_FLAT | |
| COpTraits | Convenience traits so we can automatically infer the correct FP type without looking at the number of dwords (i.e., to determine if we need a float or a double when creating FP constants) |
| COpTraits< ScalarRegF64 > | |
| COpTraits< ScalarRegU64 > | |
| COperand | |
| CScalarOperand | |
| CVecOperand | |
| ►NGenericISA | |
| CM5DebugFault | |
| CM5DebugOnceFault | |
| CM5PanicFault | |
| CM5FatalFault | |
| CM5WarnFaultBase | |
| CM5HackFaultBase | |
| CM5InformFaultBase | |
| ►CBasicDecodeCache | |
| CAddrMapEntry | |
| CPCStateWithNext | |
| CSimplePCState | |
| CUPCState | |
| CDelaySlotPCState | |
| CDelaySlotUPCState | |
| ►Nguest_abi | |
| CIsAapcs32Composite | |
| CIsAapcs32Composite< T, typename std::enable_if_t<(std::is_array_v< T >||std::is_class_v< T >||std::is_union_v< T >) &&!IsVarArgsV< T > > > | |
| CIsAapcs32HomogeneousAggregate | |
| CIsAapcs32HomogeneousAggregate< E[N]> | |
| CAapcs32ArgumentBase | |
| CResult< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)< sizeof(uint32_t))> > | |
| CResult< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint32_t))> > | |
| CResult< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint64_t))> > | |
| CArgument< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=sizeof(uint32_t)) > > | |
| CArgument< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > sizeof(uint32_t)) > > | |
| CResult< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > > | |
| CArgument< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > > | |
| CResult< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > > | |
| CArgument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > > | |
| CResult< Aapcs32Vfp, Integer, typename std::enable_if_t< std::is_integral_v< Integer > > > | |
| CArgument< Aapcs32Vfp, Integer, typename std::enable_if_t< std::is_integral_v< Integer > > > | |
| CResult< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > > | |
| CArgument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > > | |
| CResult< Aapcs32Vfp, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > &&!IsAapcs32HomogeneousAggregateV< Composite > > > | |
| CArgument< Aapcs32Vfp, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > &&!IsAapcs32HomogeneousAggregateV< Composite > > > | |
| CAapcs32ArrayType | |
| CAapcs32ArrayType< E[N]> | |
| CArgument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > > | |
| CResult< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > > | |
| CArgument< Aapcs32Vfp, VarArgs< Types... > > | |
| CIsAapcs64ShortVector | |
| CIsAapcs64ShortVector< E[N], typename std::enable_if_t<(std::is_integral_v< E >||std::is_floating_point_v< E >) &&(sizeof(E) *N==8||sizeof(E) *N==16)> > | |
| CIsAapcs64Composite | |
| CIsAapcs64Composite< T, typename std::enable_if_t<(std::is_array_v< T >||std::is_class_v< T >||std::is_union_v< T >) &&!IsVarArgsV< T > &&!IsAapcs64ShortVectorV< T > > > | |
| CIsAapcs64Hfa | |
| CArgument< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> > | |
| CArgument< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > 8)> > | |
| CResult< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> > | |
| CResult< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > 8)> > | |
| CAapcs64ArrayType | |
| CAapcs64ArrayType< E[N]> | |
| CArgument< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > > | |
| CResult< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > > | |
| CArgument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > > | |
| CResult< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > > | |
| CResult< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuFreebsd::BaseSyscallABI, ABI > > > | |
| CResult< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuLinux::BaseSyscallABI, ABI > > > | |
| CArgument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< ArmISA::RegABI32, ABI > &&std::is_integral_v< Arg > &&ABI::template IsWideV< Arg > > > | |
| CArgument< SemiPseudoAbi32, T > | |
| CArgument< SemiPseudoAbi64, T > | |
| CArgument< ArmSemihosting::Abi64, Arg, typename std::enable_if_t< std::is_integral_v< Arg > > > | |
| CArgument< ArmSemihosting::Abi32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > > > | |
| CArgument< Abi, ArmSemihosting::InPlaceArg, typename std::enable_if_t< std::is_base_of_v< ArmSemihosting::AbiBase, Abi > > > | |
| CResult< ArmSemihosting::Abi32, ArmSemihosting::RetErrno > | |
| CResult< ArmSemihosting::Abi64, ArmSemihosting::RetErrno > | |
| CResult< MipsISA::SEWorkload::SyscallABI, SyscallReturn > | |
| CResult< PowerISA::SEWorkload::SyscallABI, SyscallReturn > | |
| CResult< RiscvISA::SEWorkload::SyscallABI, SyscallReturn > | |
| CResult< SparcPseudoInstABI, T > | |
| CArgument< SparcPseudoInstABI, uint64_t > | |
| CResult< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< SparcISA::SEWorkload::BaseSyscallABI, ABI > > > | |
| CArgument< SparcISA::SEWorkload::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&SparcISA::SEWorkload::SyscallABI32::IsWideV< Arg > > > | |
| CResult< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< X86Linux::SyscallABI, ABI > > > | |
| CArgument< X86ISA::EmuLinux::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&X86ISA::EmuLinux::SyscallABI32::IsWideV< Arg > > > | |
| CResult< X86PseudoInstABI, T > | |
| CArgument< X86PseudoInstABI, uint64_t > | |
| CResult | |
| CResult< ABI, void > | |
| CArgument | |
| CStateInitializer | |
| CStateInitializer< ABI, typename std::enable_if_t< std::is_constructible_v< typename ABI::State, const ThreadContext * > > > | |
| CPreparer | |
| CPreparer< ABI, Role, Type, decltype((void)&Role< ABI, Type >::prepare)> | |
| CResultStorer | |
| CResultStorer< ABI, Ret, typename std::enable_if_t< std::is_same_v< void(*)(ThreadContext *, const Ret &, typename ABI::State &), decltype(&Result< ABI, Ret >::store)> > > | |
| CVarArgsBase | |
| CVarArgsBase< First, Types... > | |
| CVarArgsBase<> | |
| CVarArgsImpl | |
| CVarArgsImpl< ABI, Base, First, Types... > | |
| CVarArgsImpl< ABI, Base > | |
| CVarArgs | |
| CIsVarArgs | |
| CIsVarArgs< VarArgs< Types... > > | |
| CArgument< ABI, VarArgs< Types... > > | |
| CArgument< TestABI_1D, int > | |
| CArgument< TestABI_1D, Arg, typename std::enable_if_t< std::is_floating_point_v< Arg > > > | |
| CResult< TestABI_1D, int > | |
| CResult< TestABI_1D, Ret, typename std::enable_if_t< std::is_floating_point_v< Ret > > > | |
| CArgument< TestABI_Prepare, int > | |
| CResult< TestABI_Prepare, Ret > | |
| CArgument< TestABI_2D, int > | |
| CArgument< TestABI_2D, Arg, typename std::enable_if_t< std::is_floating_point_v< Arg > > > | |
| CResult< TestABI_2D, int > | |
| CResult< TestABI_2D, Ret, typename std::enable_if_t< std::is_floating_point_v< Ret > > > | |
| CArgument< TestABI_TcInit, int > | |
| CArgument< ABI, ProxyPtr< T, Proxy > > | |
| CArgument< ABI, ConstProxyPtr< T, Proxy > > | |
| CArgument< TestABI, Addr > | |
| CArgument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< GenericSyscallABI64, ABI > &&std::is_integral_v< Arg > > > | |
| CArgument< ABI, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&!ABI::template IsWideV< Arg > > > | |
| ►Nigbreg | |
| CRxDesc | |
| CTxDesc | |
| ►CRegs | |
| CCTRL | |
| CCTRL_EXT | |
| CEECD | |
| CEERD | |
| CFCRTH | |
| CFCRTL | |
| CFCTTV | |
| CFWSM | |
| CICR | |
| CITR | |
| CMANC | |
| CMDIC | |
| CPBA | |
| CRADV | |
| CRCTL | |
| CRDBA | |
| CRDH | |
| CRDLEN | |
| CRDT | |
| CRDTR | |
| CReg | |
| CRFCTL | |
| CRSRPD | |
| CRXCSUM | |
| CRXDCTL | |
| CSRRCTL | |
| CSTATUS | |
| CSWSM | |
| CTADV | |
| CTCTL | |
| CTDBA | |
| CTDH | |
| CTDLEN | |
| CTDT | |
| CTIDV | |
| CTXDCA_CTL | |
| CTXDCTL | |
| ►NIris | |
| CBaseCpuEvs | |
| CBaseCPU | |
| CCPU | |
| CInterrupts | |
| CISA | |
| CMMU | |
| ►CThreadContext | |
| CBpInfo | |
| CTLB | |
| ►Nlinux | |
| CThreadInfo | |
| Cpcb_struct | |
| Cthread_info | |
| CDebugPrintk | |
| CDmesgDump | Dump the guest kernel's dmesg buffer to a file in gem5's output directory and print a warning |
| CKernelPanic | Dump the guest kernel's dmesg buffer to a file in gem5's output directory and panic |
| CSkipUDelay | A class to skip udelay() and related calls in the kernel |
| ►Nloader | |
| CDtbFile | |
| CElfObjectFormat | |
| CElfObject | |
| CImageFile | |
| CImageFileData | |
| ►CMemoryImage | |
| CSegment | |
| CObjectFile | |
| CObjectFileFormat | |
| CRawImage | |
| CSymbol | |
| CSymbolTable | |
| ►Nmemory | |
| ►Nqos | |
| ►CMemCtrl | The qos::MemCtrl is a base class for Memory objects which support QoS - it provides access to a set of QoS scheduling policies |
| CMemCtrlStats | |
| ►CMemSinkCtrl | QoS Memory Sink |
| CMemoryPort | |
| CMemSinkCtrlStats | |
| CMemSinkInterface | |
| CPolicy | QoS Policy base class |
| CFixedPriorityPolicy | Fixed Priority QoS Policy |
| CPropFairPolicy | Proportional Fair QoS Policy Providing a configurable fair scheduling policy based on utilization; utilization is directly proportional to a score which is inversely proportional to the QoS priority Users can tune the policy by adjusting the weight parameter (weight of the formula) |
| CQueuePolicy | QoS Queue Policy |
| CLifoQueuePolicy | Last In First Out Queue Policy |
| CFifoQueuePolicy | First In First Out Queue Policy |
| CLrgQueuePolicy | Least Recently Granted Queue Policy It selects packets from the queue with a round robin-like policy: using the requestor id as a switching parameter rather than switching over a time quantum |
| CTurnaroundPolicy | Base class for QoS Bus Turnaround policies |
| CTurnaroundPolicyIdeal | Ideal QoS Bus Turnaround policy |
| CLockedAddr | Locked address class that represents a physical address and a context id |
| ►CAbstractMemory | An abstract memory represents a contiguous block of physical memory, with an associated address range, and also provides basic functionality for reading and writing this memory without any timing information |
| CMemStats | |
| ►CCfiMemory | CfiMemory: This is modelling a flash memory adhering to the Common Flash Interface (CFI): |
| CBlockData | Metadata about the erase blocks in flash |
| CDeferredPacket | A deferred packet stores a packet along with its scheduled transmission time |
| CMemoryPort | |
| CProgramBuffer | Word Buffer used by the BUFFERED PROGRAM command to write (program) chunks of words to flash |
| ►CDRAMInterface | Interface to DRAM devices with media specific parameters, statistics, and functions |
| CCommand | Simple structure to hold the values needed to keep track of commands for DRAMPower |
| CDRAMStats | |
| CRank | Rank class includes a vector of banks |
| CRankStats | |
| ►CDRAMSim2 | |
| CMemoryPort | The memory port has to deal with its own flow control to avoid having unbounded storage that is implicitly created in the port itself |
| CDRAMSim2Wrapper | Wrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world |
| ►CDRAMsim3 | |
| CMemoryPort | The memory port has to deal with its own flow control to avoid having unbounded storage that is implicitly created in the port itself |
| CDRAMsim3Wrapper | Wrapper class to avoid having DRAMsim3 names like ClockDomain etc clashing with the normal gem5 world |
| CHBMCtrl | HBM2 is divided into two pseudo channels which have independent data buses but share a command bus (separate row and column command bus) |
| CHeteroMemCtrl | |
| CBurstHelper | A burst helper helps organize and manage a packet that is larger than the memory burst size |
| CMemPacket | A memory packet stores packets along with the timestamp of when the packet entered the queue, and also the decoded address |
| ►CMemCtrl | The memory controller is a single-channel memory controller capturing the most important timing constraints associated with a contemporary controller |
| CCtrlStats | |
| CMemoryPort | |
| ►CMemInterface | General interface to memory device Includes functions and parameters shared across media types |
| CBank | A basic class to track the bank state, i.e |
| ►CNVMInterface | Interface to NVM devices with media specific parameters, statistics, and functions |
| CNVMStats | |
| CRank | NVM rank class simply includes a vector of banks |
| CBackingStoreEntry | A single entry for the backing store |
| CPhysicalMemory | The physical memory encapsulates all memories in the system and provides basic functionality for accessing those memories without going through the memory system and interconnect |
| ►CSharedMemoryServer | |
| CBaseShmPollEvent | |
| CClientSocketEvent | |
| CListenSocketEvent | |
| ►CSimpleMemory | The simple memory is a basic single-ported memory controller with a configurable throughput and latency |
| CDeferredPacket | A deferred packet stores a packet along with its scheduled transmission time |
| CMemoryPort | |
| ►Nminor | |
| CMinorActivityRecorder | ActivityRecorder with a Ticked interface |
| CReportIF | Interface class for data with reporting/tracing facilities |
| CBubbleIF | Interface class for data with 'bubble' values |
| CReportTraitsAdaptor | ...ReportTraits are trait classes with the same functionality as ReportIF, but with elements explicitly passed into the report.. |
| CReportTraitsPtrAdaptor | A similar adaptor but for elements held by pointer ElemType should implement ReportIF |
| CNoBubbleTraits | .. |
| CBubbleTraitsAdaptor | Pass on call to the element |
| CBubbleTraitsPtrAdaptor | Pass on call to the element where the element is a pointer |
| CMinorBuffer | TimeBuffer with MinorTrace and Named interfaces |
| ►CLatch | Wraps a MinorBuffer with Input/Output interfaces to ensure that units within the model can only see the right end of buffers between them |
| CInput | Encapsulate wires on either input or output of the latch |
| COutput | |
| CSelfStallingPipeline | A pipeline simulating class that will stall (not advance when advance() is called) if a non-bubble value lies at the far end of the pipeline |
| CReservable | Base class for space reservation requestable objects |
| CQueue | Wrapper for a queue type to act as a pipeline stage input queue |
| CInputBuffer | Like a Queue but with a restricted interface and a setTail function which, when the queue is empty, just takes a reference to the pushed item as the single element |
| ►CDecode | |
| CDecodeThreadInfo | Data members after this line are cycle-to-cycle state |
| CInstId | Id for lines and instructions |
| CMinorDynInst | Dynamic instruction for Minor |
| CExecContext | ExecContext bears the exec_context interface for Minor |
| ►CExecute | Execute stage |
| CExecuteThreadInfo | |
| ►CFetch1 | A stage responsible for fetching "lines" from memory and passing them to Fetch2 |
| CFetch1ThreadInfo | Stage cycle-by-cycle state |
| CFetchRequest | Memory access queuing |
| CIcachePort | Exposable fetch port |
| ►CFetch2 | This stage receives lines of data from Fetch1, separates them into instructions and passes them to Decode |
| CFetch2Stats | |
| CFetch2ThreadInfo | Data members after this line are cycle-to-cycle state |
| CQueuedInst | Container class to box instructions in the FUs to make those queues have correct bubble behaviour when stepped |
| CFUPipeline | A functional unit configured from a MinorFU object |
| ►CLSQ | |
| CBarrierDataRequest | Request for doing barrier accounting in the store buffer |
| CDcachePort | Exposable data port |
| CFailedDataRequest | FailedDataRequest represents requests from instructions that failed their predicates but need to ride the requests/transfers queues to maintain trace ordering |
| CLSQRequest | Derived SenderState to carry data access info |
| CSingleDataRequest | SingleDataRequest is used for requests that don't fragment |
| CSpecialDataRequest | Special request types that don't actually issue memory requests |
| CSplitDataRequest | |
| CStoreBuffer | Store buffer |
| CBranchData | Forward data betwen Execute and Fetch1 carrying change-of-address/stream information |
| CForwardLineData | Line fetch data in the forward direction |
| CForwardInstData | Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appropriate to the configured stage widths |
| CPipeline | The constructed pipeline |
| CScoreboard | A scoreboard of register dependencies including, for each register: The number of in-flight instructions which will generate a result for this register |
| CMinorStats | Currently unused stats class |
| ►NMipsISA | |
| CDecoder | |
| ►CMipsFaultBase | |
| CFaultVals | |
| CMipsFault | |
| CSystemCallFault | |
| CReservedInstructionFault | |
| CThreadFault | |
| CIntegerOverflowFault | |
| CTrapFault | |
| CBreakpointFault | |
| CDspStateDisabledFault | |
| CMachineCheckFault | |
| CResetFault | |
| CSoftResetFault | |
| CNonMaskableInterrupt | |
| CCoprocessorUnusableFault | |
| CInterruptFault | |
| CAddressFault | |
| CAddressErrorFault | |
| CTlbFault | |
| CTlbRefillFault | |
| CTlbInvalidFault | |
| CTlbModifiedFault | |
| CInterrupts | |
| CISA | |
| CEmuLinux | |
| CMMU | |
| CPTE | |
| CTlbEntry | |
| ►CRemoteGDB | |
| CMipsGdbRegCache | |
| ►CSEWorkload | |
| CSyscallABI | |
| CStackTrace | |
| CTLB | |
| CCoreSpecific | |
| ►Nnetworking | |
| CEthAddr | |
| CEthHdr | |
| CEthPtr | |
| CIpAddress | |
| CIpNetmask | |
| CIpWithPort | |
| CIpHdr | |
| CIpPtr | |
| CIpOpt | |
| CIp6Hdr | |
| CIp6Ptr | |
| Cip6_opt_fragment | |
| Cip6_opt_routing_type2 | |
| Cip6_opt_dstopts | |
| Cip6_opt_hdr | |
| CIp6Opt | |
| CTcpHdr | |
| CTcpPtr | |
| CTcpOpt | |
| CUdpHdr | |
| CUdpPtr | |
| ►No3 | |
| CChecker | Specific non-templated derived class used for SimObject configuration |
| CFetchStruct | Struct that defines the information passed from fetch to decode |
| CDecodeStruct | Struct that defines the information passed from decode to rename |
| CRenameStruct | Struct that defines the information passed from rename to IEW |
| CIEWStruct | Struct that defines the information passed from IEW to commit |
| CIssueStruct | |
| ►CTimeStruct | Struct that defines all backwards communication |
| CCommitComm | |
| CDecodeComm | |
| CIewComm | |
| CRenameComm | |
| ►CCommit | Commit handles single threaded and SMT commit |
| CCommitStats | |
| ►CCPU | O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages |
| CCPUStats | |
| ►CDecode | Decode class handles both single threaded and SMT decode |
| CDecodeStats | |
| CStalls | Source of possible stalls |
| CDependencyEntry | Node in a linked list |
| CDependencyGraph | Array of linked list that maintains the dependencies between producing instructions and consuming instructions |
| ►CDynInst | |
| CArrays | |
| ►CFetch | Fetch class handles both single threaded and SMT fetch |
| CFetchStatGroup | |
| CFetchTranslation | |
| CFinishTranslationEvent | |
| CIcachePort | IcachePort class for instruction fetch |
| CStalls | Source of possible stalls |
| CSimpleFreeList | Free list for a single class of registers (e.g., integer or floating point) |
| CUnifiedFreeList | FreeList class that simply holds the list of free integer and floating point registers |
| ►CFUPool | Pool of FU's, specific to the new CPU model |
| CFUIdxQueue | Class that implements a circular queue to hold FU indices |
| ►CIEW | IEW handles both single threaded and SMT IEW (issue/execute/writeback) |
| ►CIEWStats | |
| CExecutedInstStats | |
| ►CInstructionQueue | A standard instruction queue class |
| CFUCompletion | FU completion event class |
| CIQIOStats | |
| CIQStats | |
| CListOrderEntry | Entry for the list age ordering by op class |
| CPqCompare | Struct for comparing entries to be added to the priority queue |
| ►CLSQ | |
| CDcachePort | DcachePort class for the load/store queue |
| CLSQRequest | Memory operation metadata |
| CSingleDataRequest | |
| CSplitDataRequest | |
| CUnsquashableDirectRequest | |
| ►CLSQUnit | Class that implements the actual LQ and SQ for each specific thread |
| CLSQEntry | |
| CLSQUnitStats | |
| CSQEntry | |
| CWritebackEvent | Writeback event, specifically for when stores forward data to loads |
| ►CMemDepUnit | Memory dependency unit class |
| CMemDepEntry | Memory dependence entries that track memory operations, marking when the instruction is ready to execute and what instructions depend upon it |
| CMemDepUnitStats | |
| ►CElasticTrace | The elastic trace is a type of probe listener and listens to probe points in multiple stages of the O3CPU |
| CElasticTraceStats | |
| CInstExecInfo | |
| CTraceInfo | |
| CSimpleTrace | |
| CPhysRegFile | Simple physical register file class |
| ►CRename | Rename handles both single threaded and SMT rename |
| CFreeEntries | Structures whose free entries impact the amount of instructions that can be renamed |
| CRenameHistory | Holds the information for each destination register rename |
| CRenameStats | |
| CStalls | Source of possible stalls |
| CSimpleRenameMap | Register rename map for a single class of registers (e.g., integer or floating point) |
| CUnifiedRenameMap | Unified register rename map for all classes of registers |
| ►CROB | ROB class |
| CROBStats | |
| CScoreboard | Implements a simple scoreboard to track which registers are ready |
| Cltseqnum | |
| CStoreSet | Implements a store set predictor for determining if memory instructions are dependent upon each other |
| CThreadContext | Derived ThreadContext class for use with the O3CPU |
| CThreadState | Class that has various thread state, such as the status, the current instruction being processed, whether or not the thread has a trap pending or is being externally updated, the ThreadContext pointer, etc |
| ►NPowerISA | |
| CDecoder | |
| CPowerFault | |
| CUnimplementedOpcodeFault | |
| CMachineCheckFault | |
| CAlignmentFault | |
| CTrapFault | |
| CPCDependentDisassembly | Base class for instructions whose disassembly is not purely a function of the machine instruction (i.e., it depends on the PC) |
| CBranchOp | Base class for unconditional, PC-relative or absolute address branches |
| CBranchCondOp | Base class for conditional branches |
| CBranchDispCondOp | Base class for conditional, PC-relative or absolute address branches |
| CBranchRegCondOp | Base class for conditional, register-based branches |
| CCondLogicOp | Class for condition register logical operations |
| CCondMoveOp | Class for condition register move operations |
| CFloatOp | Base class for floating point operations |
| CIntOp | We provide a base class for integer operations and then inherit for several other classes |
| CIntImmOp | Class for integer immediate (signed and unsigned) operations |
| CIntArithOp | Class for integer arithmetic operations |
| CIntImmArithOp | Class for integer immediate arithmetic operations |
| CIntDispArithOp | Class for integer arithmetic operations with displacement |
| CIntCompOp | Class for integer compare operations |
| CIntImmCompOp | Class for integer immediate compare operations |
| CIntImmCompLogicOp | Class for integer immediate compare logical operations |
| CIntLogicOp | Class for integer logical operations |
| CIntImmLogicOp | Class for integer immediate logical operations |
| CIntShiftOp | Class for integer operations with a shift value obtained from a register or an instruction field |
| CIntConcatShiftOp | Class for integer shift operations with a shift value obtained from a register or by concatenating immediates |
| CIntRotateOp | Class for integer rotate operations with a shift amount obtained from a register or an immediate and the first and last bits of a mask obtained from immediates |
| CIntConcatRotateOp | Class for integer rotate operations with a shift amount obtained from a register or by concatenating immediate fields and the first and last bits of a mask obtained by concatenating immediate fields |
| CIntTrapOp | Class for integer trap operations |
| CIntImmTrapOp | Class for integer immediate trap operations |
| CMemOp | Base class for memory operations |
| CMemDispOp | Class for memory operations with displacement |
| CMemDispShiftOp | Class for memory operations with shifted displacement |
| CMemIndexOp | Class for memory operations with register indexed addressing |
| CMiscOp | Class for misc operations |
| CPowerStaticInst | |
| CInterrupts | |
| CISA | |
| CEmuLinux | |
| CMMU | |
| CPTE | |
| CPCState | |
| ►CRemoteGDB | |
| ►CPower64GdbRegCache | |
| CGEM5_PACKED | |
| ►CPowerGdbRegCache | |
| CGEM5_PACKED | |
| ►CSEWorkload | |
| CSyscallABI | |
| CStackTrace | |
| CTlbEntry | |
| CTLB | |
| ►Nprefetch | |
| ►CAccessMapPatternMatching | |
| CAccessMapEntry | AccessMapEntry data type |
| CAMPM | |
| ►CBase | |
| CPrefetchInfo | Class containing the information needed by the prefetch to train and generate new prefetch requests |
| CPrefetchListener | |
| CStatGroup | |
| ►CBOP | |
| CDelayQueueEntry | In a first implementation of the BO prefetcher, both banks of the RR were written simultaneously when a prefetched line is inserted into the cache |
| ►CDeltaCorrelatingPredictionTables | Delta Correlating Prediction Tables Prefetcher References: Multi-level hardware prefetching using low complexity delta correlating prediction tables with partial matching |
| CDCPTEntry | DCPT Table entry datatype |
| CDCPT | The prefetcher object using the DCPT |
| ►CIndirectMemory | |
| CIndirectPatternDetectorEntry | Indirect Pattern Detector entrt |
| CPrefetchTableEntry | Prefetch Table Entry |
| ►CIrregularStreamBuffer | |
| CAddressMapping | Address Mapping entry, holds an address and a confidence counter |
| CAddressMappingEntry | Maps a set of contiguous addresses to another set of (not necessarily contiguos) addresses, with their corresponding confidence counters |
| CTrainingUnitEntry | Training Unit Entry datatype, it holds the last accessed address and its secure flag |
| CMulti | |
| ►CPIF | |
| CCompactorEntry | The compactor tracks retired instructions addresses, leveraging the spatial and temporal locality among instructions for compaction |
| CIndexEntry | |
| CPrefetchListenerPC | Probe Listener to handle probe events from the CPU |
| ►CQueued | |
| CDeferredPacket | |
| CQueuedStats | |
| ►CSBOOE | |
| CSandbox | |
| CSandboxEntry | |
| ►CSignaturePath | |
| CPatternEntry | Pattern entry data type, a set of stride and counter entries |
| CPatternStrideEntry | A stride entry with its counter |
| CSignatureEntry | Signature entry data type |
| ►CSignaturePathV2 | |
| CGlobalHistoryEntry | Global History Register entry datatype |
| CSlimAMPM | |
| ►CSTeMS | |
| ►CActiveGenerationTableEntry | Entry data type for the Active Generation Table (AGT) and the Pattern Sequence Table (PST) |
| CSequenceEntry | Sequence entry data type |
| CRegionMissOrderBufferEntry | Data type of the Region Miss Order Buffer entry |
| CStridePrefetcherHashedSetAssociative | Override the default set associative to apply a specific hash function when extracting a set |
| ►CStride | |
| CPCTableInfo | Information used to create a new PC table |
| CStrideEntry | Tagged by hashed PCs |
| CTagged | |
| ►Nprobing | |
| CPacketInfo | A struct to hold on to the essential fields from a packet, so that the packet and underlying request can be safely passed on, and consequently modified or even deleted |
| ►Nps2 | |
| CDevice | |
| CPS2Keyboard | |
| CPS2Mouse | |
| CTouchKit | |
| ►Nqemu | |
| CFwCfgItem | |
| CFwCfgItemFixed | |
| CFwCfgItemFile | |
| CFwCfgItemString | |
| CFwCfgItemBytes | |
| CFwCfgItemFactoryBase | |
| CFwCfgItemFactory | |
| ►CFwCfg | |
| CDirectory | |
| CFwCfgIo | |
| CFwCfgMmio | |
| CFwCfgItemE820 | |
| ►Nreplacement_policy | |
| CBase | A common base class of cache replacement policy objects |
| CBIP | |
| ►CBRRIP | |
| CBRRIPReplData | BRRIP-specific implementation of replacement data |
| ►CDueling | This replacement policy duels two replacement policies to find out which one provides the best results |
| CDuelerReplData | Dueler-specific implementation of replacement data |
| CDuelingStats | |
| ►CFIFO | |
| CFIFOReplData | FIFO-specific implementation of replacement data |
| ►CLFU | |
| CLFUReplData | LFU-specific implementation of replacement data |
| ►CLRU | |
| CLRUReplData | LRU-specific implementation of replacement data |
| ►CMRU | |
| CMRUReplData | MRU-specific implementation of replacement data |
| ►CRandom | |
| CRandomReplData | Random-specific implementation of replacement data |
| CReplacementData | The replacement data needed by replacement policies |
| ►CSecondChance | |
| CSecondChanceReplData | Second-Chance-specific implementation of replacement data |
| ►CSHiP | |
| CSHiPReplData | SHiP-specific implementation of replacement data |
| CSHiPMem | SHiP that Uses memory addresses as signatures |
| CSHiPPC | SHiP that Uses PCs as signatures |
| ►CTreePLRU | |
| CTreePLRUReplData | Tree-PLRU-specific implementation of replacement data |
| ►CWeightedLRU | |
| CWeightedLRUReplData | Weighted LRU implementation of replacement data |
| ►NRiscvISA | |
| CBareMetal | |
| CDecoder | |
| CRiscvFault | |
| CReset | |
| CInterruptFault | |
| CNonMaskableInterruptFault | |
| CInstFault | |
| CUnknownInstFault | |
| CIllegalInstFault | |
| CUnimplementedFault | |
| CIllegalFrmFault | |
| CAddressFault | |
| CBreakpointFault | |
| CSyscallFault | |
| CMemFenceMicro | |
| CLoadReserved | |
| CLoadReservedMicro | |
| CStoreCond | |
| CStoreCondMicro | |
| CAtomicMemOp | |
| CAtomicMemOpMicro | |
| CAtomicGenericOp | A generic atomic op class |
| CCompRegOp | Base class for compressed operations that work only on registers |
| CMemInst | |
| CLoad | |
| CStore | |
| CPseudoOp | |
| CRegOp | Base class for operations that work only on registers |
| CImmOp | Base class for operations with immediates (I is the type of immediate) |
| CSystemOp | Base class for system operations |
| CCSROp | Base class for CSR operations |
| CRiscvStaticInst | Base class for all RISC-V static instructions |
| CRiscvMacroInst | Base class for all RISC-V Macroops |
| CRiscvMicroInst | Base class for all RISC-V Microops |
| CUnknown | Static instruction class for unknown (illegal) instructions |
| CInterrupts | |
| CISA | |
| CFsLinux | |
| CEmuLinux | |
| CMMU | |
| CTlbEntry | |
| ►CWalker | |
| CWalkerPort | |
| CWalkerSenderState | |
| CWalkerState | |
| CPCState | |
| CRegABI64 | |
| CCSRMetadata | |
| ►CRemoteGDB | |
| CRiscvGdbRegCache | |
| CSEWorkload | |
| CStackTrace | |
| ►CTLB | |
| CTlbStats | |
| CMmioVirtIO | |
| ►Nruby | |
| ►Ngarnet | |
| CRouteInfo | |
| CCredit | |
| CCreditLink | |
| CCrossbarSwitch | |
| Cflit | |
| CflitBuffer | |
| CGarnetIntLink | |
| CGarnetExtLink | |
| CGarnetNetwork | |
| CInputUnit | |
| CNetworkBridge | |
| ►CNetworkInterface | |
| CInputPort | |
| COutputPort | |
| CNetworkLink | |
| COutputUnit | |
| COutVcState | |
| CRouter | |
| CRoutingUnit | |
| CSwitchAllocator | |
| CVirtualChannel | |
| CConsumer | |
| CDataBlock | |
| ►CExpectedMap | |
| ►CExpectedState | |
| CEnumClassHash | |
| CHistogram | |
| CMachineID | |
| CNetDest | |
| CSet | |
| CSubBlock | |
| ►CTriggerQueue | |
| CValType | |
| CWriteMask | |
| CBasicLink | |
| CBasicExtLink | |
| CBasicIntLink | |
| CBasicRouter | |
| CRubyDummyPort | |
| ►CFaultModel | |
| Csystem_conf | |
| CMessageBuffer | |
| ►CNetwork | |
| CAddrMapNode | |
| ►CPerfectSwitch | |
| COutputPort | |
| ►CBaseRoutingUnit | |
| CRouteInfo | |
| ►CWeightBased | |
| CLinkInfo | |
| CSimpleExtLink | |
| CSimpleIntLink | |
| ►CSimpleNetwork | |
| CNetworkStats | |
| ►CSwitch | |
| CSwitchStats | |
| ►CThrottle | |
| CThrottleStats | |
| CLinkEntry | |
| CTopology | |
| CAccessTraceForAddress | |
| CAddressProfiler | |
| ►CProfiler | |
| ►CProfilerStats | |
| CPerMachineTypeStats | |
| CPerRequestTypeMachineTypeStats | |
| CPerRequestTypeStats | |
| CStoreTrace | |
| CAbstractCacheEntry | |
| CRejectException | |
| ►CAbstractController | |
| CControllerStats | |
| CMemoryPort | Port that forwards requests and receives responses from the memory controller |
| CSenderState | |
| CTransMapPair | |
| CMessage | |
| CRubyRequest | |
| ►CBankedArray | |
| CAccessRecord | |
| ►CCacheMemory | |
| CCacheMemoryStats | |
| CDirectoryMemory | |
| ►CMN_TBEStorage | |
| CMN_TBEStorageStats | |
| CMN_TBETable | |
| CPerfectCacheLineState | |
| CPerfectCacheMemory | |
| CPersistentTableEntry | |
| CPersistentTable | |
| CPrefetchEntry | |
| ►CRubyPrefetcher | |
| CNonUnitFilterEntry | |
| CRubyPrefetcherStats | |
| CUnitFilterEntry | |
| ►CTBEStorage | |
| CTBEStorageStats | |
| CTBETable | |
| CTimerTable | |
| CWireBuffer | |
| CTraceRecord | Class for recording cache contents |
| CCacheRecorder | |
| CDMARequest | |
| CDMASequencer | |
| CUncoalescedTable | |
| CCoalescedRequest | |
| CPendingWriteInst | |
| ►CGPUCoalescer | |
| CGMTokenPort | |
| CHTMSequencer | |
| ►CRubyPort | |
| CMemRequestPort | |
| CMemResponsePort | |
| CPioRequestPort | |
| CPioResponsePort | |
| CSenderState | |
| CRubyPortProxy | |
| CRubySystem | |
| CSequencerRequest | |
| CSequencer | |
| CVIPERCoalescer | |
| ►Nscmi | |
| CMessage | |
| CVirtualChannel | Generic communication channel between the Agent and the Platform |
| CAgentChannel | This is a Agent to Platform channel (The agent is the initiator) |
| CPlatformChannel | This is a Platform to Agent channel (The platform is the initiator) |
| CCommunication | The SCMI Communication class models a bidirectional communication between the SCMI platform and the agent |
| CPlatform | |
| CProtocol | |
| CBaseProtocol | This protocol describes the properties of the implementation and provides generic error management |
| ►Nsinic | |
| ►Nregisters | |
| CInfo | |
| CBase | |
| ►CDevice | |
| CDeviceStats | Statistics |
| CVirtualReg | |
| CInterface | |
| ►NSparcISA | |
| CDecoder | |
| ►CSparcFaultBase | |
| CFaultVals | |
| CSparcFault | |
| CPowerOnReset | |
| CWatchDogReset | |
| CExternallyInitiatedReset | |
| CSoftwareInitiatedReset | |
| CREDStateException | |
| CStoreError | |
| CInstructionAccessException | |
| CInstructionAccessError | |
| CIllegalInstruction | |
| CPrivilegedOpcode | |
| CFpDisabled | |
| CVecDisabled | |
| CFpExceptionIEEE754 | |
| CFpExceptionOther | |
| CTagOverflow | |
| CCleanWindow | |
| CDivisionByZero | |
| CInternalProcessorError | |
| CInstructionInvalidTSBEntry | |
| CDataInvalidTSBEntry | |
| CDataAccessException | |
| CDataAccessError | |
| CDataAccessProtection | |
| CMemAddressNotAligned | |
| CLDDFMemAddressNotAligned | |
| CSTDFMemAddressNotAligned | |
| CPrivilegedAction | |
| CLDQFMemAddressNotAligned | |
| CSTQFMemAddressNotAligned | |
| CInstructionRealTranslationMiss | |
| CDataRealTranslationMiss | |
| CEnumeratedFault | |
| CInterruptLevelN | |
| CHstickMatch | |
| CTrapLevelZero | |
| CInterruptVector | |
| CPAWatchpoint | |
| CVAWatchpoint | |
| CFastInstructionAccessMMUMiss | |
| CFastDataAccessMMUMiss | |
| CFastDataAccessProtection | |
| CInstructionBreakpoint | |
| CCpuMondo | |
| CDevMondo | |
| CResumableError | |
| CSpillNNormal | |
| CSpillNOther | |
| CFillNNormal | |
| CFillNOther | |
| CTrapInstruction | |
| CFsWorkload | |
| CBlockMem | |
| CBlockMemImm | |
| CBlockMemMicro | |
| CBlockMemImmMicro | |
| CBranch | Base class for branch operations |
| CBranchDisp | Base class for branch operations with an immediate displacement |
| CBranchNBits | Base class for branches with n bit displacements |
| CBranchSplit | Base class for 16bit split displacements |
| CBranchImm13 | Base class for branches that use an immediate and a register to compute their displacements |
| CIntOp | Base class for integer operations |
| CIntOpImm | Base class for immediate integer operations |
| CIntOpImm10 | Base class for 10 bit immediate integer operations |
| CIntOpImm11 | Base class for 11 bit immediate integer operations |
| CIntOpImm13 | Base class for 13 bit immediate integer operations |
| CSetHi | Base class for sethi |
| CMem | Base class for memory operations |
| CMemImm | Class for memory operations which use an immediate offset |
| CSparcMacroInst | |
| CSparcMicroInst | |
| CSparcDelayedMicroInst | |
| CNop | Nop class |
| CPriv | Base class for privelege mode operations |
| CPrivReg | |
| CRdPriv | |
| CWrPriv | |
| CPrivImm | Base class for privelege mode operations with immediates |
| CWrPrivImm | |
| CSparcStaticInst | Base class for all SPARC static instructions |
| CTrap | Base class for trap instructions, or instructions that always fault |
| CFpUnimpl | |
| CFailUnimplemented | Static instruction class for unimplemented instructions that cause simulator termination |
| CWarnUnimplemented | Base class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation) |
| CUnknown | Class for Unknown/Illegal instructions |
| CInterrupts | |
| CISA | |
| CEmuLinux | |
| CMMU | |
| CTteTag | |
| CPageTableEntry | |
| CTlbRange | |
| CTlbEntry | |
| CIntRegClassOps | |
| ►CRemoteGDB | |
| CSPARC64GdbRegCache | |
| CSPARCGdbRegCache | |
| ►CSEWorkload | |
| CBaseSyscallABI | |
| CSyscallABI32 | |
| CSyscallABI64 | |
| CStackTrace | |
| CTLB | |
| CTlbMap | |
| ►Nstatistics | |
| ►Nunits | |
| CBase | Parent class of all unit classes |
| CCycle | |
| CTick | |
| CSecond | |
| CBit | |
| CByte | |
| CWatt | |
| CJoule | |
| CVolt | |
| CDegreeCelsius | |
| CCount | |
| CRatio | |
| CUnspecified | |
| CRate | |
| CInfoProxy | |
| CScalarInfoProxy | |
| CVectorInfoProxy | |
| CDistInfoProxy | |
| CVectorDistInfoProxy | |
| CVector2dInfoProxy | |
| CInfoAccess | |
| CDataWrap | |
| CDataWrapVec | |
| CDataWrapVec2d | |
| CScalarBase | Implementation of a scalar stat |
| CProxyInfo | |
| CValueProxy | |
| CFunctorProxy | |
| CFunctorProxy< T, typename std::enable_if_t< std::is_constructible_v< std::function< Result()>, const T & > > > | Template specialization for type std::function<Result()> which holds a copy of its target instead of a pointer to it |
| CMethodProxy | A proxy similar to the FunctorProxy, but allows calling a method of a bound object, instead of a global free-standing function |
| CValueBase | |
| CScalarProxy | A proxy class to access the stat at a given index in a VectorBase stat |
| CVectorBase | Implementation of a vector of stats |
| CVectorProxy | |
| CVector2dBase | |
| CDistBase | Implementation of a distribution stat |
| CDistProxy | |
| CVectorDistBase | |
| CNode | Base class for formula statistic node |
| CScalarStatNode | |
| CScalarProxyNode | |
| CVectorStatNode | |
| CConstNode | |
| CConstVectorNode | |
| COpString | |
| COpString< std::plus< Result > > | |
| COpString< std::minus< Result > > | |
| COpString< std::multiplies< Result > > | |
| COpString< std::divides< Result > > | |
| COpString< std::modulus< Result > > | |
| COpString< std::negate< Result > > | |
| CUnaryNode | |
| CBinaryNode | |
| CSumNode | |
| CScalar | This is a simple scalar statistic, like a counter |
| CAverage | A stat that calculates the per tick average of a value |
| CValue | |
| CVector | A vector of scalar stats |
| CAverageVector | A vector of Average stats |
| CVector2d | A 2-Dimensional vecto of scalar stats |
| CDistribution | A simple distribution stat |
| CHistogram | A simple histogram stat |
| CStandardDeviation | Calculates the mean and variance of all the samples |
| CAverageDeviation | Calculates the per tick mean and variance of the samples |
| CVectorDistribution | A vector of distributions |
| CVectorStandardDeviation | This is a vector of StandardDeviation stats |
| CVectorAverageDeviation | This is a vector of AverageDeviation stats |
| CFormulaInfoProxy | |
| CSparseHistInfoProxy | |
| CSparseHistBase | Implementation of a sparse histogram stat |
| CSparseHistogram | |
| CFormula | A formula for statistics that is calculated when printed |
| CFormulaNode | |
| CTemp | Helper class to construct formula node trees |
| CGroup | Statistics container |
| CHdf5 | |
| CInfo | |
| CScalarInfo | |
| CVectorInfo | |
| CDistInfo | |
| CVectorDistInfo | |
| CVector2dInfo | |
| CFormulaInfo | |
| CSparseHistInfo | |
| COutput | |
| CStorageParams | |
| ►CStatStor | Templatized storage and interface for a simple scalar stat |
| CParams | |
| ►CAvgStor | Templatized storage and interface to a per-tick average stat |
| CParams | |
| CDistParams | The parameters for a distribution stat |
| ►CDistStor | Templatized storage and interface for a distribution stat |
| CParams | The parameters for a distribution stat |
| ►CHistStor | Templatized storage and interface for a histogram stat |
| CParams | The parameters for a distribution stat |
| ►CSampleStor | Templatized storage and interface for a distribution that calculates mean and variance |
| CParams | |
| ►CAvgSampleStor | Templatized storage for distribution that calculates per tick mean and variance |
| CParams | |
| ►CSparseHistStor | Templatized storage and interface for a sparse histogram stat |
| CParams | The parameters for a sparse histogram stat |
| CBasePrint | |
| CScalarPrint | |
| CVectorPrint | |
| CDistPrint | |
| CSparseHistPrint | |
| CText | |
| CDistData | General container for distribution data |
| CSparseHistData | Data structure of sparse histogram |
| CStatEvent | Event to dump and/or reset the statistics |
| ►Nstl_helpers | |
| CIsHelpedContainer | |
| CIsHelpedContainer< std::vector< Types... > > | |
| ►Ntrace | |
| ►CArmNativeTrace | |
| CThreadState | |
| ►CTarmacBaseRecord | |
| CInstEntry | TARMAC instruction trace record |
| CMemEntry | TARMAC memory access trace record (stores only) |
| CRegEntry | TARMAC register trace record |
| ►CTarmacParserRecord | |
| CParserInstEntry | |
| CParserMemEntry | |
| CParserRegEntry | |
| CTarmacParserRecordEvent | Event triggered to check the value of the destination registers |
| CTarmacParser | Tarmac Parser: this tracer parses an existing Tarmac trace and it diffs it with gem5 simulation status, comparing results and reporting architectural mismatches if any |
| ►CTarmacTracerRecord | TarmacTracer Record: Record generated by the TarmacTracer for every executed instruction |
| CTraceInstEntry | Instruction Entry |
| CTraceMemEntry | Memory Entry |
| CTraceRegEntry | Register Entry |
| ►CTarmacTracerRecordV8 | TarmacTracer record for ARMv8 CPUs: The record is adding some data to the base TarmacTracer record |
| CTraceEntryV8 | General data shared by all v8 entries |
| CTraceInstEntryV8 | Instruction entry for v8 records |
| CTraceMemEntryV8 | Memory Entry for V8 |
| CTraceRegEntryV8 | Register entry for v8 records |
| CTarmacContext | This object type is encapsulating the informations needed by a Tarmac record to generate it's own entries |
| CTarmacTracer | Tarmac Tracer: this tracer generates a new Tarmac Record for every instruction being executed in gem5 |
| CSparcNativeTrace | |
| ►CX86NativeTrace | |
| CThreadState | |
| CLogger | Debug logging base class |
| COstreamLogger | Logging wrapper for ostreams with the format: <when>: <name>: <message-body> |
| CExeTracerRecord | |
| CExeTracer | |
| CInstPBTraceRecord | This in an instruction tracer that records the flow of instructions through multiple cpus and systems to a protobuf file specified by proto/inst.proto for further analysis |
| CInstPBTrace | |
| CIntelTraceRecord | |
| CIntelTrace | |
| CNativeTraceRecord | |
| CNativeTrace | |
| ►CInstRecord | |
| CData | |
| CInstTracer | |
| ►NVegaISA | Classes that represnt vector/scalar operands in VEGA ISA |
| CVegaFault | |
| CPageFault | |
| CDecoder | |
| CInFmt_DS | |
| CInFmt_DS_1 | |
| CInFmt_EXP | |
| CInFmt_EXP_1 | |
| CInFmt_FLAT | |
| CInFmt_FLAT_1 | |
| CInFmt_INST | |
| CInFmt_MIMG | |
| CInFmt_MIMG_1 | |
| CInFmt_MTBUF | |
| CInFmt_MTBUF_1 | |
| CInFmt_MUBUF | |
| CInFmt_MUBUF_1 | |
| CInFmt_SMEM | |
| CInFmt_SMEM_1 | |
| CInFmt_SOP1 | |
| CInFmt_SOP2 | |
| CInFmt_SOPC | |
| CInFmt_SOPK | |
| CInFmt_SOPP | |
| CInFmt_VINTRP | |
| CInFmt_VOP1 | |
| CInFmt_VOP2 | |
| CInFmt_VOP3A | |
| CInFmt_VOP3_1 | |
| CInFmt_VOP3B | |
| CInFmt_VOPC | |
| CInFmt_VOP_DPP | |
| CInFmt_VOP_SDWA | |
| CInFmt_VOP_SDWAB | |
| CInFmt_VOP3P | |
| CInFmt_VOP3P_1 | |
| CInstFormat | |
| CGPUISA | |
| CStatusReg | |
| CVEGAGPUStaticInst | |
| CInst_SOP2__S_ADD_U32 | |
| CInst_SOP2__S_SUB_U32 | |
| CInst_SOP2__S_ADD_I32 | |
| CInst_SOP2__S_SUB_I32 | |
| CInst_SOP2__S_ADDC_U32 | |
| CInst_SOP2__S_SUBB_U32 | |
| CInst_SOP2__S_MIN_I32 | |
| CInst_SOP2__S_MIN_U32 | |
| CInst_SOP2__S_MAX_I32 | |
| CInst_SOP2__S_MAX_U32 | |
| CInst_SOP2__S_CSELECT_B32 | |
| CInst_SOP2__S_CSELECT_B64 | |
| CInst_SOP2__S_AND_B32 | |
| CInst_SOP2__S_AND_B64 | |
| CInst_SOP2__S_OR_B32 | |
| CInst_SOP2__S_OR_B64 | |
| CInst_SOP2__S_XOR_B32 | |
| CInst_SOP2__S_XOR_B64 | |
| CInst_SOP2__S_ANDN2_B32 | |
| CInst_SOP2__S_ANDN2_B64 | |
| CInst_SOP2__S_ORN2_B32 | |
| CInst_SOP2__S_ORN2_B64 | |
| CInst_SOP2__S_NAND_B32 | |
| CInst_SOP2__S_NAND_B64 | |
| CInst_SOP2__S_NOR_B32 | |
| CInst_SOP2__S_NOR_B64 | |
| CInst_SOP2__S_XNOR_B32 | |
| CInst_SOP2__S_XNOR_B64 | |
| CInst_SOP2__S_LSHL_B32 | |
| CInst_SOP2__S_LSHL_B64 | |
| CInst_SOP2__S_LSHR_B32 | |
| CInst_SOP2__S_LSHR_B64 | |
| CInst_SOP2__S_ASHR_I32 | |
| CInst_SOP2__S_ASHR_I64 | |
| CInst_SOP2__S_BFM_B32 | |
| CInst_SOP2__S_BFM_B64 | |
| CInst_SOP2__S_MUL_I32 | |
| CInst_SOP2__S_BFE_U32 | |
| CInst_SOP2__S_BFE_I32 | |
| CInst_SOP2__S_BFE_U64 | |
| CInst_SOP2__S_BFE_I64 | |
| CInst_SOP2__S_CBRANCH_G_FORK | |
| CInst_SOP2__S_ABSDIFF_I32 | |
| CInst_SOP2__S_RFE_RESTORE_B64 | |
| CInst_SOP2__S_MUL_HI_U32 | |
| CInst_SOP2__S_MUL_HI_I32 | |
| CInst_SOPK__S_MOVK_I32 | |
| CInst_SOPK__S_CMOVK_I32 | |
| CInst_SOPK__S_CMPK_EQ_I32 | |
| CInst_SOPK__S_CMPK_LG_I32 | |
| CInst_SOPK__S_CMPK_GT_I32 | |
| CInst_SOPK__S_CMPK_GE_I32 | |
| CInst_SOPK__S_CMPK_LT_I32 | |
| CInst_SOPK__S_CMPK_LE_I32 | |
| CInst_SOPK__S_CMPK_EQ_U32 | |
| CInst_SOPK__S_CMPK_LG_U32 | |
| CInst_SOPK__S_CMPK_GT_U32 | |
| CInst_SOPK__S_CMPK_GE_U32 | |
| CInst_SOPK__S_CMPK_LT_U32 | |
| CInst_SOPK__S_CMPK_LE_U32 | |
| CInst_SOPK__S_ADDK_I32 | |
| CInst_SOPK__S_MULK_I32 | |
| CInst_SOPK__S_CBRANCH_I_FORK | |
| CInst_SOPK__S_GETREG_B32 | |
| CInst_SOPK__S_SETREG_B32 | |
| CInst_SOPK__S_SETREG_IMM32_B32 | |
| CInst_SOP1__S_MOV_B32 | |
| CInst_SOP1__S_MOV_B64 | |
| CInst_SOP1__S_CMOV_B32 | |
| CInst_SOP1__S_CMOV_B64 | |
| CInst_SOP1__S_NOT_B32 | |
| CInst_SOP1__S_NOT_B64 | |
| CInst_SOP1__S_WQM_B32 | |
| CInst_SOP1__S_WQM_B64 | |
| CInst_SOP1__S_BREV_B32 | |
| CInst_SOP1__S_BREV_B64 | |
| CInst_SOP1__S_BCNT0_I32_B32 | |
| CInst_SOP1__S_BCNT0_I32_B64 | |
| CInst_SOP1__S_BCNT1_I32_B32 | |
| CInst_SOP1__S_BCNT1_I32_B64 | |
| CInst_SOP1__S_FF0_I32_B32 | |
| CInst_SOP1__S_FF0_I32_B64 | |
| CInst_SOP1__S_FF1_I32_B32 | |
| CInst_SOP1__S_FF1_I32_B64 | |
| CInst_SOP1__S_FLBIT_I32_B32 | |
| CInst_SOP1__S_FLBIT_I32_B64 | |
| CInst_SOP1__S_FLBIT_I32 | |
| CInst_SOP1__S_FLBIT_I32_I64 | |
| CInst_SOP1__S_SEXT_I32_I8 | |
| CInst_SOP1__S_SEXT_I32_I16 | |
| CInst_SOP1__S_BITSET0_B32 | |
| CInst_SOP1__S_BITSET0_B64 | |
| CInst_SOP1__S_BITSET1_B32 | |
| CInst_SOP1__S_BITSET1_B64 | |
| CInst_SOP1__S_GETPC_B64 | |
| CInst_SOP1__S_SETPC_B64 | |
| CInst_SOP1__S_SWAPPC_B64 | |
| CInst_SOP1__S_RFE_B64 | |
| CInst_SOP1__S_AND_SAVEEXEC_B64 | |
| CInst_SOP1__S_OR_SAVEEXEC_B64 | |
| CInst_SOP1__S_XOR_SAVEEXEC_B64 | |
| CInst_SOP1__S_ANDN2_SAVEEXEC_B64 | |
| CInst_SOP1__S_ORN2_SAVEEXEC_B64 | |
| CInst_SOP1__S_NAND_SAVEEXEC_B64 | |
| CInst_SOP1__S_NOR_SAVEEXEC_B64 | |
| CInst_SOP1__S_XNOR_SAVEEXEC_B64 | |
| CInst_SOP1__S_QUADMASK_B32 | |
| CInst_SOP1__S_QUADMASK_B64 | |
| CInst_SOP1__S_MOVRELS_B32 | |
| CInst_SOP1__S_MOVRELS_B64 | |
| CInst_SOP1__S_MOVRELD_B32 | |
| CInst_SOP1__S_MOVRELD_B64 | |
| CInst_SOP1__S_CBRANCH_JOIN | |
| CInst_SOP1__S_ABS_I32 | |
| CInst_SOP1__S_MOV_FED_B32 | |
| CInst_SOP1__S_SET_GPR_IDX_IDX | |
| CInst_SOPC__S_CMP_EQ_I32 | |
| CInst_SOPC__S_CMP_LG_I32 | |
| CInst_SOPC__S_CMP_GT_I32 | |
| CInst_SOPC__S_CMP_GE_I32 | |
| CInst_SOPC__S_CMP_LT_I32 | |
| CInst_SOPC__S_CMP_LE_I32 | |
| CInst_SOPC__S_CMP_EQ_U32 | |
| CInst_SOPC__S_CMP_LG_U32 | |
| CInst_SOPC__S_CMP_GT_U32 | |
| CInst_SOPC__S_CMP_GE_U32 | |
| CInst_SOPC__S_CMP_LT_U32 | |
| CInst_SOPC__S_CMP_LE_U32 | |
| CInst_SOPC__S_BITCMP0_B32 | |
| CInst_SOPC__S_BITCMP1_B32 | |
| CInst_SOPC__S_BITCMP0_B64 | |
| CInst_SOPC__S_BITCMP1_B64 | |
| CInst_SOPC__S_SETVSKIP | |
| CInst_SOPC__S_SET_GPR_IDX_ON | |
| CInst_SOPC__S_CMP_EQ_U64 | |
| CInst_SOPC__S_CMP_LG_U64 | |
| CInst_SOPP__S_NOP | |
| CInst_SOPP__S_ENDPGM | |
| CInst_SOPP__S_BRANCH | |
| CInst_SOPP__S_WAKEUP | |
| CInst_SOPP__S_CBRANCH_SCC0 | |
| CInst_SOPP__S_CBRANCH_SCC1 | |
| CInst_SOPP__S_CBRANCH_VCCZ | |
| CInst_SOPP__S_CBRANCH_VCCNZ | |
| CInst_SOPP__S_CBRANCH_EXECZ | |
| CInst_SOPP__S_CBRANCH_EXECNZ | |
| CInst_SOPP__S_BARRIER | |
| CInst_SOPP__S_SETKILL | |
| CInst_SOPP__S_WAITCNT | |
| CInst_SOPP__S_SETHALT | |
| CInst_SOPP__S_SLEEP | |
| CInst_SOPP__S_SETPRIO | |
| CInst_SOPP__S_SENDMSG | |
| CInst_SOPP__S_SENDMSGHALT | |
| CInst_SOPP__S_TRAP | |
| CInst_SOPP__S_ICACHE_INV | |
| CInst_SOPP__S_INCPERFLEVEL | |
| CInst_SOPP__S_DECPERFLEVEL | |
| CInst_SOPP__S_TTRACEDATA | |
| CInst_SOPP__S_CBRANCH_CDBGSYS | |
| CInst_SOPP__S_CBRANCH_CDBGUSER | |
| CInst_SOPP__S_CBRANCH_CDBGSYS_OR_USER | |
| CInst_SOPP__S_CBRANCH_CDBGSYS_AND_USER | |
| CInst_SOPP__S_ENDPGM_SAVED | |
| CInst_SOPP__S_SET_GPR_IDX_OFF | |
| CInst_SOPP__S_SET_GPR_IDX_MODE | |
| CInst_SMEM__S_LOAD_DWORD | |
| CInst_SMEM__S_LOAD_DWORDX2 | |
| CInst_SMEM__S_LOAD_DWORDX4 | |
| CInst_SMEM__S_LOAD_DWORDX8 | |
| CInst_SMEM__S_LOAD_DWORDX16 | |
| CInst_SMEM__S_BUFFER_LOAD_DWORD | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX2 | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX4 | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX8 | |
| CInst_SMEM__S_BUFFER_LOAD_DWORDX16 | |
| CInst_SMEM__S_STORE_DWORD | |
| CInst_SMEM__S_STORE_DWORDX2 | |
| CInst_SMEM__S_STORE_DWORDX4 | |
| CInst_SMEM__S_BUFFER_STORE_DWORD | |
| CInst_SMEM__S_BUFFER_STORE_DWORDX2 | |
| CInst_SMEM__S_BUFFER_STORE_DWORDX4 | |
| CInst_SMEM__S_DCACHE_INV | |
| CInst_SMEM__S_DCACHE_WB | |
| CInst_SMEM__S_DCACHE_INV_VOL | |
| CInst_SMEM__S_DCACHE_WB_VOL | |
| CInst_SMEM__S_MEMTIME | |
| CInst_SMEM__S_MEMREALTIME | |
| CInst_SMEM__S_ATC_PROBE | |
| CInst_SMEM__S_ATC_PROBE_BUFFER | |
| CInst_VOP2__V_CNDMASK_B32 | |
| CInst_VOP2__V_ADD_F32 | |
| CInst_VOP2__V_SUB_F32 | |
| CInst_VOP2__V_SUBREV_F32 | |
| CInst_VOP2__V_MUL_LEGACY_F32 | |
| CInst_VOP2__V_MUL_F32 | |
| CInst_VOP2__V_MUL_I32_I24 | |
| CInst_VOP2__V_MUL_HI_I32_I24 | |
| CInst_VOP2__V_MUL_U32_U24 | |
| CInst_VOP2__V_MUL_HI_U32_U24 | |
| CInst_VOP2__V_MIN_F32 | |
| CInst_VOP2__V_MAX_F32 | |
| CInst_VOP2__V_MIN_I32 | |
| CInst_VOP2__V_MAX_I32 | |
| CInst_VOP2__V_MIN_U32 | |
| CInst_VOP2__V_MAX_U32 | |
| CInst_VOP2__V_LSHRREV_B32 | |
| CInst_VOP2__V_ASHRREV_I32 | |
| CInst_VOP2__V_LSHLREV_B32 | |
| CInst_VOP2__V_AND_B32 | |
| CInst_VOP2__V_OR_B32 | |
| CInst_VOP2__V_XOR_B32 | |
| CInst_VOP2__V_MAC_F32 | |
| CInst_VOP2__V_MADMK_F32 | |
| CInst_VOP2__V_MADAK_F32 | |
| CInst_VOP2__V_ADD_CO_U32 | |
| CInst_VOP2__V_SUB_CO_U32 | |
| CInst_VOP2__V_SUBREV_CO_U32 | |
| CInst_VOP2__V_ADDC_CO_U32 | |
| CInst_VOP2__V_SUBB_CO_U32 | |
| CInst_VOP2__V_SUBBREV_CO_U32 | |
| CInst_VOP2__V_ADD_F16 | |
| CInst_VOP2__V_SUB_F16 | |
| CInst_VOP2__V_SUBREV_F16 | |
| CInst_VOP2__V_MUL_F16 | |
| CInst_VOP2__V_MAC_F16 | |
| CInst_VOP2__V_MADMK_F16 | |
| CInst_VOP2__V_MADAK_F16 | |
| CInst_VOP2__V_ADD_U16 | |
| CInst_VOP2__V_SUB_U16 | |
| CInst_VOP2__V_SUBREV_U16 | |
| CInst_VOP2__V_MUL_LO_U16 | |
| CInst_VOP2__V_LSHLREV_B16 | |
| CInst_VOP2__V_LSHRREV_B16 | |
| CInst_VOP2__V_ASHRREV_I16 | |
| CInst_VOP2__V_MAX_F16 | |
| CInst_VOP2__V_MIN_F16 | |
| CInst_VOP2__V_MAX_U16 | |
| CInst_VOP2__V_MAX_I16 | |
| CInst_VOP2__V_MIN_U16 | |
| CInst_VOP2__V_MIN_I16 | |
| CInst_VOP2__V_LDEXP_F16 | |
| CInst_VOP2__V_ADD_U32 | |
| CInst_VOP2__V_SUB_U32 | |
| CInst_VOP2__V_SUBREV_U32 | |
| CInst_VOP1__V_NOP | |
| CInst_VOP1__V_MOV_B32 | |
| CInst_VOP1__V_READFIRSTLANE_B32 | |
| CInst_VOP1__V_CVT_I32_F64 | |
| CInst_VOP1__V_CVT_F64_I32 | |
| CInst_VOP1__V_CVT_F32_I32 | |
| CInst_VOP1__V_CVT_F32_U32 | |
| CInst_VOP1__V_CVT_U32_F32 | |
| CInst_VOP1__V_CVT_I32_F32 | |
| CInst_VOP1__V_MOV_FED_B32 | |
| CInst_VOP1__V_CVT_F16_F32 | |
| CInst_VOP1__V_CVT_F32_F16 | |
| CInst_VOP1__V_CVT_RPI_I32_F32 | |
| CInst_VOP1__V_CVT_FLR_I32_F32 | |
| CInst_VOP1__V_CVT_OFF_F32_I4 | |
| CInst_VOP1__V_CVT_F32_F64 | |
| CInst_VOP1__V_CVT_F64_F32 | |
| CInst_VOP1__V_CVT_F32_UBYTE0 | |
| CInst_VOP1__V_CVT_F32_UBYTE1 | |
| CInst_VOP1__V_CVT_F32_UBYTE2 | |
| CInst_VOP1__V_CVT_F32_UBYTE3 | |
| CInst_VOP1__V_CVT_U32_F64 | |
| CInst_VOP1__V_CVT_F64_U32 | |
| CInst_VOP1__V_TRUNC_F64 | |
| CInst_VOP1__V_CEIL_F64 | |
| CInst_VOP1__V_RNDNE_F64 | |
| CInst_VOP1__V_FLOOR_F64 | |
| CInst_VOP1__V_FRACT_F32 | |
| CInst_VOP1__V_TRUNC_F32 | |
| CInst_VOP1__V_CEIL_F32 | |
| CInst_VOP1__V_RNDNE_F32 | |
| CInst_VOP1__V_FLOOR_F32 | |
| CInst_VOP1__V_EXP_F32 | |
| CInst_VOP1__V_LOG_F32 | |
| CInst_VOP1__V_RCP_F32 | |
| CInst_VOP1__V_RCP_IFLAG_F32 | |
| CInst_VOP1__V_RSQ_F32 | |
| CInst_VOP1__V_RCP_F64 | |
| CInst_VOP1__V_RSQ_F64 | |
| CInst_VOP1__V_SQRT_F32 | |
| CInst_VOP1__V_SQRT_F64 | |
| CInst_VOP1__V_SIN_F32 | |
| CInst_VOP1__V_COS_F32 | |
| CInst_VOP1__V_NOT_B32 | |
| CInst_VOP1__V_BFREV_B32 | |
| CInst_VOP1__V_FFBH_U32 | |
| CInst_VOP1__V_FFBL_B32 | |
| CInst_VOP1__V_FFBH_I32 | |
| CInst_VOP1__V_FREXP_EXP_I32_F64 | |
| CInst_VOP1__V_FREXP_MANT_F64 | |
| CInst_VOP1__V_FRACT_F64 | |
| CInst_VOP1__V_FREXP_EXP_I32_F32 | |
| CInst_VOP1__V_FREXP_MANT_F32 | |
| CInst_VOP1__V_CLREXCP | |
| CInst_VOP1__V_CVT_F16_U16 | |
| CInst_VOP1__V_CVT_F16_I16 | |
| CInst_VOP1__V_CVT_U16_F16 | |
| CInst_VOP1__V_CVT_I16_F16 | |
| CInst_VOP1__V_RCP_F16 | |
| CInst_VOP1__V_SQRT_F16 | |
| CInst_VOP1__V_RSQ_F16 | |
| CInst_VOP1__V_LOG_F16 | |
| CInst_VOP1__V_EXP_F16 | |
| CInst_VOP1__V_FREXP_MANT_F16 | |
| CInst_VOP1__V_FREXP_EXP_I16_F16 | |
| CInst_VOP1__V_FLOOR_F16 | |
| CInst_VOP1__V_CEIL_F16 | |
| CInst_VOP1__V_TRUNC_F16 | |
| CInst_VOP1__V_RNDNE_F16 | |
| CInst_VOP1__V_FRACT_F16 | |
| CInst_VOP1__V_SIN_F16 | |
| CInst_VOP1__V_COS_F16 | |
| CInst_VOP1__V_EXP_LEGACY_F32 | |
| CInst_VOP1__V_LOG_LEGACY_F32 | |
| CInst_VOPC__V_CMP_CLASS_F32 | |
| CInst_VOPC__V_CMPX_CLASS_F32 | |
| CInst_VOPC__V_CMP_CLASS_F64 | |
| CInst_VOPC__V_CMPX_CLASS_F64 | |
| CInst_VOPC__V_CMP_CLASS_F16 | |
| CInst_VOPC__V_CMPX_CLASS_F16 | |
| CInst_VOPC__V_CMP_F_F16 | |
| CInst_VOPC__V_CMP_LT_F16 | |
| CInst_VOPC__V_CMP_EQ_F16 | |
| CInst_VOPC__V_CMP_LE_F16 | |
| CInst_VOPC__V_CMP_GT_F16 | |
| CInst_VOPC__V_CMP_LG_F16 | |
| CInst_VOPC__V_CMP_GE_F16 | |
| CInst_VOPC__V_CMP_O_F16 | |
| CInst_VOPC__V_CMP_U_F16 | |
| CInst_VOPC__V_CMP_NGE_F16 | |
| CInst_VOPC__V_CMP_NLG_F16 | |
| CInst_VOPC__V_CMP_NGT_F16 | |
| CInst_VOPC__V_CMP_NLE_F16 | |
| CInst_VOPC__V_CMP_NEQ_F16 | |
| CInst_VOPC__V_CMP_NLT_F16 | |
| CInst_VOPC__V_CMP_TRU_F16 | |
| CInst_VOPC__V_CMPX_F_F16 | |
| CInst_VOPC__V_CMPX_LT_F16 | |
| CInst_VOPC__V_CMPX_EQ_F16 | |
| CInst_VOPC__V_CMPX_LE_F16 | |
| CInst_VOPC__V_CMPX_GT_F16 | |
| CInst_VOPC__V_CMPX_LG_F16 | |
| CInst_VOPC__V_CMPX_GE_F16 | |
| CInst_VOPC__V_CMPX_O_F16 | |
| CInst_VOPC__V_CMPX_U_F16 | |
| CInst_VOPC__V_CMPX_NGE_F16 | |
| CInst_VOPC__V_CMPX_NLG_F16 | |
| CInst_VOPC__V_CMPX_NGT_F16 | |
| CInst_VOPC__V_CMPX_NLE_F16 | |
| CInst_VOPC__V_CMPX_NEQ_F16 | |
| CInst_VOPC__V_CMPX_NLT_F16 | |
| CInst_VOPC__V_CMPX_TRU_F16 | |
| CInst_VOPC__V_CMP_F_F32 | |
| CInst_VOPC__V_CMP_LT_F32 | |
| CInst_VOPC__V_CMP_EQ_F32 | |
| CInst_VOPC__V_CMP_LE_F32 | |
| CInst_VOPC__V_CMP_GT_F32 | |
| CInst_VOPC__V_CMP_LG_F32 | |
| CInst_VOPC__V_CMP_GE_F32 | |
| CInst_VOPC__V_CMP_O_F32 | |
| CInst_VOPC__V_CMP_U_F32 | |
| CInst_VOPC__V_CMP_NGE_F32 | |
| CInst_VOPC__V_CMP_NLG_F32 | |
| CInst_VOPC__V_CMP_NGT_F32 | |
| CInst_VOPC__V_CMP_NLE_F32 | |
| CInst_VOPC__V_CMP_NEQ_F32 | |
| CInst_VOPC__V_CMP_NLT_F32 | |
| CInst_VOPC__V_CMP_TRU_F32 | |
| CInst_VOPC__V_CMPX_F_F32 | |
| CInst_VOPC__V_CMPX_LT_F32 | |
| CInst_VOPC__V_CMPX_EQ_F32 | |
| CInst_VOPC__V_CMPX_LE_F32 | |
| CInst_VOPC__V_CMPX_GT_F32 | |
| CInst_VOPC__V_CMPX_LG_F32 | |
| CInst_VOPC__V_CMPX_GE_F32 | |
| CInst_VOPC__V_CMPX_O_F32 | |
| CInst_VOPC__V_CMPX_U_F32 | |
| CInst_VOPC__V_CMPX_NGE_F32 | |
| CInst_VOPC__V_CMPX_NLG_F32 | |
| CInst_VOPC__V_CMPX_NGT_F32 | |
| CInst_VOPC__V_CMPX_NLE_F32 | |
| CInst_VOPC__V_CMPX_NEQ_F32 | |
| CInst_VOPC__V_CMPX_NLT_F32 | |
| CInst_VOPC__V_CMPX_TRU_F32 | |
| CInst_VOPC__V_CMP_F_F64 | |
| CInst_VOPC__V_CMP_LT_F64 | |
| CInst_VOPC__V_CMP_EQ_F64 | |
| CInst_VOPC__V_CMP_LE_F64 | |
| CInst_VOPC__V_CMP_GT_F64 | |
| CInst_VOPC__V_CMP_LG_F64 | |
| CInst_VOPC__V_CMP_GE_F64 | |
| CInst_VOPC__V_CMP_O_F64 | |
| CInst_VOPC__V_CMP_U_F64 | |
| CInst_VOPC__V_CMP_NGE_F64 | |
| CInst_VOPC__V_CMP_NLG_F64 | |
| CInst_VOPC__V_CMP_NGT_F64 | |
| CInst_VOPC__V_CMP_NLE_F64 | |
| CInst_VOPC__V_CMP_NEQ_F64 | |
| CInst_VOPC__V_CMP_NLT_F64 | |
| CInst_VOPC__V_CMP_TRU_F64 | |
| CInst_VOPC__V_CMPX_F_F64 | |
| CInst_VOPC__V_CMPX_LT_F64 | |
| CInst_VOPC__V_CMPX_EQ_F64 | |
| CInst_VOPC__V_CMPX_LE_F64 | |
| CInst_VOPC__V_CMPX_GT_F64 | |
| CInst_VOPC__V_CMPX_LG_F64 | |
| CInst_VOPC__V_CMPX_GE_F64 | |
| CInst_VOPC__V_CMPX_O_F64 | |
| CInst_VOPC__V_CMPX_U_F64 | |
| CInst_VOPC__V_CMPX_NGE_F64 | |
| CInst_VOPC__V_CMPX_NLG_F64 | |
| CInst_VOPC__V_CMPX_NGT_F64 | |
| CInst_VOPC__V_CMPX_NLE_F64 | |
| CInst_VOPC__V_CMPX_NEQ_F64 | |
| CInst_VOPC__V_CMPX_NLT_F64 | |
| CInst_VOPC__V_CMPX_TRU_F64 | |
| CInst_VOPC__V_CMP_F_I16 | |
| CInst_VOPC__V_CMP_LT_I16 | |
| CInst_VOPC__V_CMP_EQ_I16 | |
| CInst_VOPC__V_CMP_LE_I16 | |
| CInst_VOPC__V_CMP_GT_I16 | |
| CInst_VOPC__V_CMP_NE_I16 | |
| CInst_VOPC__V_CMP_GE_I16 | |
| CInst_VOPC__V_CMP_T_I16 | |
| CInst_VOPC__V_CMP_F_U16 | |
| CInst_VOPC__V_CMP_LT_U16 | |
| CInst_VOPC__V_CMP_EQ_U16 | |
| CInst_VOPC__V_CMP_LE_U16 | |
| CInst_VOPC__V_CMP_GT_U16 | |
| CInst_VOPC__V_CMP_NE_U16 | |
| CInst_VOPC__V_CMP_GE_U16 | |
| CInst_VOPC__V_CMP_T_U16 | |
| CInst_VOPC__V_CMPX_F_I16 | |
| CInst_VOPC__V_CMPX_LT_I16 | |
| CInst_VOPC__V_CMPX_EQ_I16 | |
| CInst_VOPC__V_CMPX_LE_I16 | |
| CInst_VOPC__V_CMPX_GT_I16 | |
| CInst_VOPC__V_CMPX_NE_I16 | |
| CInst_VOPC__V_CMPX_GE_I16 | |
| CInst_VOPC__V_CMPX_T_I16 | |
| CInst_VOPC__V_CMPX_F_U16 | |
| CInst_VOPC__V_CMPX_LT_U16 | |
| CInst_VOPC__V_CMPX_EQ_U16 | |
| CInst_VOPC__V_CMPX_LE_U16 | |
| CInst_VOPC__V_CMPX_GT_U16 | |
| CInst_VOPC__V_CMPX_NE_U16 | |
| CInst_VOPC__V_CMPX_GE_U16 | |
| CInst_VOPC__V_CMPX_T_U16 | |
| CInst_VOPC__V_CMP_F_I32 | |
| CInst_VOPC__V_CMP_LT_I32 | |
| CInst_VOPC__V_CMP_EQ_I32 | |
| CInst_VOPC__V_CMP_LE_I32 | |
| CInst_VOPC__V_CMP_GT_I32 | |
| CInst_VOPC__V_CMP_NE_I32 | |
| CInst_VOPC__V_CMP_GE_I32 | |
| CInst_VOPC__V_CMP_T_I32 | |
| CInst_VOPC__V_CMP_F_U32 | |
| CInst_VOPC__V_CMP_LT_U32 | |
| CInst_VOPC__V_CMP_EQ_U32 | |
| CInst_VOPC__V_CMP_LE_U32 | |
| CInst_VOPC__V_CMP_GT_U32 | |
| CInst_VOPC__V_CMP_NE_U32 | |
| CInst_VOPC__V_CMP_GE_U32 | |
| CInst_VOPC__V_CMP_T_U32 | |
| CInst_VOPC__V_CMPX_F_I32 | |
| CInst_VOPC__V_CMPX_LT_I32 | |
| CInst_VOPC__V_CMPX_EQ_I32 | |
| CInst_VOPC__V_CMPX_LE_I32 | |
| CInst_VOPC__V_CMPX_GT_I32 | |
| CInst_VOPC__V_CMPX_NE_I32 | |
| CInst_VOPC__V_CMPX_GE_I32 | |
| CInst_VOPC__V_CMPX_T_I32 | |
| CInst_VOPC__V_CMPX_F_U32 | |
| CInst_VOPC__V_CMPX_LT_U32 | |
| CInst_VOPC__V_CMPX_EQ_U32 | |
| CInst_VOPC__V_CMPX_LE_U32 | |
| CInst_VOPC__V_CMPX_GT_U32 | |
| CInst_VOPC__V_CMPX_NE_U32 | |
| CInst_VOPC__V_CMPX_GE_U32 | |
| CInst_VOPC__V_CMPX_T_U32 | |
| CInst_VOPC__V_CMP_F_I64 | |
| CInst_VOPC__V_CMP_LT_I64 | |
| CInst_VOPC__V_CMP_EQ_I64 | |
| CInst_VOPC__V_CMP_LE_I64 | |
| CInst_VOPC__V_CMP_GT_I64 | |
| CInst_VOPC__V_CMP_NE_I64 | |
| CInst_VOPC__V_CMP_GE_I64 | |
| CInst_VOPC__V_CMP_T_I64 | |
| CInst_VOPC__V_CMP_F_U64 | |
| CInst_VOPC__V_CMP_LT_U64 | |
| CInst_VOPC__V_CMP_EQ_U64 | |
| CInst_VOPC__V_CMP_LE_U64 | |
| CInst_VOPC__V_CMP_GT_U64 | |
| CInst_VOPC__V_CMP_NE_U64 | |
| CInst_VOPC__V_CMP_GE_U64 | |
| CInst_VOPC__V_CMP_T_U64 | |
| CInst_VOPC__V_CMPX_F_I64 | |
| CInst_VOPC__V_CMPX_LT_I64 | |
| CInst_VOPC__V_CMPX_EQ_I64 | |
| CInst_VOPC__V_CMPX_LE_I64 | |
| CInst_VOPC__V_CMPX_GT_I64 | |
| CInst_VOPC__V_CMPX_NE_I64 | |
| CInst_VOPC__V_CMPX_GE_I64 | |
| CInst_VOPC__V_CMPX_T_I64 | |
| CInst_VOPC__V_CMPX_F_U64 | |
| CInst_VOPC__V_CMPX_LT_U64 | |
| CInst_VOPC__V_CMPX_EQ_U64 | |
| CInst_VOPC__V_CMPX_LE_U64 | |
| CInst_VOPC__V_CMPX_GT_U64 | |
| CInst_VOPC__V_CMPX_NE_U64 | |
| CInst_VOPC__V_CMPX_GE_U64 | |
| CInst_VOPC__V_CMPX_T_U64 | |
| CInst_VINTRP__V_INTERP_P1_F32 | |
| CInst_VINTRP__V_INTERP_P2_F32 | |
| CInst_VINTRP__V_INTERP_MOV_F32 | |
| CInst_VOP3__V_CMP_CLASS_F32 | |
| CInst_VOP3__V_CMPX_CLASS_F32 | |
| CInst_VOP3__V_CMP_CLASS_F64 | |
| CInst_VOP3__V_CMPX_CLASS_F64 | |
| CInst_VOP3__V_CMP_CLASS_F16 | |
| CInst_VOP3__V_CMPX_CLASS_F16 | |
| CInst_VOP3__V_CMP_F_F16 | |
| CInst_VOP3__V_CMP_LT_F16 | |
| CInst_VOP3__V_CMP_EQ_F16 | |
| CInst_VOP3__V_CMP_LE_F16 | |
| CInst_VOP3__V_CMP_GT_F16 | |
| CInst_VOP3__V_CMP_LG_F16 | |
| CInst_VOP3__V_CMP_GE_F16 | |
| CInst_VOP3__V_CMP_O_F16 | |
| CInst_VOP3__V_CMP_U_F16 | |
| CInst_VOP3__V_CMP_NGE_F16 | |
| CInst_VOP3__V_CMP_NLG_F16 | |
| CInst_VOP3__V_CMP_NGT_F16 | |
| CInst_VOP3__V_CMP_NLE_F16 | |
| CInst_VOP3__V_CMP_NEQ_F16 | |
| CInst_VOP3__V_CMP_NLT_F16 | |
| CInst_VOP3__V_CMP_TRU_F16 | |
| CInst_VOP3__V_CMPX_F_F16 | |
| CInst_VOP3__V_CMPX_LT_F16 | |
| CInst_VOP3__V_CMPX_EQ_F16 | |
| CInst_VOP3__V_CMPX_LE_F16 | |
| CInst_VOP3__V_CMPX_GT_F16 | |
| CInst_VOP3__V_CMPX_LG_F16 | |
| CInst_VOP3__V_CMPX_GE_F16 | |
| CInst_VOP3__V_CMPX_O_F16 | |
| CInst_VOP3__V_CMPX_U_F16 | |
| CInst_VOP3__V_CMPX_NGE_F16 | |
| CInst_VOP3__V_CMPX_NLG_F16 | |
| CInst_VOP3__V_CMPX_NGT_F16 | |
| CInst_VOP3__V_CMPX_NLE_F16 | |
| CInst_VOP3__V_CMPX_NEQ_F16 | |
| CInst_VOP3__V_CMPX_NLT_F16 | |
| CInst_VOP3__V_CMPX_TRU_F16 | |
| CInst_VOP3__V_CMP_F_F32 | |
| CInst_VOP3__V_CMP_LT_F32 | |
| CInst_VOP3__V_CMP_EQ_F32 | |
| CInst_VOP3__V_CMP_LE_F32 | |
| CInst_VOP3__V_CMP_GT_F32 | |
| CInst_VOP3__V_CMP_LG_F32 | |
| CInst_VOP3__V_CMP_GE_F32 | |
| CInst_VOP3__V_CMP_O_F32 | |
| CInst_VOP3__V_CMP_U_F32 | |
| CInst_VOP3__V_CMP_NGE_F32 | |
| CInst_VOP3__V_CMP_NLG_F32 | |
| CInst_VOP3__V_CMP_NGT_F32 | |
| CInst_VOP3__V_CMP_NLE_F32 | |
| CInst_VOP3__V_CMP_NEQ_F32 | |
| CInst_VOP3__V_CMP_NLT_F32 | |
| CInst_VOP3__V_CMP_TRU_F32 | |
| CInst_VOP3__V_CMPX_F_F32 | |
| CInst_VOP3__V_CMPX_LT_F32 | |
| CInst_VOP3__V_CMPX_EQ_F32 | |
| CInst_VOP3__V_CMPX_LE_F32 | |
| CInst_VOP3__V_CMPX_GT_F32 | |
| CInst_VOP3__V_CMPX_LG_F32 | |
| CInst_VOP3__V_CMPX_GE_F32 | |
| CInst_VOP3__V_CMPX_O_F32 | |
| CInst_VOP3__V_CMPX_U_F32 | |
| CInst_VOP3__V_CMPX_NGE_F32 | |
| CInst_VOP3__V_CMPX_NLG_F32 | |
| CInst_VOP3__V_CMPX_NGT_F32 | |
| CInst_VOP3__V_CMPX_NLE_F32 | |
| CInst_VOP3__V_CMPX_NEQ_F32 | |
| CInst_VOP3__V_CMPX_NLT_F32 | |
| CInst_VOP3__V_CMPX_TRU_F32 | |
| CInst_VOP3__V_CMP_F_F64 | |
| CInst_VOP3__V_CMP_LT_F64 | |
| CInst_VOP3__V_CMP_EQ_F64 | |
| CInst_VOP3__V_CMP_LE_F64 | |
| CInst_VOP3__V_CMP_GT_F64 | |
| CInst_VOP3__V_CMP_LG_F64 | |
| CInst_VOP3__V_CMP_GE_F64 | |
| CInst_VOP3__V_CMP_O_F64 | |
| CInst_VOP3__V_CMP_U_F64 | |
| CInst_VOP3__V_CMP_NGE_F64 | |
| CInst_VOP3__V_CMP_NLG_F64 | |
| CInst_VOP3__V_CMP_NGT_F64 | |
| CInst_VOP3__V_CMP_NLE_F64 | |
| CInst_VOP3__V_CMP_NEQ_F64 | |
| CInst_VOP3__V_CMP_NLT_F64 | |
| CInst_VOP3__V_CMP_TRU_F64 | |
| CInst_VOP3__V_CMPX_F_F64 | |
| CInst_VOP3__V_CMPX_LT_F64 | |
| CInst_VOP3__V_CMPX_EQ_F64 | |
| CInst_VOP3__V_CMPX_LE_F64 | |
| CInst_VOP3__V_CMPX_GT_F64 | |
| CInst_VOP3__V_CMPX_LG_F64 | |
| CInst_VOP3__V_CMPX_GE_F64 | |
| CInst_VOP3__V_CMPX_O_F64 | |
| CInst_VOP3__V_CMPX_U_F64 | |
| CInst_VOP3__V_CMPX_NGE_F64 | |
| CInst_VOP3__V_CMPX_NLG_F64 | |
| CInst_VOP3__V_CMPX_NGT_F64 | |
| CInst_VOP3__V_CMPX_NLE_F64 | |
| CInst_VOP3__V_CMPX_NEQ_F64 | |
| CInst_VOP3__V_CMPX_NLT_F64 | |
| CInst_VOP3__V_CMPX_TRU_F64 | |
| CInst_VOP3__V_CMP_F_I16 | |
| CInst_VOP3__V_CMP_LT_I16 | |
| CInst_VOP3__V_CMP_EQ_I16 | |
| CInst_VOP3__V_CMP_LE_I16 | |
| CInst_VOP3__V_CMP_GT_I16 | |
| CInst_VOP3__V_CMP_NE_I16 | |
| CInst_VOP3__V_CMP_GE_I16 | |
| CInst_VOP3__V_CMP_T_I16 | |
| CInst_VOP3__V_CMP_F_U16 | |
| CInst_VOP3__V_CMP_LT_U16 | |
| CInst_VOP3__V_CMP_EQ_U16 | |
| CInst_VOP3__V_CMP_LE_U16 | |
| CInst_VOP3__V_CMP_GT_U16 | |
| CInst_VOP3__V_CMP_NE_U16 | |
| CInst_VOP3__V_CMP_GE_U16 | |
| CInst_VOP3__V_CMP_T_U16 | |
| CInst_VOP3__V_CMPX_F_I16 | |
| CInst_VOP3__V_CMPX_LT_I16 | |
| CInst_VOP3__V_CMPX_EQ_I16 | |
| CInst_VOP3__V_CMPX_LE_I16 | |
| CInst_VOP3__V_CMPX_GT_I16 | |
| CInst_VOP3__V_CMPX_NE_I16 | |
| CInst_VOP3__V_CMPX_GE_I16 | |
| CInst_VOP3__V_CMPX_T_I16 | |
| CInst_VOP3__V_CMPX_F_U16 | |
| CInst_VOP3__V_CMPX_LT_U16 | |
| CInst_VOP3__V_CMPX_EQ_U16 | |
| CInst_VOP3__V_CMPX_LE_U16 | |
| CInst_VOP3__V_CMPX_GT_U16 | |
| CInst_VOP3__V_CMPX_NE_U16 | |
| CInst_VOP3__V_CMPX_GE_U16 | |
| CInst_VOP3__V_CMPX_T_U16 | |
| CInst_VOP3__V_CMP_F_I32 | |
| CInst_VOP3__V_CMP_LT_I32 | |
| CInst_VOP3__V_CMP_EQ_I32 | |
| CInst_VOP3__V_CMP_LE_I32 | |
| CInst_VOP3__V_CMP_GT_I32 | |
| CInst_VOP3__V_CMP_NE_I32 | |
| CInst_VOP3__V_CMP_GE_I32 | |
| CInst_VOP3__V_CMP_T_I32 | |
| CInst_VOP3__V_CMP_F_U32 | |
| CInst_VOP3__V_CMP_LT_U32 | |
| CInst_VOP3__V_CMP_EQ_U32 | |
| CInst_VOP3__V_CMP_LE_U32 | |
| CInst_VOP3__V_CMP_GT_U32 | |
| CInst_VOP3__V_CMP_NE_U32 | |
| CInst_VOP3__V_CMP_GE_U32 | |
| CInst_VOP3__V_CMP_T_U32 | |
| CInst_VOP3__V_CMPX_F_I32 | |
| CInst_VOP3__V_CMPX_LT_I32 | |
| CInst_VOP3__V_CMPX_EQ_I32 | |
| CInst_VOP3__V_CMPX_LE_I32 | |
| CInst_VOP3__V_CMPX_GT_I32 | |
| CInst_VOP3__V_CMPX_NE_I32 | |
| CInst_VOP3__V_CMPX_GE_I32 | |
| CInst_VOP3__V_CMPX_T_I32 | |
| CInst_VOP3__V_CMPX_F_U32 | |
| CInst_VOP3__V_CMPX_LT_U32 | |
| CInst_VOP3__V_CMPX_EQ_U32 | |
| CInst_VOP3__V_CMPX_LE_U32 | |
| CInst_VOP3__V_CMPX_GT_U32 | |
| CInst_VOP3__V_CMPX_NE_U32 | |
| CInst_VOP3__V_CMPX_GE_U32 | |
| CInst_VOP3__V_CMPX_T_U32 | |
| CInst_VOP3__V_CMP_F_I64 | |
| CInst_VOP3__V_CMP_LT_I64 | |
| CInst_VOP3__V_CMP_EQ_I64 | |
| CInst_VOP3__V_CMP_LE_I64 | |
| CInst_VOP3__V_CMP_GT_I64 | |
| CInst_VOP3__V_CMP_NE_I64 | |
| CInst_VOP3__V_CMP_GE_I64 | |
| CInst_VOP3__V_CMP_T_I64 | |
| CInst_VOP3__V_CMP_F_U64 | |
| CInst_VOP3__V_CMP_LT_U64 | |
| CInst_VOP3__V_CMP_EQ_U64 | |
| CInst_VOP3__V_CMP_LE_U64 | |
| CInst_VOP3__V_CMP_GT_U64 | |
| CInst_VOP3__V_CMP_NE_U64 | |
| CInst_VOP3__V_CMP_GE_U64 | |
| CInst_VOP3__V_CMP_T_U64 | |
| CInst_VOP3__V_CMPX_F_I64 | |
| CInst_VOP3__V_CMPX_LT_I64 | |
| CInst_VOP3__V_CMPX_EQ_I64 | |
| CInst_VOP3__V_CMPX_LE_I64 | |
| CInst_VOP3__V_CMPX_GT_I64 | |
| CInst_VOP3__V_CMPX_NE_I64 | |
| CInst_VOP3__V_CMPX_GE_I64 | |
| CInst_VOP3__V_CMPX_T_I64 | |
| CInst_VOP3__V_CMPX_F_U64 | |
| CInst_VOP3__V_CMPX_LT_U64 | |
| CInst_VOP3__V_CMPX_EQ_U64 | |
| CInst_VOP3__V_CMPX_LE_U64 | |
| CInst_VOP3__V_CMPX_GT_U64 | |
| CInst_VOP3__V_CMPX_NE_U64 | |
| CInst_VOP3__V_CMPX_GE_U64 | |
| CInst_VOP3__V_CMPX_T_U64 | |
| CInst_VOP3__V_CNDMASK_B32 | |
| CInst_VOP3__V_ADD_F32 | |
| CInst_VOP3__V_SUB_F32 | |
| CInst_VOP3__V_SUBREV_F32 | |
| CInst_VOP3__V_MUL_LEGACY_F32 | |
| CInst_VOP3__V_MUL_F32 | |
| CInst_VOP3__V_MUL_I32_I24 | |
| CInst_VOP3__V_MUL_HI_I32_I24 | |
| CInst_VOP3__V_MUL_U32_U24 | |
| CInst_VOP3__V_MUL_HI_U32_U24 | |
| CInst_VOP3__V_MIN_F32 | |
| CInst_VOP3__V_MAX_F32 | |
| CInst_VOP3__V_MIN_I32 | |
| CInst_VOP3__V_MAX_I32 | |
| CInst_VOP3__V_MIN_U32 | |
| CInst_VOP3__V_MAX_U32 | |
| CInst_VOP3__V_LSHRREV_B32 | |
| CInst_VOP3__V_ASHRREV_I32 | |
| CInst_VOP3__V_LSHLREV_B32 | |
| CInst_VOP3__V_AND_B32 | |
| CInst_VOP3__V_OR_B32 | |
| CInst_VOP3__V_OR3_B32 | |
| CInst_VOP3__V_XOR_B32 | |
| CInst_VOP3__V_MAC_F32 | |
| CInst_VOP3__V_ADD_CO_U32 | |
| CInst_VOP3__V_SUB_CO_U32 | |
| CInst_VOP3__V_SUBREV_CO_U32 | |
| CInst_VOP3__V_ADDC_CO_U32 | |
| CInst_VOP3__V_SUBB_CO_U32 | |
| CInst_VOP3__V_SUBBREV_CO_U32 | |
| CInst_VOP3__V_ADD_F16 | |
| CInst_VOP3__V_SUB_F16 | |
| CInst_VOP3__V_SUBREV_F16 | |
| CInst_VOP3__V_MUL_F16 | |
| CInst_VOP3__V_MAC_F16 | |
| CInst_VOP3__V_ADD_U16 | |
| CInst_VOP3__V_SUB_U16 | |
| CInst_VOP3__V_SUBREV_U16 | |
| CInst_VOP3__V_MUL_LO_U16 | |
| CInst_VOP3__V_LSHLREV_B16 | |
| CInst_VOP3__V_LSHRREV_B16 | |
| CInst_VOP3__V_ASHRREV_I16 | |
| CInst_VOP3__V_MAX_F16 | |
| CInst_VOP3__V_MIN_F16 | |
| CInst_VOP3__V_MAX_U16 | |
| CInst_VOP3__V_MAX_I16 | |
| CInst_VOP3__V_MIN_U16 | |
| CInst_VOP3__V_MIN_I16 | |
| CInst_VOP3__V_LDEXP_F16 | |
| CInst_VOP3__V_ADD_U32 | |
| CInst_VOP3__V_SUB_U32 | |
| CInst_VOP3__V_SUBREV_U32 | |
| CInst_VOP3__V_NOP | |
| CInst_VOP3__V_MOV_B32 | |
| CInst_VOP3__V_CVT_I32_F64 | |
| CInst_VOP3__V_CVT_F64_I32 | |
| CInst_VOP3__V_CVT_F32_I32 | |
| CInst_VOP3__V_CVT_F32_U32 | |
| CInst_VOP3__V_CVT_U32_F32 | |
| CInst_VOP3__V_CVT_I32_F32 | |
| CInst_VOP3__V_MOV_FED_B32 | |
| CInst_VOP3__V_CVT_F16_F32 | |
| CInst_VOP3__V_CVT_F32_F16 | |
| CInst_VOP3__V_CVT_RPI_I32_F32 | |
| CInst_VOP3__V_CVT_FLR_I32_F32 | |
| CInst_VOP3__V_CVT_OFF_F32_I4 | |
| CInst_VOP3__V_CVT_F32_F64 | |
| CInst_VOP3__V_CVT_F64_F32 | |
| CInst_VOP3__V_CVT_F32_UBYTE0 | |
| CInst_VOP3__V_CVT_F32_UBYTE1 | |
| CInst_VOP3__V_CVT_F32_UBYTE2 | |
| CInst_VOP3__V_CVT_F32_UBYTE3 | |
| CInst_VOP3__V_CVT_U32_F64 | |
| CInst_VOP3__V_CVT_F64_U32 | |
| CInst_VOP3__V_TRUNC_F64 | |
| CInst_VOP3__V_CEIL_F64 | |
| CInst_VOP3__V_RNDNE_F64 | |
| CInst_VOP3__V_FLOOR_F64 | |
| CInst_VOP3__V_FRACT_F32 | |
| CInst_VOP3__V_TRUNC_F32 | |
| CInst_VOP3__V_CEIL_F32 | |
| CInst_VOP3__V_RNDNE_F32 | |
| CInst_VOP3__V_FLOOR_F32 | |
| CInst_VOP3__V_EXP_F32 | |
| CInst_VOP3__V_LOG_F32 | |
| CInst_VOP3__V_RCP_F32 | |
| CInst_VOP3__V_RCP_IFLAG_F32 | |
| CInst_VOP3__V_RSQ_F32 | |
| CInst_VOP3__V_RCP_F64 | |
| CInst_VOP3__V_RSQ_F64 | |
| CInst_VOP3__V_SQRT_F32 | |
| CInst_VOP3__V_SQRT_F64 | |
| CInst_VOP3__V_SIN_F32 | |
| CInst_VOP3__V_COS_F32 | |
| CInst_VOP3__V_NOT_B32 | |
| CInst_VOP3__V_BFREV_B32 | |
| CInst_VOP3__V_FFBH_U32 | |
| CInst_VOP3__V_FFBL_B32 | |
| CInst_VOP3__V_FFBH_I32 | |
| CInst_VOP3__V_FREXP_EXP_I32_F64 | |
| CInst_VOP3__V_FREXP_MANT_F64 | |
| CInst_VOP3__V_FRACT_F64 | |
| CInst_VOP3__V_FREXP_EXP_I32_F32 | |
| CInst_VOP3__V_FREXP_MANT_F32 | |
| CInst_VOP3__V_CLREXCP | |
| CInst_VOP3__V_CVT_F16_U16 | |
| CInst_VOP3__V_CVT_F16_I16 | |
| CInst_VOP3__V_CVT_U16_F16 | |
| CInst_VOP3__V_CVT_I16_F16 | |
| CInst_VOP3__V_RCP_F16 | |
| CInst_VOP3__V_SQRT_F16 | |
| CInst_VOP3__V_RSQ_F16 | |
| CInst_VOP3__V_LOG_F16 | |
| CInst_VOP3__V_EXP_F16 | |
| CInst_VOP3__V_FREXP_MANT_F16 | |
| CInst_VOP3__V_FREXP_EXP_I16_F16 | |
| CInst_VOP3__V_FLOOR_F16 | |
| CInst_VOP3__V_CEIL_F16 | |
| CInst_VOP3__V_TRUNC_F16 | |
| CInst_VOP3__V_RNDNE_F16 | |
| CInst_VOP3__V_FRACT_F16 | |
| CInst_VOP3__V_SIN_F16 | |
| CInst_VOP3__V_COS_F16 | |
| CInst_VOP3__V_EXP_LEGACY_F32 | |
| CInst_VOP3__V_LOG_LEGACY_F32 | |
| CInst_VOP3__V_MAD_LEGACY_F32 | |
| CInst_VOP3__V_MAD_F32 | |
| CInst_VOP3__V_MAD_I32_I24 | |
| CInst_VOP3__V_MAD_U32_U24 | |
| CInst_VOP3__V_CUBEID_F32 | |
| CInst_VOP3__V_CUBESC_F32 | |
| CInst_VOP3__V_CUBETC_F32 | |
| CInst_VOP3__V_CUBEMA_F32 | |
| CInst_VOP3__V_BFE_U32 | |
| CInst_VOP3__V_BFE_I32 | |
| CInst_VOP3__V_BFI_B32 | |
| CInst_VOP3__V_FMA_F32 | |
| CInst_VOP3__V_FMA_F64 | |
| CInst_VOP3__V_LERP_U8 | |
| CInst_VOP3__V_ALIGNBIT_B32 | |
| CInst_VOP3__V_ALIGNBYTE_B32 | |
| CInst_VOP3__V_MIN3_F32 | |
| CInst_VOP3__V_MIN3_I32 | |
| CInst_VOP3__V_MIN3_U32 | |
| CInst_VOP3__V_MAX3_F32 | |
| CInst_VOP3__V_MAX3_I32 | |
| CInst_VOP3__V_MAX3_U32 | |
| CInst_VOP3__V_MED3_F32 | |
| CInst_VOP3__V_MED3_I32 | |
| CInst_VOP3__V_MED3_U32 | |
| CInst_VOP3__V_SAD_U8 | |
| CInst_VOP3__V_SAD_HI_U8 | |
| CInst_VOP3__V_SAD_U16 | |
| CInst_VOP3__V_SAD_U32 | |
| CInst_VOP3__V_CVT_PK_U8_F32 | |
| CInst_VOP3__V_DIV_FIXUP_F32 | |
| CInst_VOP3__V_DIV_FIXUP_F64 | |
| CInst_VOP3__V_DIV_SCALE_F32 | |
| CInst_VOP3__V_DIV_SCALE_F64 | |
| CInst_VOP3__V_DIV_FMAS_F32 | |
| CInst_VOP3__V_DIV_FMAS_F64 | |
| CInst_VOP3__V_MSAD_U8 | |
| CInst_VOP3__V_QSAD_PK_U16_U8 | |
| CInst_VOP3__V_MQSAD_PK_U16_U8 | |
| CInst_VOP3__V_MQSAD_U32_U8 | |
| CInst_VOP3__V_MAD_U64_U32 | |
| CInst_VOP3__V_MAD_I64_I32 | |
| CInst_VOP3__V_XAD_U32 | |
| CInst_VOP3__V_LSHL_ADD_U32 | |
| CInst_VOP3__V_ADD_LSHL_U32 | |
| CInst_VOP3__V_ADD3_U32 | |
| CInst_VOP3__V_LSHL_OR_B32 | |
| CInst_VOP3__V_AND_OR_B32 | |
| CInst_VOP3__V_MAD_F16 | |
| CInst_VOP3__V_MAD_U16 | |
| CInst_VOP3__V_MAD_I16 | |
| CInst_VOP3__V_PERM_B32 | |
| CInst_VOP3__V_FMA_F16 | |
| CInst_VOP3__V_DIV_FIXUP_F16 | |
| CInst_VOP3__V_CVT_PKACCUM_U8_F32 | |
| CInst_VOP3__V_INTERP_P1_F32 | |
| CInst_VOP3__V_INTERP_P2_F32 | |
| CInst_VOP3__V_INTERP_MOV_F32 | |
| CInst_VOP3__V_INTERP_P1LL_F16 | |
| CInst_VOP3__V_INTERP_P1LV_F16 | |
| CInst_VOP3__V_INTERP_P2_F16 | |
| CInst_VOP3__V_ADD_F64 | |
| CInst_VOP3__V_MUL_F64 | |
| CInst_VOP3__V_MIN_F64 | |
| CInst_VOP3__V_MAX_F64 | |
| CInst_VOP3__V_LDEXP_F64 | |
| CInst_VOP3__V_MUL_LO_U32 | |
| CInst_VOP3__V_MUL_HI_U32 | |
| CInst_VOP3__V_MUL_HI_I32 | |
| CInst_VOP3__V_LDEXP_F32 | |
| CInst_VOP3__V_READLANE_B32 | |
| CInst_VOP3__V_WRITELANE_B32 | |
| CInst_VOP3__V_BCNT_U32_B32 | |
| CInst_VOP3__V_MBCNT_LO_U32_B32 | |
| CInst_VOP3__V_MBCNT_HI_U32_B32 | |
| CInst_VOP3__V_LSHLREV_B64 | |
| CInst_VOP3__V_LSHRREV_B64 | |
| CInst_VOP3__V_ASHRREV_I64 | |
| CInst_VOP3__V_TRIG_PREOP_F64 | |
| CInst_VOP3__V_BFM_B32 | |
| CInst_VOP3__V_CVT_PKNORM_I16_F32 | |
| CInst_VOP3__V_CVT_PKNORM_U16_F32 | |
| CInst_VOP3__V_CVT_PKRTZ_F16_F32 | |
| CInst_VOP3__V_CVT_PK_U16_U32 | |
| CInst_VOP3__V_CVT_PK_I16_I32 | |
| CInst_DS__DS_ADD_U32 | |
| CInst_DS__DS_SUB_U32 | |
| CInst_DS__DS_RSUB_U32 | |
| CInst_DS__DS_INC_U32 | |
| CInst_DS__DS_DEC_U32 | |
| CInst_DS__DS_MIN_I32 | |
| CInst_DS__DS_MAX_I32 | |
| CInst_DS__DS_MIN_U32 | |
| CInst_DS__DS_MAX_U32 | |
| CInst_DS__DS_AND_B32 | |
| CInst_DS__DS_OR_B32 | |
| CInst_DS__DS_XOR_B32 | |
| CInst_DS__DS_MSKOR_B32 | |
| CInst_DS__DS_WRITE_B32 | |
| CInst_DS__DS_WRITE2_B32 | |
| CInst_DS__DS_WRITE2ST64_B32 | |
| CInst_DS__DS_CMPST_B32 | |
| CInst_DS__DS_CMPST_F32 | |
| CInst_DS__DS_MIN_F32 | |
| CInst_DS__DS_MAX_F32 | |
| CInst_DS__DS_NOP | |
| CInst_DS__DS_ADD_F32 | |
| CInst_DS__DS_WRITE_B8 | |
| CInst_DS__DS_WRITE_B16 | |
| CInst_DS__DS_ADD_RTN_U32 | |
| CInst_DS__DS_SUB_RTN_U32 | |
| CInst_DS__DS_RSUB_RTN_U32 | |
| CInst_DS__DS_INC_RTN_U32 | |
| CInst_DS__DS_DEC_RTN_U32 | |
| CInst_DS__DS_MIN_RTN_I32 | |
| CInst_DS__DS_MAX_RTN_I32 | |
| CInst_DS__DS_MIN_RTN_U32 | |
| CInst_DS__DS_MAX_RTN_U32 | |
| CInst_DS__DS_AND_RTN_B32 | |
| CInst_DS__DS_OR_RTN_B32 | |
| CInst_DS__DS_XOR_RTN_B32 | |
| CInst_DS__DS_MSKOR_RTN_B32 | |
| CInst_DS__DS_WRXCHG_RTN_B32 | |
| CInst_DS__DS_WRXCHG2_RTN_B32 | |
| CInst_DS__DS_WRXCHG2ST64_RTN_B32 | |
| CInst_DS__DS_CMPST_RTN_B32 | |
| CInst_DS__DS_CMPST_RTN_F32 | |
| CInst_DS__DS_MIN_RTN_F32 | |
| CInst_DS__DS_MAX_RTN_F32 | |
| CInst_DS__DS_WRAP_RTN_B32 | |
| CInst_DS__DS_ADD_RTN_F32 | |
| CInst_DS__DS_READ_B32 | |
| CInst_DS__DS_READ2_B32 | |
| CInst_DS__DS_READ2ST64_B32 | |
| CInst_DS__DS_READ_I8 | |
| CInst_DS__DS_READ_U8 | |
| CInst_DS__DS_READ_I16 | |
| CInst_DS__DS_READ_U16 | |
| CInst_DS__DS_SWIZZLE_B32 | |
| CInst_DS__DS_PERMUTE_B32 | |
| CInst_DS__DS_BPERMUTE_B32 | |
| CInst_DS__DS_ADD_U64 | |
| CInst_DS__DS_SUB_U64 | |
| CInst_DS__DS_RSUB_U64 | |
| CInst_DS__DS_INC_U64 | |
| CInst_DS__DS_DEC_U64 | |
| CInst_DS__DS_MIN_I64 | |
| CInst_DS__DS_MAX_I64 | |
| CInst_DS__DS_MIN_U64 | |
| CInst_DS__DS_MAX_U64 | |
| CInst_DS__DS_AND_B64 | |
| CInst_DS__DS_OR_B64 | |
| CInst_DS__DS_XOR_B64 | |
| CInst_DS__DS_MSKOR_B64 | |
| CInst_DS__DS_WRITE_B64 | |
| CInst_DS__DS_WRITE2_B64 | |
| CInst_DS__DS_WRITE2ST64_B64 | |
| CInst_DS__DS_CMPST_B64 | |
| CInst_DS__DS_CMPST_F64 | |
| CInst_DS__DS_MIN_F64 | |
| CInst_DS__DS_MAX_F64 | |
| CInst_DS__DS_ADD_RTN_U64 | |
| CInst_DS__DS_SUB_RTN_U64 | |
| CInst_DS__DS_RSUB_RTN_U64 | |
| CInst_DS__DS_INC_RTN_U64 | |
| CInst_DS__DS_DEC_RTN_U64 | |
| CInst_DS__DS_MIN_RTN_I64 | |
| CInst_DS__DS_MAX_RTN_I64 | |
| CInst_DS__DS_MIN_RTN_U64 | |
| CInst_DS__DS_MAX_RTN_U64 | |
| CInst_DS__DS_AND_RTN_B64 | |
| CInst_DS__DS_OR_RTN_B64 | |
| CInst_DS__DS_XOR_RTN_B64 | |
| CInst_DS__DS_MSKOR_RTN_B64 | |
| CInst_DS__DS_WRXCHG_RTN_B64 | |
| CInst_DS__DS_WRXCHG2_RTN_B64 | |
| CInst_DS__DS_WRXCHG2ST64_RTN_B64 | |
| CInst_DS__DS_CMPST_RTN_B64 | |
| CInst_DS__DS_CMPST_RTN_F64 | |
| CInst_DS__DS_MIN_RTN_F64 | |
| CInst_DS__DS_MAX_RTN_F64 | |
| CInst_DS__DS_READ_B64 | |
| CInst_DS__DS_READ2_B64 | |
| CInst_DS__DS_READ2ST64_B64 | |
| CInst_DS__DS_CONDXCHG32_RTN_B64 | |
| CInst_DS__DS_ADD_SRC2_U32 | |
| CInst_DS__DS_SUB_SRC2_U32 | |
| CInst_DS__DS_RSUB_SRC2_U32 | |
| CInst_DS__DS_INC_SRC2_U32 | |
| CInst_DS__DS_DEC_SRC2_U32 | |
| CInst_DS__DS_MIN_SRC2_I32 | |
| CInst_DS__DS_MAX_SRC2_I32 | |
| CInst_DS__DS_MIN_SRC2_U32 | |
| CInst_DS__DS_MAX_SRC2_U32 | |
| CInst_DS__DS_AND_SRC2_B32 | |
| CInst_DS__DS_OR_SRC2_B32 | |
| CInst_DS__DS_XOR_SRC2_B32 | |
| CInst_DS__DS_WRITE_SRC2_B32 | |
| CInst_DS__DS_MIN_SRC2_F32 | |
| CInst_DS__DS_MAX_SRC2_F32 | |
| CInst_DS__DS_ADD_SRC2_F32 | |
| CInst_DS__DS_GWS_SEMA_RELEASE_ALL | |
| CInst_DS__DS_GWS_INIT | |
| CInst_DS__DS_GWS_SEMA_V | |
| CInst_DS__DS_GWS_SEMA_BR | |
| CInst_DS__DS_GWS_SEMA_P | |
| CInst_DS__DS_GWS_BARRIER | |
| CInst_DS__DS_CONSUME | |
| CInst_DS__DS_APPEND | |
| CInst_DS__DS_ORDERED_COUNT | |
| CInst_DS__DS_ADD_SRC2_U64 | |
| CInst_DS__DS_SUB_SRC2_U64 | |
| CInst_DS__DS_RSUB_SRC2_U64 | |
| CInst_DS__DS_INC_SRC2_U64 | |
| CInst_DS__DS_DEC_SRC2_U64 | |
| CInst_DS__DS_MIN_SRC2_I64 | |
| CInst_DS__DS_MAX_SRC2_I64 | |
| CInst_DS__DS_MIN_SRC2_U64 | |
| CInst_DS__DS_MAX_SRC2_U64 | |
| CInst_DS__DS_AND_SRC2_B64 | |
| CInst_DS__DS_OR_SRC2_B64 | |
| CInst_DS__DS_XOR_SRC2_B64 | |
| CInst_DS__DS_WRITE_SRC2_B64 | |
| CInst_DS__DS_MIN_SRC2_F64 | |
| CInst_DS__DS_MAX_SRC2_F64 | |
| CInst_DS__DS_WRITE_B96 | |
| CInst_DS__DS_WRITE_B128 | |
| CInst_DS__DS_READ_B96 | |
| CInst_DS__DS_READ_B128 | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_X | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_XY | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_XYZ | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_XYZW | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_X | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_XY | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_XYZ | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_XYZW | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_X | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ | |
| CInst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_X | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_XY | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ | |
| CInst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW | |
| CInst_MUBUF__BUFFER_LOAD_UBYTE | |
| CInst_MUBUF__BUFFER_LOAD_SBYTE | |
| CInst_MUBUF__BUFFER_LOAD_USHORT | |
| CInst_MUBUF__BUFFER_LOAD_SSHORT | |
| CInst_MUBUF__BUFFER_LOAD_DWORD | |
| CInst_MUBUF__BUFFER_LOAD_DWORDX2 | |
| CInst_MUBUF__BUFFER_LOAD_DWORDX3 | |
| CInst_MUBUF__BUFFER_LOAD_DWORDX4 | |
| CInst_MUBUF__BUFFER_STORE_BYTE | |
| CInst_MUBUF__BUFFER_STORE_SHORT | |
| CInst_MUBUF__BUFFER_STORE_DWORD | |
| CInst_MUBUF__BUFFER_STORE_DWORDX2 | |
| CInst_MUBUF__BUFFER_STORE_DWORDX3 | |
| CInst_MUBUF__BUFFER_STORE_DWORDX4 | |
| CInst_MUBUF__BUFFER_STORE_LDS_DWORD | |
| CInst_MUBUF__BUFFER_WBINVL1 | |
| CInst_MUBUF__BUFFER_WBINVL1_VOL | |
| CInst_MUBUF__BUFFER_ATOMIC_SWAP | |
| CInst_MUBUF__BUFFER_ATOMIC_CMPSWAP | |
| CInst_MUBUF__BUFFER_ATOMIC_ADD | |
| CInst_MUBUF__BUFFER_ATOMIC_SUB | |
| CInst_MUBUF__BUFFER_ATOMIC_SMIN | |
| CInst_MUBUF__BUFFER_ATOMIC_UMIN | |
| CInst_MUBUF__BUFFER_ATOMIC_SMAX | |
| CInst_MUBUF__BUFFER_ATOMIC_UMAX | |
| CInst_MUBUF__BUFFER_ATOMIC_AND | |
| CInst_MUBUF__BUFFER_ATOMIC_OR | |
| CInst_MUBUF__BUFFER_ATOMIC_XOR | |
| CInst_MUBUF__BUFFER_ATOMIC_INC | |
| CInst_MUBUF__BUFFER_ATOMIC_DEC | |
| CInst_MUBUF__BUFFER_ATOMIC_SWAP_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_ADD_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_SUB_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_SMIN_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_UMIN_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_SMAX_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_UMAX_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_AND_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_OR_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_XOR_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_INC_X2 | |
| CInst_MUBUF__BUFFER_ATOMIC_DEC_X2 | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_X | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_XY | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_X | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_XY | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_XYZ | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_XYZW | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ | |
| CInst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_X | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ | |
| CInst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW | |
| CInst_MIMG__IMAGE_LOAD | |
| CInst_MIMG__IMAGE_LOAD_MIP | |
| CInst_MIMG__IMAGE_LOAD_PCK | |
| CInst_MIMG__IMAGE_LOAD_PCK_SGN | |
| CInst_MIMG__IMAGE_LOAD_MIP_PCK | |
| CInst_MIMG__IMAGE_LOAD_MIP_PCK_SGN | |
| CInst_MIMG__IMAGE_STORE | |
| CInst_MIMG__IMAGE_STORE_MIP | |
| CInst_MIMG__IMAGE_STORE_PCK | |
| CInst_MIMG__IMAGE_STORE_MIP_PCK | |
| CInst_MIMG__IMAGE_GET_RESINFO | |
| CInst_MIMG__IMAGE_ATOMIC_SWAP | |
| CInst_MIMG__IMAGE_ATOMIC_CMPSWAP | |
| CInst_MIMG__IMAGE_ATOMIC_ADD | |
| CInst_MIMG__IMAGE_ATOMIC_SUB | |
| CInst_MIMG__IMAGE_ATOMIC_SMIN | |
| CInst_MIMG__IMAGE_ATOMIC_UMIN | |
| CInst_MIMG__IMAGE_ATOMIC_SMAX | |
| CInst_MIMG__IMAGE_ATOMIC_UMAX | |
| CInst_MIMG__IMAGE_ATOMIC_AND | |
| CInst_MIMG__IMAGE_ATOMIC_OR | |
| CInst_MIMG__IMAGE_ATOMIC_XOR | |
| CInst_MIMG__IMAGE_ATOMIC_INC | |
| CInst_MIMG__IMAGE_ATOMIC_DEC | |
| CInst_MIMG__IMAGE_SAMPLE | |
| CInst_MIMG__IMAGE_SAMPLE_CL | |
| CInst_MIMG__IMAGE_SAMPLE_D | |
| CInst_MIMG__IMAGE_SAMPLE_D_CL | |
| CInst_MIMG__IMAGE_SAMPLE_L | |
| CInst_MIMG__IMAGE_SAMPLE_B | |
| CInst_MIMG__IMAGE_SAMPLE_B_CL | |
| CInst_MIMG__IMAGE_SAMPLE_LZ | |
| CInst_MIMG__IMAGE_SAMPLE_C | |
| CInst_MIMG__IMAGE_SAMPLE_C_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_D | |
| CInst_MIMG__IMAGE_SAMPLE_C_D_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_L | |
| CInst_MIMG__IMAGE_SAMPLE_C_B | |
| CInst_MIMG__IMAGE_SAMPLE_C_B_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_LZ | |
| CInst_MIMG__IMAGE_SAMPLE_O | |
| CInst_MIMG__IMAGE_SAMPLE_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_D_O | |
| CInst_MIMG__IMAGE_SAMPLE_D_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_L_O | |
| CInst_MIMG__IMAGE_SAMPLE_B_O | |
| CInst_MIMG__IMAGE_SAMPLE_B_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_LZ_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_D_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_D_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_L_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_B_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_B_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_LZ_O | |
| CInst_MIMG__IMAGE_GATHER4 | |
| CInst_MIMG__IMAGE_GATHER4_CL | |
| CInst_MIMG__IMAGE_GATHER4_L | |
| CInst_MIMG__IMAGE_GATHER4_B | |
| CInst_MIMG__IMAGE_GATHER4_B_CL | |
| CInst_MIMG__IMAGE_GATHER4_LZ | |
| CInst_MIMG__IMAGE_GATHER4_C | |
| CInst_MIMG__IMAGE_GATHER4_C_CL | |
| CInst_MIMG__IMAGE_GATHER4_C_L | |
| CInst_MIMG__IMAGE_GATHER4_C_B | |
| CInst_MIMG__IMAGE_GATHER4_C_B_CL | |
| CInst_MIMG__IMAGE_GATHER4_C_LZ | |
| CInst_MIMG__IMAGE_GATHER4_O | |
| CInst_MIMG__IMAGE_GATHER4_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_L_O | |
| CInst_MIMG__IMAGE_GATHER4_B_O | |
| CInst_MIMG__IMAGE_GATHER4_B_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_LZ_O | |
| CInst_MIMG__IMAGE_GATHER4_C_O | |
| CInst_MIMG__IMAGE_GATHER4_C_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_C_L_O | |
| CInst_MIMG__IMAGE_GATHER4_C_B_O | |
| CInst_MIMG__IMAGE_GATHER4_C_B_CL_O | |
| CInst_MIMG__IMAGE_GATHER4_C_LZ_O | |
| CInst_MIMG__IMAGE_GET_LOD | |
| CInst_MIMG__IMAGE_SAMPLE_CD | |
| CInst_MIMG__IMAGE_SAMPLE_CD_CL | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD_CL | |
| CInst_MIMG__IMAGE_SAMPLE_CD_O | |
| CInst_MIMG__IMAGE_SAMPLE_CD_CL_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD_O | |
| CInst_MIMG__IMAGE_SAMPLE_C_CD_CL_O | |
| CInst_EXP__EXP | |
| CInst_FLAT__FLAT_LOAD_UBYTE | |
| CInst_FLAT__FLAT_LOAD_SBYTE | |
| CInst_FLAT__FLAT_LOAD_USHORT | |
| CInst_FLAT__FLAT_LOAD_SSHORT | |
| CInst_FLAT__FLAT_LOAD_DWORD | |
| CInst_FLAT__FLAT_LOAD_DWORDX2 | |
| CInst_FLAT__FLAT_LOAD_DWORDX3 | |
| CInst_FLAT__FLAT_LOAD_DWORDX4 | |
| CInst_FLAT__FLAT_STORE_BYTE | |
| CInst_FLAT__FLAT_STORE_SHORT | |
| CInst_FLAT__FLAT_STORE_DWORD | |
| CInst_FLAT__FLAT_STORE_DWORDX2 | |
| CInst_FLAT__FLAT_STORE_DWORDX3 | |
| CInst_FLAT__FLAT_STORE_DWORDX4 | |
| CInst_FLAT__FLAT_ATOMIC_SWAP | |
| CInst_FLAT__FLAT_ATOMIC_CMPSWAP | |
| CInst_FLAT__FLAT_ATOMIC_ADD | |
| CInst_FLAT__FLAT_ATOMIC_SUB | |
| CInst_FLAT__FLAT_ATOMIC_SMIN | |
| CInst_FLAT__FLAT_ATOMIC_UMIN | |
| CInst_FLAT__FLAT_ATOMIC_SMAX | |
| CInst_FLAT__FLAT_ATOMIC_UMAX | |
| CInst_FLAT__FLAT_ATOMIC_AND | |
| CInst_FLAT__FLAT_ATOMIC_OR | |
| CInst_FLAT__FLAT_ATOMIC_XOR | |
| CInst_FLAT__FLAT_ATOMIC_INC | |
| CInst_FLAT__FLAT_ATOMIC_DEC | |
| CInst_FLAT__FLAT_ATOMIC_SWAP_X2 | |
| CInst_FLAT__FLAT_ATOMIC_CMPSWAP_X2 | |
| CInst_FLAT__FLAT_ATOMIC_ADD_X2 | |
| CInst_FLAT__FLAT_ATOMIC_SUB_X2 | |
| CInst_FLAT__FLAT_ATOMIC_SMIN_X2 | |
| CInst_FLAT__FLAT_ATOMIC_UMIN_X2 | |
| CInst_FLAT__FLAT_ATOMIC_SMAX_X2 | |
| CInst_FLAT__FLAT_ATOMIC_UMAX_X2 | |
| CInst_FLAT__FLAT_ATOMIC_AND_X2 | |
| CInst_FLAT__FLAT_ATOMIC_OR_X2 | |
| CInst_FLAT__FLAT_ATOMIC_XOR_X2 | |
| CInst_FLAT__FLAT_ATOMIC_INC_X2 | |
| CInst_FLAT__FLAT_ATOMIC_DEC_X2 | |
| CBufferRsrcDescriptor | |
| CInst_SOP2 | |
| CInst_SOPK | |
| CInst_SOP1 | |
| CInst_SOPC | |
| CInst_SOPP | |
| CInst_SMEM | |
| CInst_VOP2 | |
| CInst_VOP1 | |
| CInst_VOPC | |
| CInst_VINTRP | |
| CInst_VOP3A | |
| CInst_VOP3B | |
| CInst_DS | |
| CInst_MUBUF | |
| CInst_MTBUF | |
| CInst_MIMG | |
| CInst_EXP | |
| CInst_FLAT | |
| COpTraits | Convenience traits so we can automatically infer the correct FP type without looking at the number of dwords (i.e., to determine if we need a float or a double when creating FP constants) |
| COpTraits< ScalarRegF64 > | |
| COpTraits< ScalarRegU64 > | |
| COperand | |
| CScalarOperand | |
| CVecOperand | |
| ►CWalker | |
| CWalkerPort | |
| CWalkerSenderState | |
| CWalkerState | |
| ►CGpuTLB | |
| CCpuSidePort | |
| CMemSidePort | MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will not be connected |
| CTLBEvent | |
| CTranslation | |
| CVegaTLBStats | |
| ►NX86ISA | This is exposed globally, independent of the ISA |
| ►NACPI | |
| ►NMADT | |
| ►CRecord | |
| CMem | |
| ►CLAPIC | |
| CMem | |
| ►CIOAPIC | |
| CMem | |
| ►CIntSourceOverride | |
| CMem | |
| ►CNMI | |
| CMem | |
| ►CLAPICOverride | |
| CMem | |
| ►CMADT | |
| CMem | |
| CAllocator | |
| CLinearAllocator | |
| ►CRSDP | |
| CMem | |
| CMemR0 | |
| ►CSysDescTable | |
| CMem | |
| CRXSDT | |
| CRSDT | |
| CXSDT | |
| ►Nintelmp | |
| CFloatingPointer | |
| CBaseConfigEntry | |
| CExtConfigEntry | |
| CConfigTable | |
| CProcessor | |
| CBus | |
| CIOAPIC | |
| CIntAssignment | |
| CIOIntAssignment | |
| CLocalIntAssignment | |
| CAddrSpaceMapping | |
| CBusHierarchy | |
| CCompatAddrSpaceMod | |
| ►Nsmbios | |
| CSMBiosStructure | |
| CBiosInformation | |
| ►CSMBiosTable | |
| ►CSMBiosHeader | |
| CIntermediateHeader | |
| ►CGpuTLB | |
| CAccessInfo | This hash map will use the virtual page address as a key and will keep track of total number of accesses per page |
| CCpuSidePort | |
| CGpuTLBStats | |
| CMemSidePort | MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will not be connected |
| CTLBEvent | |
| CTranslation | |
| CBareMetalWorkload | |
| CE820Entry | |
| CE820Table | |
| CCpuidResult | |
| ►CDecoder | |
| CInstBytes | |
| CEmulEnv | |
| CX86FaultBase | |
| CX86Fault | |
| CX86Trap | |
| CX86Abort | |
| CX86Interrupt | |
| CUnimpInstFault | |
| CDivideError | |
| CDebugException | |
| CNonMaskableInterrupt | |
| CBreakpoint | |
| COverflowTrap | |
| CBoundRange | |
| CInvalidOpcode | |
| CDeviceNotAvailable | |
| CDoubleFault | |
| CInvalidTSS | |
| CSegmentNotPresent | |
| CStackFault | |
| CGeneralProtection | |
| CPageFault | |
| CX87FpExceptionPending | |
| CAlignmentCheck | |
| CMachineCheck | |
| CSIMDFloatingPointFault | |
| CSecurityException | |
| CExternalInterrupt | |
| CSystemManagementInterrupt | |
| CInitInterrupt | |
| CStartupInterrupt | |
| CFsWorkload | |
| CDecodeFaultInst | |
| CMacroopBase | |
| CMicroDebug | |
| CFpOp | |
| CMemOp | Base class for memory ops |
| CLdStOp | Base class for load ops using one integer register |
| CLdStFpOp | Base class for load ops using one FP register |
| CMemNoDataOp | Base class for the tia microop which has no destination register |
| CLdStSplitOp | Base class for load and store ops using two registers, we will call them split ops for this reason |
| CMediaOpBase | |
| CX86MicroopBase | |
| CMicroCondBase | |
| CDestOp | |
| CSrc1Op | |
| CSrc2Op | |
| CDataOp | |
| CDataHiOp | |
| CDataLowOp | |
| CHasDataSize | |
| CHasDataSize< T, decltype((void)&T::dataSize)> | |
| CIntOp | |
| CFoldedOp | |
| CCrOp | |
| CDbgOp | |
| CSegOp | |
| CMiscOp | |
| CFloatOp | |
| CImm8Op | |
| CImm64Op | |
| CUpcOp | |
| CFaultOp | |
| ►CAddrOp | |
| CArgType | |
| CInstOperands | |
| CRegOpBase | |
| CMicroHalt | |
| CGpRegIndex | Classes for register indices passed to instruction constructors |
| CFpRegIndex | |
| CCtrlRegIndex | |
| CCrRegIndex | |
| CDbgRegIndex | |
| CSegRegIndex | |
| CX86StaticInst | Base class for all X86 static instructions |
| CInterrupts | |
| CISA | |
| CFsLinux | |
| ►CEmuLinux | |
| CSyscallABI32 | |
| CSyscallABI64 | |
| CMMU | |
| CTlbEntry | |
| CLongModePTE | |
| ►CWalker | |
| CWalkerPort | |
| CWalkerSenderState | |
| CWalkerState | |
| CPCState | |
| CX86Process | |
| ►CX86_64Process | |
| CVSyscallPage | |
| ►CI386Process | |
| CVSyscallPage | |
| CFlatFloatRegClassOps | |
| CFloatRegClassOps | |
| CFlatIntRegClassOps | |
| CIntRegClassOps | |
| CSegDescriptorLimit | |
| ►CRemoteGDB | |
| ►CAMD64GdbRegCache | |
| CGEM5_PACKED | |
| CX86GdbRegCache | |
| CStackTrace | |
| ►CTLB | |
| CTlbStats | |
| CExtMachInst | |
| ►CCmos | |
| CX86RTC | |
| CI8042 | |
| CI82094AA | |
| ►CI8237 | |
| ►CChannel | |
| CChannelAddrReg | |
| CChannelRemainingReg | |
| CWriteOnlyReg | |
| ►CI8254 | |
| CX86Intel8254Timer | |
| CI8259 | |
| CIntResponsePort | |
| ►CIntRequestPort | |
| COnCompletion | |
| CSpeaker | |
| ►NX86ISAInst | |
| CMicrocodeRom | |
| CGpuTranslationState | GPU TranslationState: this currently is a somewhat bastardization of the usage of SenderState, whereby the receiver of a packet is not usually supposed to need to look at the contents of the senderState, you're really only supposed to look at what you pushed on, pop it off, and send it back |
| ►CTLBCoalescer | The TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of each TLB |
| CCpuSidePort | |
| CMemSidePort | |
| CTLBCoalescerStats | |
| ►CVegaTLBCoalescer | The VegaTLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of each TLB |
| CCpuSidePort | |
| CMemSidePort | |
| ►CAapcs32 | |
| CState | |
| ►CAapcs32Vfp | |
| CState | |
| ►CAapcs64 | |
| CState | |
| CClockRateControlDummyProtocolType | |
| CClockRateControlFwIf | |
| CClockRateControlBwIf | |
| CClockRateControlSlaveBase | |
| CClockRateControlInitiatorSocket | |
| CClockRateControlTargetSocket | |
| CSignalInterruptDummyProtocolType | |
| CSignalInterruptFwIf | |
| CSignalInterruptBwIf | |
| CSignalInterruptSlaveBase | |
| CSignalInterruptInitiatorSocket | |
| CSignalInterruptTargetSocket | |
| CArmFreebsd | |
| ►CArmFreebsd32 | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | For getrusage() |
| Ctgt_iovec | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctimeval | For gettimeofday() |
| Ctms | For times() |
| ►CArmFreebsd64 | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | For getrusage() |
| Ctgt_iovec | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctimeval | For gettimeofday() |
| Ctms | For times() |
| CMrsOp | |
| CMsrBase | |
| CMsrImmOp | |
| CMsrRegOp | |
| CMrrcOp | |
| CMcrrOp | |
| CImmOp | |
| CRegImmOp | |
| CRegRegOp | |
| CRegOp | |
| CRegImmRegOp | |
| CRegRegRegImmOp | |
| CRegRegRegRegOp | |
| CRegRegRegOp | |
| CRegRegImmOp | |
| CMiscRegRegImmOp | |
| CRegMiscRegImmOp | |
| CRegImmImmOp | |
| CRegRegImmImmOp | |
| CRegImmRegShiftOp | |
| CUnknownOp | |
| CMcrMrcMiscInst | Certain mrc/mcr instructions act as nops or flush the pipe based on what register the instruction is trying to access |
| CMcrMrcImplDefined | This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc behaviour is trappable even for unimplemented registers |
| CTlbiOp | |
| CImmOp64 | |
| CRegRegImmImmOp64 | |
| CRegRegRegImmOp64 | |
| CUnknownOp64 | |
| CMiscRegOp64 | This class is implementing the Base class for a generic AArch64 instruction which is making use of system registers (MiscReg), like MSR,MRS,SYS |
| CMiscRegImmOp64 | |
| CMiscRegRegImmOp64 | |
| CRegMiscRegImmOp64 | |
| CMiscRegImplDefined64 | |
| CRegNone | |
| CTlbiOp64 | |
| CDecoderFaultInst | |
| CFailUnimplemented | Static instruction class for unimplemented instructions that cause simulator termination |
| CWarnUnimplemented | Base class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation) |
| CIllegalExecInst | This class is modelling instructions which are not going to be executed since they are flagged as Illegal Execution Instructions (PSTATE.IL = 1 or CPSR.IL = 1) |
| CDebugStep | |
| ►CArmKvmCPU | ARM implementation of a KVM-based hardware virtualized CPU |
| CKvmCoreMiscRegInfo | |
| CKvmIntRegInfo | |
| CKvmFPReg | |
| ►CArmV8KvmCPU | This is an implementation of a KVM-based ARMv8-compatible CPU |
| CIntRegInfo | Mapping between integer registers in gem5 and KVM |
| CMiscRegInfo | Mapping between misc registers in gem5 and registers in KVM |
| CBaseArmKvmCPU | |
| CKvmKernelGic | KVM in-kernel GIC abstraction |
| CKvmKernelGicV2 | |
| CKvmKernelGicV3 | |
| CGicV2Types | |
| CGicV3Types | |
| CMuxingKvmGic | |
| CAtagHeader | |
| CAtagCore | |
| CAtagMem | |
| CAtagRev | |
| CAtagSerial | |
| CAtagCmdline | |
| CAtagNone | |
| CArmLinux | |
| ►CArmLinux32 | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | For getrusage() |
| Ctgt_iovec | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctgt_sysinfo | |
| Ctimespec | |
| Ctimeval | For gettimeofday() |
| Ctms | For times() |
| ►CArmLinux64 | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | For getrusage() |
| Ctgt_iovec | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctgt_sysinfo | |
| Ctimespec | |
| Ctimeval | For gettimeofday() |
| Ctms | For times() |
| CArmLinuxProcess32 | A process with emulated Arm/Linux syscalls |
| CArmLinuxProcess64 | A process with emulated Arm/Linux syscalls |
| CArmProcess | |
| CArmProcess32 | |
| CArmProcess64 | |
| ►CSemiPseudoAbi32 | |
| CState | |
| ►CSemiPseudoAbi64 | |
| CState | |
| ►CArmSemihosting | Semihosting for AArch32 and AArch64 |
| ►CAbi32 | |
| CState | |
| ►CAbi64 | |
| CState | |
| ►CAbiBase | |
| CStateBase | |
| CFile | |
| CFileBase | Internal state for open files |
| CFileFeatures | Implementation of the ':semihosting-features' magic file |
| CInPlaceArg | |
| CSemiCall | Semihosting call information structure |
| CArmRelease | |
| CArmSystem | |
| CInstDecoder | |
| CBaseHTMCheckpoint | Transactional Memory checkpoint |
| CBaseInterrupts | |
| CBaseISA | |
| ►CBaseMMU | |
| CMMUTranslationGen | |
| CTranslation | |
| CPCStateBase | |
| CBaseTLB | |
| CVecPredRegContainer | Generic predicate register container |
| CVecPredRegT | Predicate register view |
| CParseParam< VecPredRegContainer< NumBits, Packed > > | |
| CShowParam< VecPredRegContainer< NumBits, Packed > > | |
| CDummyVecPredRegContainer | Dummy type aliases and constants for architectures that do not implement vector predicate registers |
| CParseParam< DummyVecPredRegContainer > | |
| CVecRegContainer | Vector Register Abstraction This generic class is the model in a particularization of MVC, to vector registers |
| CParseParam< VecRegContainer< Sz > > | Calls required for serialization/deserialization |
| CShowParam< VecRegContainer< Sz > > | |
| CDummyVecRegContainer | Dummy type aliases and constants for architectures that do not implement vector registers |
| CParseParam< DummyVecRegContainer > | |
| CIdleStartEvent | |
| ►CMipsLinux | |
| Ctgt_sysinfo | |
| CMipsProcess | |
| ►CBaseRemoteGDB | |
| ►CGdbCommand | |
| CContext | |
| ►CGdbMultiLetterCommand | |
| CContext | |
| ►CQuerySetCommand | |
| CContext | |
| CSocketEvent | |
| CTrapEvent | |
| ►CPowerLinux | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctms | For times() |
| CPowerProcess | |
| CRiscvLinux | |
| ►CRiscvLinux64 | |
| Ctgt_fsid_t | |
| Ctgt_stat64 | |
| Ctgt_statfs | |
| Ctgt_sysinfo | |
| Ctimespec | |
| ►CRiscvLinux32 | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Ctgt_fsid_t | |
| Ctgt_stat | |
| Ctgt_statfs | |
| Ctgt_sysinfo | |
| Ctimespec | |
| CPMAChecker | Based on the RISC-V ISA privileged specifications V1.11, there is no implementation guidelines on the Physical Memory Attributes |
| ►CPMP | This class helps to implement RISCV's physical memory protection (pmp) primitive |
| CPmpEntry | Single pmp entry struct |
| CRiscvProcess | |
| CRiscvProcess64 | |
| CRiscvProcess32 | |
| ►CSparcLinux | |
| Ctgt_stat | |
| Ctgt_stat64 | |
| Ctgt_sysinfo | |
| ►CSparc32Linux | |
| Ctgt_stat64 | |
| Ctgt_sysinfo | |
| CSparcProcess | |
| CSparc32Process | |
| CSparc64Process | |
| CSparcPseudoInstABI | |
| CSparcSolaris | |
| CFXSave | |
| CX86KvmCPU | X86 implementation of a KVM-based hardware virtualized CPU |
| ►CX86Linux | |
| CSyscallABI | |
| ►CX86Linux64 | |
| Ctgt_clone_args | |
| Ctgt_fsid | |
| Ctgt_iovec | |
| Ctgt_stat64 | |
| Ctgt_statfs | |
| Ctgt_sysinfo | |
| ►CX86Linux32 | |
| Ctgt_stat64 | |
| Ctgt_sysinfo | |
| CX86PseudoInstABI | |
| ►CAddrRange | Encapsulates an address range, and supports a number of tests to check if two ranges intersect, if a range contains a specific address etc |
| CDummy | |
| CAddrRangeMap | The AddrRangeMap uses an STL map to implement an interval tree for address decoding |
| CAtomicOpFunctor | |
| CTypedAtomicOpFunctor | |
| CAtomicGeneric2Op | |
| CAtomicGeneric3Op | |
| CAtomicGenericPair3Op | |
| CAtomicOpAnd | |
| CAtomicOpOr | |
| CAtomicOpXor | |
| CAtomicOpExch | |
| CAtomicOpAdd | |
| CAtomicOpSub | |
| CAtomicOpInc | |
| CAtomicOpDec | |
| CAtomicOpMax | |
| CAtomicOpMin | |
| CBarrier | |
| ►CBitfieldTypeImpl | |
| ►CTypeDeducer | |
| CT | |
| CT< void(C::*)(Type1 &, Type2)> | |
| CWrapper | |
| CBitfieldType | |
| CBitfieldROType | |
| CBitfieldWOType | |
| CParseParam< BitUnionType< T > > | |
| CShowParam< BitUnionType< T > > | |
| ►CBmpWriter | |
| CBmpPixel32 | |
| CCompleteV1Header | |
| CFileHeader | |
| CInfoHeaderV1 | |
| CCallbackQueue | |
| CChannelAddr | Class holding a guest address in a contiguous channel-local address space |
| CChannelAddrRange | The ChanneelAddrRange class describes a contiguous range of addresses in a contiguous channel-local address space |
| CChunkGenerator | This class takes an arbitrary memory region (address/length pair) and generates a series of appropriately (e.g |
| CCircleBuf | Circular buffer backed by a vector |
| CFifo | Simple FIFO implementation backed by a circular buffer |
| ►CCircularQueue | Circular queue |
| Citerator | Iterator to the circular queue |
| ►CCoroutine | This template defines a Coroutine wrapper type with a Boost-like interface |
| CCallerType | CallerType: A reference to an object of this class will be passed to the coroutine task |
| CEmpty | |
| CFiber | This class represents a fiber, which is a light weight sort of thread which is cooperatively scheduled and runs sequentially with other fibers, swapping in and out of a single actual thread of execution |
| CFlags | Wrapper that groups a few flag bits under the same undelying container |
| CFrameBuffer | Internal gem5 representation of a frame buffer |
| CGTestTickHandler | |
| ►CGTestLogOutput | |
| CEventHook | |
| CSerializationFixture | Fixture class that handles temporary directory creation |
| CImgWriter | |
| ►CIniFile | This class represents the contents of a ".ini" file |
| CEntry | A single key/value pair |
| CSection | A section |
| ►CLogger | |
| CLoc | |
| CObjectMatch | ObjectMatch contains a vector of expressions |
| CMemoizer | This class takes a function as a constructor argument and memoizes it: every time the function gets invoked through the Memoizer object (see operator()), the result gets saved in the internal cache, ready to be retrieved next time an invokation is made with the same arguments |
| CNamed | Interface for things with names |
| COutputStream | |
| COutputFile | |
| COutputDirectory | Interface for creating files in a gem5 output directory |
| CPixel | Internal gem5 representation of a Pixel |
| ►CPixelConverter | Configurable RGB pixel converter |
| CChannel | Color channel conversion and scaling helper class |
| ►CPngWriter | Image writer implementing support for PNG |
| CPngPixel24 | Png Pixel type: not containing padding |
| CPngStructHandle | |
| CPollEvent | |
| CPollQueue | |
| CPrintable | Abstract base class for objects which support being printed to a stream for debugging |
| CRandom | |
| CRefCounted | Derive from RefCounted if you want to enable reference counting of this class |
| CRefCountingPtr | If you want a reference counting pointer to a mutable object, create it like this: |
| CHardBreakpoint | |
| CBaseGdbRegCache | Concrete subclasses of this abstract class represent how the register values are transmitted on the wire |
| CGenericSatCounter | Implements an n bit saturating counter and provides methods to increment, decrement, and read it |
| CListenSocket | |
| CTemperature | The class stores temperatures in Kelvin and provides helper methods to convert to/from Celsius |
| CTime | |
| CStringWrap | |
| ►CTrie | A trie is a tree-based data structure used for data retrieval |
| CNode | |
| CCycles | Cycles is a wrapper class for representing cycle counts, i.e |
| CUncontendedMutex | |
| CVncKeyboard | A device that expects to receive input from the vnc server should derrive (through mulitple inheritence if necessary from VncKeyboard or VncMouse and call setKeyboard() or setMouse() respectively on the vnc server |
| CVncMouse | |
| ►CVncInput | |
| CClientCutTextMessage | |
| CFrameBufferUpdateReq | |
| CKeyEventMessage | |
| CPixelEncodingsMessage | |
| CPixelFormat | |
| CPixelFormatMessage | |
| CPointerEventMessage | |
| ►CVncServer | |
| CDataEvent | DataEvent to read data from vnc |
| CFrameBufferRect | |
| CFrameBufferUpdate | |
| CListenEvent | ListenEvent to accept a vnc client connection |
| CServerCutText | |
| CServerInitMsg | |
| CActivityRecorder | ActivityRecorder helper class that informs the CPU if it can switch over to being idle or not |
| CAddressMonitor | |
| CCPUProgressEvent | |
| ►CBaseCPU | |
| CBaseCPUStats | |
| CGlobalStats | Global CPU statistics that are merged into the Root object |
| CCheckerCPU | CheckerCPU class |
| CChecker | Templated Checker class |
| CCheckerThreadContext | Derived ThreadContext class for use with the Checker |
| CDummyChecker | Specific non-templated derived class used for SimObject configuration |
| CExecContext | The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model |
| COpDesc | |
| CFUDesc | |
| CFuncUnit | |
| CInstResult | |
| ►CBaseKvmCPU | Base class for KVM based CPU models |
| CKVMCpuPort | KVM memory port |
| CStatGroup | |
| CKvmDevice | KVM device wrapper |
| CPerfKvmCounterConfig | PerfEvent counter configuration |
| CPerfKvmCounter | An instance of a performance counter |
| CBaseKvmTimer | Timer functions to interrupt VM execution after a number of simulation ticks |
| CPosixKvmTimer | Timer based on standard POSIX timers |
| CPerfKvmTimer | PerfEvent based timer using the host's CPU cycle counter |
| CKvm | KVM parent interface |
| ►CKvmVM | KVM VM container |
| CMemorySlot | Structures tracking memory slots |
| CMemSlot | |
| ►CMinorCPU | MinorCPU is an in-order CPU model with four fixed pipeline stages: |
| CMinorCPUPort | Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Execute |
| CMinorOpClass | Boxing for MinorOpClass to get around a build problem with C++11 but also allow for future additions to op class checking |
| CMinorOpClassSet | Wrapper for a matchable set of op classes |
| CMinorFUTiming | Extra timing capability to allow individual ops to have their source register dependency latencies tweaked based on the ExtMachInst of the source instruction |
| CMinorFU | A functional unit that can execute any of opClasses operations with a single op(eration)Lat(ency) and issueLat(ency) associated with the unit rather than each operation (as in src/FuncUnit) |
| CMinorFUPool | A collection of MinorFUs |
| CSNHash | |
| CPCEvent | |
| CPCEventScope | |
| ►CPCEventQueue | |
| CMapCompare | |
| CBreakPCEvent | |
| CPanicPCEvent | |
| CBaseStackTrace | |
| CProfileNode | |
| CFunctionProfile | |
| CRegId | Register ID: describe an architectural register with its class and index |
| CRegClassOps | |
| CRegClass | |
| CRegClassIterator | |
| CTypedRegClassOps | |
| CVecElemRegClassOps | |
| CPhysRegId | Physical register ID |
| CRegFile | |
| ►CAtomicSimpleCPU | |
| CAtomicCPUDPort | |
| CAtomicCPUPort | An AtomicCPUPort overrides the default behaviour of the recvAtomicSnoop and ignores the packet instead of panicking |
| CBaseSimpleCPU | |
| ►CSimpleExecContext | |
| CExecContextStats | |
| CNonCachingSimpleCPU | The NonCachingSimpleCPU is an AtomicSimpleCPU using the 'atomic_noncaching' memory mode instead of just 'atomic' |
| ►CSimPoint | |
| CBBInfo | Basic Block information |
| ►CTimingSimpleCPU | |
| ►CDcachePort | |
| CDTickEvent | |
| CFetchTranslation | |
| ►CIcachePort | |
| CITickEvent | |
| CIprEvent | |
| CSplitFragmentSenderState | |
| CSplitMainSenderState | |
| ►CTimingCPUPort | A TimingCPUPort overrides the default behaviour of the recvTiming and recvRetry and implements events for the scheduling of handling of incoming packets in the following cycle |
| CTickEvent | |
| CSimpleThread | The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface |
| CStaticInst | Base, ISA-independent static instruction class |
| CDirectedGenerator | |
| CInvalidateGenerator | |
| ►CRubyDirectedTester | |
| CCpuPort | |
| CSeriesRequestGenerator | |
| ►CGarnetSyntheticTraffic | |
| CCpuPort | |
| CGarnetSyntheticTrafficSenderState | |
| ►CAddressManager | |
| CAtomicStruct | |
| CLastWriter | |
| CCpuThread | |
| CDmaThread | |
| ►CEpisode | |
| CAction | |
| CGpuWavefront | |
| ►CProtocolTester | |
| CGMTokenPort | |
| CSenderState | |
| CSeqPort | |
| CTesterDma | |
| ►CTesterThread | |
| CDeadlockCheckEvent | |
| COutstandingReq | |
| CTesterThreadEvent | |
| ►CMemTest | Tests a cache coherent memory system by generating false sharing and verifying the read data against a reference updated on the completion of writes |
| CCpuPort | |
| CMemTestStats | |
| CCheck | |
| CCheckTable | |
| ►CRubyTester | |
| CCpuPort | |
| CSenderState | |
| ►CBaseTrafficGen | The traffic generator is a module that generates stimuli for the memory system, based on a collection of simple generator behaviours that are either probabilistic or based on traces |
| CStatGroup | |
| CTrafficGenPort | Request port specialisation for the traffic generator |
| CBaseGen | Base class for all generators, with the shared functionality and virtual functions for entering, executing and leaving the generator |
| CStochasticGen | |
| CDramGen | DRAM specific generator is for issuing request with variable page hit length and bank utilization |
| CDramRotGen | |
| CExitGen | The exit generator exits from the simulation once entered |
| ►CGUPSGen | |
| CGenPort | Definition of the GenPort class which is of the type RequestPort |
| CGUPSGenStat | |
| CHybridGen | Hybrid NVM + DRAM specific generator is for issuing request with variable buffer hit length and bank utilization |
| CIdleGen | The idle generator does nothing |
| CLinearGen | The linear generator generates sequential requests from a start to an end address, with a fixed block size |
| CNvmGen | NVM specific generator is for issuing request with variable buffer hit length and bank utilization |
| CPyTrafficGen | |
| CRandomGen | The random generator is similar to the linear one, but does not generate sequential addresses |
| CStreamGen | |
| CFixedStreamGen | |
| CRandomStreamGen | |
| CStridedGen | The strided generator generates sequential requests from a start to an end address, with a fixed block size |
| ►CTraceGen | The trace replay generator reads a trace file and plays back the transactions |
| CInputStream | The InputStream encapsulates a trace file and the internal buffers and populates TraceElements based on the input |
| CTraceElement | This struct stores a line in the trace file |
| ►CTrafficGen | The traffic generator is a module that generates stimuli for the memory system, based on a collection of simple behaviours that are either probabilistic or based on traces |
| CTransition | Struct to represent a probabilistic transition during parsing |
| CThreadContext | ThreadContext is the external interface to all thread state for anything outside of the CPU |
| ►CThreadState | Struct for holding general thread state that is needed across CPU models |
| CThreadStateStats | |
| ►CTimeBuffer | |
| Cwire | |
| CTimingExprEvalContext | Object to gather the visible context for evaluation |
| CTimingExpr | |
| CTimingExprLiteral | |
| CTimingExprSrcReg | |
| CTimingExprLet | |
| CTimingExprRef | |
| CTimingExprUn | |
| CTimingExprBin | |
| CTimingExprIf | |
| ►CTraceCPU | The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model |
| CDcachePort | DcachePort class that interfaces with L1 Data Cache |
| ►CElasticDataGen | The elastic data memory request generator to read protobuf trace containing execution trace annotated with data and ordering dependencies |
| CElasticDataGenStatGroup | |
| CGraphNode | The struct GraphNode stores an instruction in the trace file |
| CHardwareResource | Models structures that hold the in-flight nodes |
| CInputStream | The InputStream encapsulates a trace file and the internal buffers and populates GraphNodes based on the input |
| CReadyNode | Struct to store a ready-to-execute node and its execution tick |
| ►CFixedRetryGen | Generator to read protobuf trace containing memory requests at fixed timestamps, perform flow control and issue memory requests |
| CFixedRetryGenStatGroup | |
| CInputStream | The InputStream encapsulates a trace file and the internal buffers and populates TraceElements based on the input |
| CTraceElement | This struct stores a line in the trace file |
| CIcachePort | IcachePort class that interfaces with L1 Instruction Cache |
| CTraceStats | |
| CWholeTranslationState | This class captures the state of an address translation |
| CDataTranslation | This class represents part of a data address translation |
| CAMDGPUDevice | Device model for an AMD GPU |
| ►CAMDGPUVM | |
| CAGPTranslationGen | Translation range generators |
| CAMDGPUSysVMContext | |
| CGARTTranslationGen | |
| CGEM5_PACKED | |
| CMMHUBTranslationGen | |
| CUserTranslationGen | |
| CAMDGPUInterruptCookie | |
| CAMDGPUIHRegs | Struct to contain all interrupt handler related registers |
| ►CAMDGPUInterruptHandler | |
| CDmaEvent | |
| CSenderState | |
| ►CAMDGPUMemoryManager | |
| ►CGPUMemPort | |
| CSenderState | |
| CRequestStatus | |
| ►CAMDMMIOReader | Helper class to read Linux kernel MMIO trace from amdgpu modprobes |
| CMmioTrace | |
| CGEM5_PACKED | PM4 packets |
| CPM4PacketProcessor | |
| CPrimaryQueue | |
| CPM4Queue | Class defining a PM4 queue |
| ►CSDMAEngine | System DMA Engine class for AMD dGPU |
| CSDMAQueue | |
| ►CAMDGPUSystemHub | This class handles reads from the system/host memory space from the shader |
| CResponseEvent | |
| CA9SCU | |
| CAbstractNVM | This is an interface between the disk interface (which will handle the disk data transactions) and the timing model |
| CAmbaDevice | |
| CAmbaPioDevice | |
| CAmbaIntDevice | |
| CAmbaDmaDevice | |
| CAmbaFake | |
| CBaseGic | |
| CArmInterruptPinGen | This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator |
| CArmSPIGen | Shared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a pointer to it and returns it every time it is asked for it (via the get metod) |
| CArmPPIGen | Private Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of generating more than one interrupt (one per ContextID) |
| CArmSigInterruptPinGen | |
| CArmInterruptPin | Generic representation of an Arm interrupt pin |
| CArmSPI | |
| CArmPPI | |
| CArmSigInterruptPin | |
| CMhuDoorbell | |
| CScp2ApDoorbell | |
| CAp2ScpDoorbell | |
| CMHU | Message Handling Unit |
| CScp | |
| CDisplay | |
| CDoorbell | Generic doorbell interface |
| CEnergyCtrl | |
| ►CFlashDevice | Flash Device model The Flash Device model is a timing model for a NAND flash device |
| CCallBackEntry | |
| CFlashDeviceStats | |
| CPageMapEntry | Every logical address maps to a physical block and a physical page |
| ►CFVPBasePwrCtrl | |
| CRegisters | |
| CSystemCounterListener | Abstract class for elements whose events depend on the counting speed of the System Counter |
| CSystemCounter | Global system counter |
| CArchTimer | Per-CPU architected timer |
| CArchTimerKvm | |
| ►CGenericTimer | |
| ►CCoreTimers | |
| CEventStream | |
| CGenericTimerISA | |
| CGenericTimerFrame | |
| CGenericTimerMem | |
| CGicV2Registers | |
| ►CGicV2 | |
| CBankedRegs | Registers "banked for each connected processor" per ARM IHI0048B |
| CGicv2mFrame | Ultimately this class should be embedded in the Gicv2m class, but this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame' in namespace Gicv2m |
| CGicv2m | |
| CGicv3Registers | |
| CGicv3 | |
| ►CGicv3CPUInterface | |
| Chppi_t | |
| CGicv3Distributor | |
| CItsAction | |
| ►CGicv3Its | GICv3 ITS module |
| CDataPort | |
| CItsProcess | ItsProcess is a base coroutine wrapper which is spawned by the Gicv3Its module when the latter needs to perform different actions, like translating a peripheral's MSI into an LPI (See derived ItsTranslation) or processing a Command from the ITS queue (ItsCommand) |
| CItsTranslation | An ItsTranslation is created whenever a peripheral writes a message in GITS_TRANSLATER (MSI) |
| ►CItsCommand | An ItsCommand is created whenever there is a new command in the command queue |
| CCommandEntry | |
| CDispatchEntry | Dispatch entry is a metadata struct which contains information about the command (like the name) and the function object implementing the command |
| CGicv3Redistributor | |
| CNoMaliGpu | |
| CCustomNoMaliGpu | |
| ►CHDLcd | |
| CDmaEngine | |
| CHDLcdStats | |
| CPixelPump | |
| CPl050 | |
| CGenericArmPciHost | |
| CPl011 | |
| CPl111 | |
| CRealView | |
| CPL031 | |
| ►CRealViewCtrl | |
| CDevice | |
| CRealViewOsc | This is an implementation of a programmable oscillator on the that can be configured through the RealView/Versatile Express configuration interface |
| CRealViewTemperatureSensor | This device implements the temperature sensor used in the RealView/Versatile Express platform |
| ►CSMMUv3 | |
| CSMMUv3Stats | |
| ►CSMMUv3BaseCache | |
| CSMMUv3BaseCacheStats | |
| ►CSMMUTLB | |
| CEntry | |
| ►CARMArchTLB | |
| CEntry | |
| ►CIPACache | |
| CEntry | |
| ►CConfigCache | |
| CEntry | |
| ►CWalkCache | |
| CEntry | |
| CWalkCacheStats | |
| CSMMUCommandExecProcess | |
| CSMMURegs | |
| CStreamTableEntry | |
| CContextDescriptor | |
| CSMMUCommand | |
| CSMMUEvent | |
| CSMMUv3DeviceInterface | |
| CSMMUDeviceRetryEvent | |
| CSMMURequestPort | |
| CSMMUTableWalkPort | |
| CSMMUDevicePort | |
| CSMMUControlPort | |
| CSMMUATSMemoryPort | |
| CSMMUATSDevicePort | |
| CSMMUAction | |
| CSMMUSemaphore | |
| CSMMUSignal | |
| CSMMUProcess | |
| CSMMUTranslRequest | |
| ►CSMMUTranslationProcess | |
| CTranslContext | |
| CTranslResult | |
| CSysSecCtrl | System Security Control registers |
| ►CCpuLocalTimer | |
| CTimer | |
| ►CSp804 | |
| CTimer | |
| ►CUFSHostDevice | Host controller layer: This is your Host controller This layer handles the UFS functionality |
| CHCIMem | Host Controller Interface This is a set of registers that allow the driver to control the transactions to the flash devices |
| CLUNInfo | Logic unit information structure |
| CSCSIReply | SCSI reply structure |
| CSCSIResumeInfo | After a SCSI command has been identified, the SCSI resume function will handle it |
| CtaskStart | Task start information |
| CtransferDoneInfo | Transfer completion info |
| CtransferInfo | Different events, and scenarios require different types of information |
| CtransferStart | Transfer start information |
| CUFSHCDSGEntry | Struct UFSHCDSGEntry - UFSHCI PRD Entry baseAddr: Lower 32bit physical address DW-0 upperAddr: Upper 32bit physical address DW-1 reserved: Reserved for future use DW-2 size: size of physical segment DW-3 |
| CUFSHostDeviceStats | Statistics |
| CUFSSCSIDevice | Device layer: This is your Logic unit This layer implements the SCSI functionality of the UFS Device One logic unit controls one or more disk partitions |
| CUPIUMessage | UPIU tranfer message |
| CUTPTransferCMDDesc | Struct UTPTransferCMDDesc - UFS Commad Descriptor structure commandUPIU: Command UPIU Frame address responseUPIU: Response UPIU Frame address PRDTable: Physcial Region Descriptor All lengths as defined by JEDEC220 |
| ►CUTPTransferReqDesc | Struct UTPTransferReqDesc - UTRD structure header: UTRD header DW-0 to DW-3 commandDescBaseAddrLo: UCD base address low DW-4 commandDescBaseAddrHi: UCD base address high DW-5 responseUPIULength: response UPIU length DW-6 responseUPIUOffset: response UPIU offset DW-6 PRDTableLength: Physical region descriptor length DW-7 PRDTableOffset: Physical region descriptor offset DW-7 |
| CRequestDescHeader | Struct RequestDescHeader dword0: Descriptor Header DW0 dword1: Descriptor Header DW1 dword2: Descriptor Header DW2 dword3: Descriptor Header DW3 |
| CUTPUPIUHeader | All the data structures are defined in the UFS standard This standard be found at the JEDEC website free of charge (login required): http://www.jedec.org/standards-documents/results/jesd220 |
| CUTPUPIURSP | Struct UTPUPIURSP - Response UPIU structure header: UPIU header DW-0 to DW-2 residualTransferCount: Residual transfer count DW-3 reserved: Reserved DW-4 to DW-7 senseDataLen: Sense data length DW-8 U16 senseData: Sense data field DW-8 to DW-12 |
| CUTPUPIUTaskReq | Struct UTPUPIUTaskReq - Task request UPIU structure header - UPIU header structure DW0 to DW-2 inputParam1: Input param 1 DW-3 inputParam2: Input param 2 DW-4 inputParam3: Input param 3 DW-5 reserved: Reserver DW-6 to DW-7 |
| CwriteToDiskBurst | Disk transfer burst information |
| CVGic | |
| CMmioVirtIO | |
| ►CGenericWatchdog | |
| CListener | System Counter Listener: This object is being notified any time there is a change in the SystemCounter |
| CSp805 | |
| CBadDevice | BadDevice This device just panics when accessed |
| ►CDmaPort | |
| CDmaReqState | |
| CDmaDevice | |
| CDmaCallback | DMA callback class |
| ►CDmaReadFifo | Buffered DMA engine helper class |
| CDmaDoneEvent | |
| ►CDmaVirtDevice | |
| CDmaVirtCallback | Wraps a std::function object in a DmaCallback |
| Chsa_packet_header_bitfield_t | |
| C_hsa_dispatch_packet_t | |
| C_hsa_agent_dispatch_packet_t | |
| C_hsa_barrier_and_packet_t | |
| C_hsa_barrier_or_packet_t | |
| CHSAQueueDescriptor | |
| CAQLRingBuffer | Internal ring buffer which is used to prefetch/store copies of the in-memory HSA ring buffer |
| CQCntxt | |
| ►CHSAPacketProcessor | |
| Cdma_series_ctx | Calls getCurrentEntry once the queueEntry has been dmaRead |
| CQueueProcessEvent | |
| CRQLEntry | |
| CSignalState | |
| C_hsa_signal_t | |
| C_hsa_queue_t | |
| C_amd_queue_t | |
| Camd_signal_s | |
| ►CHWScheduler | |
| CSchedulerWakeupEvent | |
| Ckfd_ioctl_get_version_args | |
| Ckfd_ioctl_create_queue_args | |
| Ckfd_ioctl_destroy_queue_args | |
| Ckfd_ioctl_update_queue_args | |
| Ckfd_ioctl_set_cu_mask_args | |
| Ckfd_ioctl_get_queue_wave_state_args | |
| Ckfd_ioctl_set_memory_policy_args | |
| Ckfd_ioctl_get_clock_counters_args | |
| Ckfd_process_device_apertures | |
| Ckfd_ioctl_get_process_apertures_args | |
| Ckfd_ioctl_get_process_apertures_new_args | |
| Ckfd_ioctl_dbg_register_args | |
| Ckfd_ioctl_dbg_unregister_args | |
| Ckfd_ioctl_dbg_address_watch_args | |
| Ckfd_ioctl_dbg_wave_control_args | |
| Ckfd_ioctl_create_event_args | |
| Ckfd_ioctl_destroy_event_args | |
| Ckfd_ioctl_set_event_args | |
| Ckfd_ioctl_reset_event_args | |
| Ckfd_memory_exception_failure | |
| Ckfd_hsa_memory_exception_data | |
| Ckfd_hsa_hw_exception_data | |
| Ckfd_event_data | |
| Ckfd_ioctl_wait_events_args | |
| Ckfd_ioctl_set_scratch_backing_va_args | |
| Ckfd_ioctl_get_tile_config_args | |
| Ckfd_ioctl_set_trap_handler_args | |
| Ckfd_ioctl_acquire_vm_args | |
| Ckfd_ioctl_alloc_memory_of_gpu_args | |
| Ckfd_ioctl_free_memory_of_gpu_args | |
| Ckfd_ioctl_map_memory_to_gpu_args | |
| Ckfd_ioctl_unmap_memory_from_gpu_args | |
| Ckfd_ioctl_alloc_queue_gws_args | |
| Ckfd_ioctl_get_dmabuf_info_args | |
| Ckfd_ioctl_import_dmabuf_args | |
| Ckfd_ioctl_smi_events_args | |
| CI2CBus | |
| CI2CDevice | |
| ►CIntel8254Timer | Programmable Interval Timer (Intel 8254) |
| ►CCounter | Counter element for PIT |
| CCounterEvent | Event for counter interrupt |
| CIntSinkPinBase | |
| CIntSinkPin | |
| CIntSourcePinBase | |
| CIntSourcePin | |
| CPioPort | The PioPort class is a programmed i/o port that all devices that are sensitive to an address range use |
| CPioDevice | This device is the base class which all devices senstive to an address range inherit from |
| CBasicPioDevice | |
| CIsaFake | IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and rites |
| CLupioBLK | LupioBLK: A virtual block device which aims to provide a disk-like interface for second-level storage |
| CLupioIPI | LupioIPI: An inter-processor interrupt virtual device |
| CLupioPIC | LupioPIC: A programmable interrupt controller virtual device that can manage input IRQs coming from up to 32 sources |
| CLupioRNG | LupioRNG: A Random Number Generator virtual device that returns either a random value, or a seed that can be configured by the user |
| CLupioRTC | LupioRTC: A Real-Time Clock Virtual Device that returns the current date and time in ISO 8601 format |
| CLupioSYS | LupioSYS: A Real-Time System Controller virtual device which provides a way for the software to halt or reboot the computer system |
| ►CLupioTMR | LupioTMR: A virtual timer device which provides a real time counter, as well as a configurable timer offering periodic and one shot modes |
| CLupioTimer | |
| CLupioTTY | LupioTTY: The LupioTTY is a virtual terminal device that can both transmit characters to a screen, as well as receive characters input from a keyboard |
| ►CMC146818 | Real-Time Clock (MC146818) |
| CRTCEvent | Event for RTC periodic interrupt |
| CRTCTickEvent | Event for RTC periodic interrupt |
| CMalta | Top level class for Malta Chipset emulation |
| CMaltaCChip | Malta CChip CSR Emulation |
| ►CMaltaIO | Malta I/O device is a catch all for all the south bridge stuff we care to implement |
| CRTC | |
| ►CDistEtherLink | Model for a fixed bandwidth full duplex ethernet link |
| CLink | Model base class for a single uni-directional link |
| CLocalIface | Interface to the local simulated system |
| CRxLink | Model for a receive link |
| CTxLink | Model for a send link |
| ►CDistIface | The interface class to talk to peer gem5 processes |
| ►CRecvScheduler | Class to encapsulate information about data packets received |
| CDesc | Received packet descriptor |
| CSync | This class implements global sync operations among gem5 peer processes |
| CSyncEvent | The global event to schedule periodic dist sync |
| CSyncNode | |
| CSyncSwitch | |
| ►CDistHeaderPkt | |
| CHeader | |
| CEtherBus | |
| ►CEtherDevice | |
| CEtherDeviceStats | |
| CEtherDevBase | Dummy class to keep the Python class hierarchy in sync with the C++ object hierarchy |
| Cpcap_file_header | |
| Cpcap_pkthdr | |
| CEtherDump | |
| CEtherInt | |
| ►CEtherLink | |
| CInterface | |
| CLink | |
| CEthPacketData | |
| ►CEtherSwitch | |
| ►CInterface | Model for an Ethernet switch port |
| ►CPortFifo | |
| CEntryOrder | |
| CPortFifoEntry | |
| CSwitchTableEntry | |
| CTapEvent | |
| ►CTapListener | |
| CEvent | |
| CEtherTapBase | |
| CEtherTapInt | |
| CEtherTapStub | |
| ►CIGbE | |
| CDescCache | |
| CRxDescCache | |
| CTxDescCache | |
| CIGbEInt | |
| Cdp_regs | Ethernet device registers |
| Cdp_rom | |
| CNSGigE | NS DP83820 Ethernet device model |
| CNSGigEInt | |
| Cns_desc32 | |
| Cns_desc64 | |
| CPacketFifoEntry | |
| CPacketFifo | |
| ►CTCPIface | |
| CNodeInfo | Compute node info and storage for the very first connection from each node (used by the switch) |
| ►CCopyEngine | |
| CCopyEngineChannel | |
| CCopyEngineStats | |
| CPciBar | |
| CPciBarNone | |
| CPciIoBar | |
| CPciLegacyIoBar | |
| CPciMemBar | |
| CPciMemUpperBar | |
| CPciDevice | PCI device, base implementation is only config space |
| ►CPciHost | The PCI host describes the interface between PCI devices and a simulated system |
| CDeviceInterface | Callback interface from PCI devices to the host |
| CGenericPciHost | Configurable generic PCI host interface |
| CPciBusAddr | |
| CDisplayTimings | |
| ►CBasePixelPump | Timing generator for a pixel-based display |
| CPixelEvent | Callback helper class with suspend support |
| CPlatform | |
| ►CRegisterBankBase | |
| CRegisterBaseBase | |
| ►CRegisterBank | |
| CRegister | |
| CRegisterBase | |
| CRegisterBuf | |
| CRegisterLBuf | |
| CRegisterRao | |
| CRegisterRaz | |
| CRegisterRoFill | |
| CParseParam< T, std::enable_if_t< std::is_base_of_v< typename RegisterBankBase::RegisterBaseBase, T > > > | |
| CShowParam< T, std::enable_if_t< std::is_base_of_v< typename RegisterBankBase::RegisterBaseBase, T > > > | |
| CResetResponsePortBase | |
| CResetResponsePort | |
| CResetRequestPort | |
| ►CClint | NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive.cdn.prismic.io/sifive/fab000f6- 0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_ full_20G1.03.00_manual.pdf |
| CClintRegisters | MMIO Registers 0x0000 - 0x3FFF: msip (write-through to misc reg file) ...: reserved[0] 0x4000 - 0xBFF7: mtimecmp ...: reserved[1] 0xBFF8: mtime (read-only) |
| CHiFive | |
| CLupV | The LupV collection consists of a RISC-V processor, as well as the set of LupiIO devices |
| CGenericRiscvPciHost | |
| CPlicOutput | NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive.cdn.prismic.io/sifive/fab000f6- 0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_ full_20G1.03.00_manual.pdf |
| ►CPlic | |
| CPlicRegisters | MMIO Registers |
| CPlicIntDevice | |
| ►CRiscvRTC | NOTE: This is a generic wrapper around the MC146818 RTC |
| CRTC | |
| CSerialDevice | Base class for serial devices such as terminals |
| CSerialNullDevice | Dummy serial device that discards all data sent to it |
| CSimpleUart | |
| ►CTerminal | |
| CDataEvent | |
| CListenEvent | |
| CUart | |
| ►CUart8250 | |
| ►CRegisters | |
| CBankedRegister | |
| CPairedRegister | |
| CRWSwitchedRegister | |
| CDumbTOD | DumbTOD simply returns some idea of time when read |
| ►CIob | |
| CIntBusy | |
| CIntCtl | |
| CIntMan | |
| CMmDisk | |
| CT1000 | |
| CDiskImage | Basic interface for accessing a disk image |
| CRawDiskImage | Specialization for accessing a raw disk image |
| ►CCowDiskImage | Specialization for accessing a copy-on-write disk image layer |
| CSector | |
| ►CIdeController | Device model for an Intel PIIX4 IDE controller |
| ►CChannel | |
| CBMIRegs | Registers used for bus master interface |
| CPrdEntry_t | |
| CPrdTableEntry | |
| CCommandReg_t | |
| ►CIdeDisk | IDE Disk device model |
| CIdeDiskStats | |
| CSimpleDisk | |
| CVirtDescriptor | VirtIO descriptor (chain) wrapper |
| ►CVirtQueue | Base wrapper around a virtqueue |
| ►CVirtRing | VirtIO ring buffer wrapper |
| CHeader | |
| CVirtIODeviceBase | Base class for all VirtIO-based devices |
| CVirtIODummyDevice | |
| ►CVirtIOBlock | VirtIO block device |
| CBlkRequest | VirtIO block device request as sent by guest |
| CConfig | Block device configuration structure |
| CRequestQueue | Virtqueue for disk requests |
| ►CVirtIOConsole | VirtIO console |
| CConfig | Console configuration structure |
| CTermRecvQueue | Virtqueue for data going from the host to the guest |
| CTermTransQueue | Virtqueue for data going from the guest to the host |
| CP9MsgInfo | |
| CP9MsgHeader | |
| ►CVirtIO9PBase | This class implements a VirtIO transport layer for the 9p network file system |
| CConfig | VirtIO 9p configuration structure |
| CFSQueue | Virtqueue for 9p requests |
| CVirtIO9PProxy | VirtIO 9p proxy base class |
| ►CVirtIO9PDiod | VirtIO 9p proxy that communicates with the diod 9p server using pipes |
| CDiodDataEvent | |
| ►CVirtIO9PSocket | VirtIO 9p proxy that communicates with a 9p server over tcp sockets |
| CSocketDataEvent | |
| CPciVirtIO | |
| ►CVirtIORng | VirtIO Rng |
| CRngQueue | Virtqueue for data going from the host to the guest |
| CX86IdeController | |
| CPc | |
| CSouthBridge | |
| CPipeStageIFace | |
| CScoreboardCheckToSchedule | Communication interface between ScoreboardCheck and Schedule stages |
| CScheduleToExecute | Communication interface between Schedule and Execute stages |
| CWFBarrier | WF barrier slots |
| ►CComputeUnit | |
| CComputeUnitStats | |
| ►CDataPort | Data access Port |
| CSenderState | |
| CSystemHubEvent | |
| ►CDTLBPort | Data TLB port |
| CSenderState | SenderState is information carried along with the packet throughout the TLB hierarchy |
| CGMTokenPort | |
| ►CITLBPort | |
| CSenderState | SenderState is information carried along with the packet throughout the TLB hierarchy |
| ►CLDSPort | Port intended to communicate between the CU and its LDS |
| CSenderState | SenderState is information carried along with the packet, esp |
| ►CScalarDataPort | |
| CMemReqEvent | |
| CSenderState | |
| CSystemHubEvent | |
| ►CScalarDTLBPort | |
| CSenderState | |
| ►CSQCPort | |
| CSenderState | |
| ►CGPUDispatcher | |
| CGPUDispatcherStats | |
| CDynPoolManager | |
| ►CExecStage | |
| CExecStageStats | |
| ►CFetchStage | |
| CFetchStageStats | |
| ►CFetchUnit | |
| CFetchBufDesc | Fetch buffer descriptor |
| CSystemHubEvent | |
| ►CGlobalMemPipeline | |
| CGlobalMemPipelineStats | |
| CGPUCommandProcessor | |
| ►CGPUComputeDriver | |
| CDriverWakeupEvent | |
| CEventList | |
| CEventTableEntry | |
| CAtomicOpCAS | |
| CRegisterOperandInfo | |
| CGPUDynInst | |
| CGPUExecContext | |
| CGPURenderDriver | |
| CGPUStaticInst | |
| CKernelLaunchStaticInst | |
| CHSAQueueEntry | |
| CAMDKernelCode | |
| CLdsChunk | This represents a slice of the overall LDS, intended to be associated with an individual workgroup |
| ►CLdsState | |
| CCuSidePort | CuSidePort is the LDS Port closer to the CU side |
| CTickEvent | Event to allow event-driven execution |
| ►CLocalMemPipeline | |
| CLocalMemPipelineStats | |
| CWaitClass | |
| CFloat16 | |
| COFSchedulingPolicy | |
| COperandInfo | |
| CPoolManager | |
| ►CRegisterFile | |
| CMarkRegBusyScbEvent | |
| CMarkRegFreeScbEvent | |
| CRegisterEvent | |
| CRegisterFileStats | |
| CRegisterManager | |
| CRegisterManagerPolicy | Register Manager Policy abstract class |
| CRRSchedulingPolicy | |
| CScalarMemPipeline | |
| CScalarRegisterFile | |
| ►CScheduleStage | |
| CScheduleStageStats | |
| CScheduler | |
| CSchedulingPolicy | Interface class for the wave scheduling policy |
| C__SchedulingPolicy | Intermediate class that derives from the i-face class, and implements its API |
| ►CScoreboardCheckStage | |
| CScoreboardCheckStageStats | |
| CApertureRegister | |
| ►CShader | |
| CShaderStats | |
| CSimplePoolManager | |
| CStaticRegisterManagerPolicy | |
| CVectorRegisterFile | |
| ►CWavefront | |
| CWavefrontStats | |
| CFreeBSD | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha FreeBSD syscall interface |
| COpenFlagTable | |
| ►CLinux | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha Linux syscall interface |
| Cfd_set | |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | |
| Ctgt_iovec | |
| Ctgt_stat | Stat buffer |
| Ctgt_stat64 | |
| Ctimespec | For clock_gettime() |
| Ctimeval | For gettimeofday() |
| Ctms | For times() |
| Cutsname | Interface struct for uname() |
| ►COperatingSystem | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to an operating system syscall interface |
| Crlimit | Limit struct for getrlimit/setrlimit |
| Crusage | For getrusage() |
| Ctgt_iovec | |
| Ctimeval | For gettimeofday() |
| Cutsname | Interface struct for uname() |
| ►CSolaris | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Solaris syscall interface |
| Ctgt_stat | Stat buffer |
| Ctgt_stat64 | |
| Ctgt_timespec | |
| Cutsname | Interface struct for uname() |
| CSkipFuncBase | |
| CGoodbyeObject | |
| CHelloObject | |
| ►CSimpleCache | A very simple cache object |
| CCPUSidePort | Port on the CPU-side that receives requests |
| CMemSidePort | Port on the memory-side that receives responses |
| CSimpleCacheStats | Cache statistics |
| ►CSimpleMemobj | A very simple memory object |
| CCPUSidePort | Port on the CPU-side that receives requests |
| CMemSidePort | Port on the memory-side that receives responses |
| CSimpleObject | |
| ►CAddrMapper | An address mapper changes the packet addresses in going from the response port side of the mapper to the request port side |
| CAddrMapperSenderState | |
| CMapperRequestPort | |
| CMapperResponsePort | |
| CRangeAddrMapper | Range address mapper that maps a set of original ranges to a set of remapped ranges, where a specific range is of the same size (original and remapped), only with an offset |
| CMemBackdoor | |
| ►CBridge | A bridge is used to interface two different crossbars (or in general a memory-mapped requestor and responder), with buffering for requests and responses |
| CBridgeRequestPort | Port on the side that forwards requests and receives responses |
| CBridgeResponsePort | The port on the side that receives requests and sends responses |
| CDeferredPacket | A deferred packet stores a packet along with its scheduled transmission time |
| ►CBaseCache | A basic cache interface |
| CCacheCmdStats | |
| CCacheReqPacketQueue | Override the default behaviour of sendDeferredPacket to enable the memory-side cache port to also send requests based on the current MSHR status |
| CCacheRequestPort | A cache request port is used for the memory-side port of the cache, and in addition to the basic timing port that only sends response packets through a transmit list, it also offers the ability to schedule and send request packets (requests & writebacks) |
| CCacheResponsePort | A cache response port is used for the CPU-side port of the cache, and it is basically a simple timing port that uses a transmit list for responses to the CPU (or connected requestor) |
| CCacheStats | |
| CCpuSidePort | The CPU-side port extends the base cache response port with access functions for functional, atomic and timing requests |
| CDataUpdate | A data contents update is composed of the updated block's address, the old contents, and the new contents |
| CMemSidePort | The memory-side port extends the base cache request port with access functions for functional, atomic and timing snoops |
| CWriteAllocator | The write allocator inspects write packets and detects streaming patterns |
| CCache | A coherent cache that can be arranged in flexible topologies |
| ►CCacheBlk | A Basic Cache block |
| CLock | Represents that the indicated thread context has a "lock" on the block, in the LL/SC sense |
| CTempCacheBlk | Special instance of CacheBlk for use with tempBlk that deals with its block address regeneration |
| CCacheBlkPrintWrapper | Simple class to provide virtual print() method on cache blocks without allocating a vtable pointer for every single cache block |
| ►CMSHR | Miss Status and handling Register |
| CTarget | |
| CTargetList | |
| CMSHRQueue | A Class for maintaining a list of pending and allocated memory requests |
| CNoncoherentCache | A non-coherent cache |
| CAssociativeSet | Associative container based on the previosuly defined Entry type Each element is indexed by a key of type Addr, an additional bool value is used as an additional tag data of the entry |
| CQueue | A high-level queue interface, to be used by both the MSHR queue and the write buffer |
| ►CQueueEntry | A queue entry base class, to be used by both the MSHRs and write-queue entries |
| CTarget | A queue entry is holding packets that will be serviced as soon as resources are available |
| CReplaceableEntry | A replaceable entry is a basic entry in a 2d table-like structure that needs to have replacement functionality |
| ►CBaseTags | A common base class of Cache tagstore objects |
| CBaseTagStats | TODO: It would be good if these stats were acquired after warmup |
| CBaseSetAssoc | A basic cache tag store |
| CCompressedTags | A CompressedTags cache tag store |
| CDueler | A dueler is an entry that may or may not be accounted for sampling |
| CDuelingMonitor | Duel between two sampled options to determine which is the winner |
| CFALRUBlk | A fully associative cache block |
| ►CFALRU | A fully associative LRU cache |
| CCacheTracking | Mechanism that allows us to simultaneously collect miss statistics for multiple caches |
| CPairHash | Hash table type mapping addresses to cache block pointers |
| CBaseIndexingPolicy | A common base class for indexing table locations |
| CSetAssociative | A set associative indexing policy |
| CSkewedAssociative | A skewed associative indexing policy |
| CSectorSubBlk | A sector is composed of sub-blocks, and each sub-block has information regarding its sector and a pointer to its sector tag |
| CSectorBlk | A Basic Sector block |
| ►CSectorTags | A SectorTags cache tag store |
| CSectorTagsStats | |
| CCompressionBlk | A superblock is composed of sub-blocks, and each sub-block has information regarding its superblock and a pointer to its superblock tag |
| CSuperBlk | A basic compression superblock |
| CTaggedEntry | A tagged entry is an entry containing a tag |
| CWriteQueue | A write queue for all eviction packets, i.e |
| ►CWriteQueueEntry | Write queue entry |
| CTargetList | |
| ►CCoherentXBar | A coherent crossbar connects a number of (potentially) snooping requestors and responders, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses |
| CCoherentXBarRequestPort | Declaration of the coherent crossbar memory-side port type, one will be instantiated for each of the CPU-side-port interfaces connecting to the crossbar |
| CCoherentXBarResponsePort | Declaration of the coherent crossbar CPU-side port type, one will be instantiated for each of the mem_side_ports connecting to the crossbar |
| CSnoopRespPort | Internal class to bridge between an incoming snoop response from a CPU-side port and forwarding it through an outgoing CPU-side port |
| ►CCommMonitor | The communication monitor is a SimObject which can monitor statistics of the communication happening between two ports in the memory system |
| CCommMonitorSenderState | Sender state class for the monitor so that we can annotate packets with a transmit time and receive time |
| CMonitorRequestPort | This is the request port of the communication monitor |
| CMonitorResponsePort | This is the CPU-side port of the communication monitor |
| CMonitorStats | Stats declarations, all in a struct for convenience |
| CDRAMPower | DRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system |
| ►CExternalMaster | |
| CExternalPort | Derive from this class to create an external port interface |
| CHandler | |
| CStubSlavePort | Implement a ‘stub’ port which just responds to requests by printing a message |
| CStubSlavePortHandler | |
| ►CExternalSlave | |
| CExternalPort | Derive from this class to create an external port interface |
| CHandler | |
| CHMCController | HMC Controller, in general, is responsible for translating the host protocol (AXI for example) to serial links protocol |
| ►CMemChecker | MemChecker |
| CByteTracker | The ByteTracker keeps track of transactions for the same byte – all outstanding reads, the completed reads (and what they observed) and write clusters (see WriteCluster) |
| CTransaction | Captures the lifetimes of read and write operations, and the values they consumed or produced respectively |
| CWriteCluster | Captures sets of writes where all writes are overlapping with at least one other write |
| ►CMemCheckerMonitor | Implements a MemChecker monitor, to be inserted between two ports |
| CMemCheckerMonitorSenderState | |
| CMonitorRequestPort | This is the request port of the communication monitor |
| CMonitorResponsePort | This is the response port of the communication monitor |
| ►CMemDelay | This abstract component provides a mechanism to delay packets |
| CRequestPort | |
| CResponsePort | |
| CSimpleMemDelay | Delay packets by a constant time |
| CRequestorInfo | Data about a specific requestor |
| CMultiLevelPageTable | |
| ►CNoncoherentXBar | A non-coherent crossbar connects a number of non-snooping memory-side ports and cpu_sides, and routes the request and response packets based on the address |
| CNoncoherentXBarRequestPort | Declaration of the crossbar memory-side port type, one will be instantiated for each of the CPU-side ports connecting to the crossbar |
| CNoncoherentXBarResponsePort | Declaration of the non-coherent crossbar CPU-side port type, one will be instantiated for each of the memory-side ports connecting to the crossbar |
| ►CMemCmd | |
| CCommandInfo | Structure that defines attributes and other data associated with a Command |
| ►CPacket | A Packet is used to encapsulate a transfer between two objects in the memory system (e.g., the L1 and L2 cache) |
| ►CPrintReqState | Object used to maintain state of a PrintReq |
| CLabelStackEntry | An entry in the label stack |
| CSenderState | A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a SimObject that sees the packet |
| ►CPacketQueue | A packet queue is a class that holds deferred packets and later sends them using the associated CPU-side port or memory-side port |
| CDeferredPacket | A deferred packet, buffered to transmit later |
| CReqPacketQueue | |
| CSnoopRespPacketQueue | |
| CRespPacketQueue | |
| ►CEmulationPageTable | |
| CEntry | |
| CPageTableTranslationGen | |
| CRequestPort | A RequestPort is a specialisation of a Port, which implements the default protocol for the three different level of transport functions |
| CMasterPort | |
| CResponsePort | A ResponsePort is a specialization of a port |
| CSlavePort | |
| CPortProxy | This object is a proxy for a port or other object which implements the functional response protocol, to be used for debug accesses |
| ►CPortTerminator | |
| CReqPort | Definition of the ReqPort class |
| CRespPort | Definition of the RespPort class |
| ►CBaseMemProbe | Base class for memory system probes accepting Packet instances |
| CPacketListener | |
| ►CMemFootprintProbe | Probe to track footprint of accessed memory Two granularity of footprint measurement i.e |
| CMemFootprintProbeStats | |
| CMemTraceProbe | |
| ►CStackDistProbe | |
| CStackDistProbeStats | |
| CAtomicRequestProtocol | |
| CAtomicResponseProtocol | |
| CFunctionalRequestProtocol | |
| CFunctionalResponseProtocol | |
| CTimingRequestProtocol | |
| CTimingResponseProtocol | |
| CQueuedResponsePort | A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module that wants to send request/responses from the flow control (retry mechanism) of the port |
| CQueuedRequestPort | The QueuedRequestPort combines two queues, a request queue and a snoop response queue, that both share the same port |
| CRequest | |
| CSETranslatingPortProxy | |
| ►CSerialLink | SerialLink is a simple variation of the Bridge class, with the ability to account for the latency of packet serialization |
| CDeferredPacket | A deferred packet stores a packet along with its scheduled transmission time |
| CSerialLinkRequestPort | Port on the side that forwards requests and receives responses |
| CSerialLinkResponsePort | The port on the side that receives requests and sends responses |
| ►CSnoopFilter | This snoop filter keeps track of which connected port has a particular line of data |
| CReqLookupResult | A request lookup must be followed by a call to finishRequest to inform the operation's success |
| CSnoopFilterStats | Statistics |
| CSnoopItem | Per cache line item tracking a bitmask of ResponsePorts who have an outstanding request to this line (requested) or already share a cache line with this address (holder) |
| ►CStackDistCalc | The stack distance calculator is a passive object that merely observes the addresses pass to it |
| CNode | Node which takes form of Leaf, INode or Root |
| ►CSysBridge | Each System object in gem5 is responsible for a set of RequestorIDs which identify different sources for memory requests within that System |
| CBridgingPort | |
| CPacketData | |
| CSysBridgeSenderState | |
| CSysBridgeSourcePort | |
| CSysBridgeTargetPort | |
| ►CThreadBridge | |
| CIncomingPort | |
| COutgoingPort | |
| CTokenRequestPort | |
| CTokenResponsePort | |
| CTokenManager | |
| CSimpleTimingPort | The simple timing port uses a queued port to implement recvFunctional and recvTimingReq through recvAtomic |
| CTranslatingPortProxy | This proxy attempts to translate virtual addresses using the TLBs |
| ►CTranslationGen | TranslationGen is a base class for a generator object which returns information about address translations over a range of virtual addresses |
| CRange | This structure represents a single, contiguous translation, or carries information about whatever fault might have happened while attempting it |
| CTranslationGenConstIterator | An iterator for pulling "Range" instances out of a TranslationGen |
| CFaultBase | |
| ►CBaseXBar | The base crossbar contains the common elements of the non-coherent and coherent crossbar |
| CLayer | A layer is an internal crossbar arbitration point with its own flow control |
| CReqLayer | |
| CRespLayer | |
| CSnoopRespLayer | |
| CEmbeddedPython | |
| CPybindSimObjectResolver | Resolve a SimObject name using the Pybind configuration |
| CPyEvent | PyBind wrapper for Events |
| CPybindModuleInit | |
| ►CClockDomain | The ClockDomain provides clock to group of clocked objects bundled under the same clock domain |
| CClockDomainStats | |
| CSrcClockDomain | The source clock domains provides the notion of a clock domain that is connected to a tunable clock source |
| CDerivedClockDomain | The derived clock domains provides the notion of a clock domain that is connected to a parent clock domain that can either be a source clock domain or a derived clock domain |
| CClocked | Helper class for objects that need to be clocked |
| CClockedObject | Extends the SimObject with a clock and accessor functions to relate ticks to the cycles of the object |
| ►CCxxConfigDirectoryEntry | Config details entry for a SimObject |
| CParamDesc | |
| CPortDesc | Similar to ParamDesc to describe ports |
| ►CCxxConfigParams | Base for peer classes of SimObjectParams derived classes with parameter modifying member functions |
| CAddToConfigDir | |
| CCxxConfigFileBase | Config file wrapper providing a common interface to CxxConfigManager |
| CCxxIniFile | CxxConfigManager interface for using .ini files |
| ►CCxxConfigManager | This class allows a config file to be read into gem5 (generating the appropriate SimObjects) from C++ |
| CException | Exception for instantiate/post-instantiate errors |
| CRenaming | Name substitution when instantiating any object whose name starts with fromPrefix |
| CSimObjectResolver | Class for resolving SimObject names to SimObjects usable by the checkpoint restore mechanism |
| CDebugBreakEvent | |
| CDrainManager | |
| CDrainable | Interface for objects that might require draining before checkpointing |
| ►CDVFSHandler | DVFS Handler class, maintains a list of all the domains it can handle |
| CUpdateEvent | Update performance level event, encapsulates all the required information for a future call to change a domain's performance level |
| CEmulatedDriver | EmulatedDriver is an abstract base class for fake SE-mode device drivers |
| CEventBase | Common base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions |
| CEvent | |
| ►CEventQueue | Queue of events sorted in time order |
| CScopedMigration | |
| CScopedRelease | |
| CEventManager | |
| CEventWrapper | |
| CEventFunctionWrapper | |
| CUnimpFault | |
| CSESyscallFault | |
| CReExec | |
| CSyscallRetryFault | |
| CGenericPageTableFault | |
| CGenericAlignmentFault | |
| CGenericHtmFailureFault | |
| CFDArray | |
| CFDEntry | Holds a single file descriptor mapping and that mapping's data for processes running in syscall emulation mode |
| CHBFDEntry | Extends the base class to include a host-backed file descriptor field that records the integer used to represent the file descriptor on the host and the file's flags |
| CFileFDEntry | Holds file descriptors for host-backed files; host-backed files are files which were opened on the physical machine where the simulation is running (probably the thing on/under your desk) |
| CPipeFDEntry | Holds the metadata needed to maintain the mappings for file descriptors allocated with the pipe() system calls and its variants |
| CDeviceFDEntry | Holds file descriptors needed to simulate devices opened with pseudo files (commonly with calls to ioctls) |
| CSocketFDEntry | |
| CFutexKey | FutexKey class defines an unique identifier for a particular futex in the system |
| CWaiterState | WaiterState defines internal state of a waiter thread |
| CFutexMap | FutexMap class holds a map of all futexes used in the system |
| ►CBaseGlobalEvent | Common base class for GlobalEvent and GlobalSyncEvent |
| CBarrierEvent | The base class for the local events that will synchronize threads to perform the global event |
| CBaseGlobalEventTemplate | Funky intermediate class to support CRTP so that we can have a common constructor to create the local events, even though the types of the local events are defined in the derived classes |
| ►CGlobalEvent | The main global event class |
| CBarrierEvent | |
| ►CGlobalSyncEvent | A special global event that synchronizes all threads and forces them to process asynchronously enqueued events |
| CBarrierEvent | |
| CGlobals | Container for serializing global variables (not associated with any serialized object) |
| CEmbeddedPyBind | |
| CKernelWorkload | |
| CLinearEquation | This class describes a linear equation with constant coefficients |
| CLinearSystem | |
| ►CMathExpr | |
| CNode | |
| COpSearch | |
| CMemPool | Class for handling allocation of physical pages in SE mode |
| CMemPools | |
| CMemState | This class holds the memory state for the Process class and all of its derived, architecture-specific children |
| ►CPort | Ports are used to interface objects to each other |
| CUnboundPortException | |
| CMathExprPowerModel | A Equation power model |
| CPowerModelState | A PowerModelState is an abstract class used as interface to get power figures out of SimObjects |
| ►CPowerModel | |
| CThermalProbeListener | Listener class to catch thermal events |
| CProbePointArg | ProbePointArg generates a point for the class of Arg |
| CThermalDomain | A ThermalDomain is used to group objects under that operate under the same temperature |
| CThermalEntity | An abstract class that represents any thermal entity which is used in the circuital thermal equivalent model |
| CThermalResistor | A ThermalResistor is used to model a thermal resistance between two thermal domains |
| CThermalCapacitor | A ThermalCapacitor is used to model a thermal capacitance between two thermal domains |
| CThermalReference | A ThermalReference is a thermal domain with fixed temperature |
| CThermalModel | |
| CThermalNode | A ThermalNode is used to connect thermal entities, such as resistors, capacitors, references and domains |
| ►CPowerDomain | The PowerDomain groups PowerState objects together to regulate their power states |
| CPowerDomainStats | |
| ►CPowerState | Helper class for objects that have power states |
| CPowerStateStats | |
| CProbeListenerObject | This class is a minimal wrapper around SimObject |
| CProbeListener | ProbeListener base class; here to simplify things like containers containing multiple types of ProbeListener |
| CProbePoint | ProbeListener base class; again used to simplify use of ProbePoints in containers and used as to define interface for adding removing listeners to the ProbePoint |
| CProbeManager | ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners with probe points |
| CProbeListenerArgBase | ProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i.e the notify method on specific type) |
| CProbeListenerArg | ProbeListenerArg generates a listener for the class of Arg and the class type T which is the class containing the function that notify will call |
| ►CProcess | |
| CLoader | Each instance of a Loader subclass will have a chance to try to load an object file when tryLoaders is called |
| CProxyPtrBuffer | |
| CConstProxyPtr | |
| CProxyPtr | |
| CProxyPtr< void, Proxy > | |
| CRedirectPath | RedirectPath stores a mapping from one 'appPath' to a vector of 'hostPath' |
| ►CRoot | |
| CRootStats | |
| CBasicSignal | |
| CSEWorkload | |
| CCheckpointIn | |
| ►CSerializable | Basic support for object serialization |
| CScopedCheckpointSection | |
| CParseParam | |
| CParseParam< T, decltype(to_number("", std::declval< T & >()), void())> | |
| CParseParam< bool > | |
| CParseParam< std::string > | |
| CShowParam | |
| CShowParam< T, std::enable_if_t< std::is_same_v< char, T >||std::is_same_v< unsigned char, T >||std::is_same_v< signed char, T > > > | |
| CShowParam< bool > | |
| CGlobalSimLoopExitEvent | |
| CLocalSimLoopExitEvent | |
| CCountedExitEvent | |
| CSimObject | Abstract superclass for simulation objects |
| CSimObjectResolver | Base class to wrap object resolving functionality |
| CSimulatorThreads | |
| CDescheduleDeleter | |
| CSubSystem | The SubSystem simobject does nothing, it is just a container for other simobjects used by the configuration system |
| CGenericSyscallABI | |
| CGenericSyscallABI64 | |
| ►CGenericSyscallABI32 | |
| CIsWide | |
| CIsWide< T, std::enable_if_t<(sizeof(T) > sizeof(UintPtr))> > | |
| CSyscallDesc | This class provides the wrapper interface for the system call implementations which are defined in the sim/syscall_emul files and bound to the ISAs in the architecture specific code (i.e |
| CSyscallDescABI | |
| CSyscallDescTable | |
| CBaseBufferArg | Base class for BufferArg and TypedBufferArg, Not intended to be used directly |
| CBufferArg | BufferArg represents an untyped buffer in target user space that is passed by reference to an (emulated) system call |
| CTypedBufferArg | TypedBufferArg is a class template; instances of this template represent typed buffers in target user space that are passed by reference to an (emulated) system call |
| CSyscallReturn | This class represents the return value from an emulated system call, including any errno setting |
| ►CSystem | |
| CSystemPort | Private class for the system port which is only used as a requestor for debug access and for non-structural entities that do not have a port of their own |
| ►CThreads | |
| Cconst_iterator | |
| CThread | |
| CTicked | Ticked attaches gem5's event queue/scheduler to evaluate calls and provides a start/stop interface to ticking |
| CTickedObject | TickedObject attaches Ticked to ClockedObject and can be used as a base class where ticked operation |
| ►CVMA | |
| CMappedFileBuffer | MappedFileBuffer is a wrapper around a region of host memory backed by a file |
| ►CVoltageDomain | A VoltageDomain is used to group clock domains that operate under the same voltage |
| CVoltageDomainStats | |
| ►CWorkload | |
| ►CWorkloadStats | |
| CInstStats | |
| CStubWorkload | |
| ►COutgoingRequestBridge | |
| COutgoingRequestPort | |
| CSSTResponderInterface | |
| ►NGem5SystemC | |
| CTlmSenderState | |
| CGem5Extension | |
| CAtomicExtension | |
| CControlExtension | |
| CMemoryManager | |
| ►Nsc_core | |
| Csc_buffer | |
| Csc_in | |
| Csc_clock | |
| Csc_event_queue_if | |
| Csc_event_queue | |
| Csc_fifo | |
| Csc_fifo_in | |
| Csc_fifo_nonblocking_in_if | |
| Csc_fifo_blocking_in_if | |
| Csc_fifo_in_if | |
| Csc_fifo_out | |
| Csc_fifo_nonblocking_out_if | |
| Csc_fifo_blocking_out_if | |
| Csc_fifo_out_if | |
| Csc_in< bool > | |
| Csc_in< sc_dt::sc_logic > | |
| Csc_in_resolved | |
| Csc_in_rv | |
| Csc_inout | |
| Csc_inout< bool > | |
| Csc_inout< sc_dt::sc_logic > | |
| Csc_inout_resolved | |
| Csc_inout_rv | |
| Csc_mutex | |
| Csc_mutex_if | |
| Csc_out | |
| Csc_out_resolved | |
| Csc_out_rv | |
| Csc_semaphore | |
| Csc_semaphore_if | |
| Csc_signal | |
| Csc_signal< bool, WRITER_POLICY > | |
| Csc_signal< sc_dt::sc_logic, WRITER_POLICY > | |
| Csc_signal_in_if | |
| Csc_signal_in_if< bool > | |
| Csc_signal_in_if< sc_dt::sc_logic > | |
| Csc_signal_write_if | |
| Csc_signal_inout_if | |
| Csc_signal_resolved | |
| Csc_signal_rv | |
| Csc_attr_base | |
| Csc_attribute | |
| Csc_attr_cltn | |
| Csc_event_and_list | |
| Csc_event_or_list | |
| Csc_event_and_expr | |
| Csc_event_or_expr | |
| Csc_event | |
| Csc_event_finder | |
| Csc_event_finder_t | |
| Csc_export_base | |
| Csc_export | |
| Csc_interface | |
| Csc_join | |
| Csc_bind_proxy | |
| Csc_module | |
| Csc_module_name | |
| Csc_object | |
| Csc_trace_params | |
| Csc_port_base | |
| Csc_port_b | |
| Csc_port | |
| Csc_prim_channel | |
| Csc_unwind_exception | |
| Csc_process_b | |
| Csc_curr_proc_info | |
| Csc_process_handle | |
| Csc_sensitive | |
| Csc_simcontext | |
| ►Csc_spawn_options | |
| CReset | |
| Csc_time | |
| Csc_time_tuple | |
| Csc_mempool | |
| Csc_mpobject | |
| Csc_byte_heap | |
| Csc_vpool | |
| Csc_user | |
| Csc_report | |
| Csc_report_handler | |
| Csc_trace_file | |
| Csc_vector_assembly | |
| Csc_vector | |
| Csc_vector_base | |
| Csc_direct_access | |
| Csc_member_access | |
| ►Csc_vector_iter | |
| CSelectIter | |
| CSelectIter< const U > | |
| Csc_int_part_if | |
| Csc_signal_in_if< sc_dt::sc_int< W > > | |
| Csc_int_sigref | |
| Csc_signal< sc_dt::sc_int< W > > | |
| Csc_in< sc_dt::sc_int< W > > | |
| Csc_inout< sc_dt::sc_int< W > > | |
| Csc_out< sc_dt::sc_int< W > > | |
| Csc_signed_part_if | |
| Csc_signal_in_if< sc_dt::sc_bigint< W > > | |
| Csc_signed_sigref | |
| Csc_signal< sc_dt::sc_bigint< W > > | |
| Csc_in< sc_dt::sc_bigint< W > > | |
| Csc_inout< sc_dt::sc_bigint< W > > | |
| Csc_out< sc_dt::sc_bigint< W > > | |
| Csc_uint_part_if | |
| Csc_signal_in_if< sc_dt::sc_uint< W > > | |
| Csc_uint_sigref | |
| Csc_signal< sc_dt::sc_uint< W > > | |
| Csc_in< sc_dt::sc_uint< W > > | |
| Csc_inout< sc_dt::sc_uint< W > > | |
| Csc_out< sc_dt::sc_uint< W > > | |
| Csc_unsigned_part_if | |
| Csc_signal_in_if< sc_dt::sc_biguint< W > > | |
| Csc_unsigned_sigref | |
| Csc_signal< sc_dt::sc_biguint< W > > | |
| Csc_in< sc_dt::sc_biguint< W > > | |
| Csc_inout< sc_dt::sc_biguint< W > > | |
| Csc_out< sc_dt::sc_biguint< W > > | |
| ►Nsc_dp | |
| Csc_barrier | |
| ►Nsc_dt | |
| Cword_list | |
| Cscfx_rep_node | |
| Cword_short | |
| Csc_lv | |
| Csc_bit | |
| Csc_bitref_conv_r | |
| Csc_bitref_r | |
| Csc_bitref | |
| Csc_subref_r | |
| Csc_subref | |
| Csc_concref_r | |
| Csc_concref | |
| Csc_bitref_conv_r< T, sc_proxy_traits< sc_bv_base > > | |
| Csc_bv | |
| Csc_bv_base | |
| Csc_logic | |
| Csc_lv_base | |
| Csc_proxy | |
| Csc_proxy_traits | |
| Csc_proxy_traits< sc_bv_base > | |
| Csc_proxy_traits< sc_lv_base > | |
| Csc_proxy_traits< sc_bitref_r< X > > | |
| Csc_proxy_traits< sc_bitref< X > > | |
| Csc_proxy_traits< sc_subref_r< X > > | |
| Csc_proxy_traits< sc_subref< X > > | |
| Csc_proxy_traits< sc_proxy< X > > | |
| Csc_mixed_proxy_traits_helper | |
| Csc_mixed_proxy_traits_helper< X, X > | |
| Csc_proxy_traits< sc_concref_r< X, Y > > | |
| Csc_proxy_traits< sc_concref< X, Y > > | |
| Csc_global | |
| Csc_context | |
| Csc_without_context | |
| Csc_fix | |
| Csc_fix_fast | |
| Csc_fixed | |
| Csc_fixed_fast | |
| Csc_fxcast_switch | |
| Csc_fxnum_bitref | |
| Csc_fxnum_fast_bitref | |
| Csc_fxnum_subref | |
| Csc_fxnum_fast_subref | |
| Csc_fxnum | |
| Csc_fxnum_fast | |
| Csc_fxnum_observer | |
| Csc_fxnum_fast_observer | |
| Csc_fxtype_params | |
| Csc_fxval | |
| Csc_fxval_fast | |
| Csc_fxval_observer | |
| Csc_fxval_fast_observer | |
| Csc_ufix | |
| Csc_ufix_fast | |
| Csc_ufixed | |
| Csc_ufixed_fast | |
| Cieee_double | |
| Cscfx_ieee_double | |
| Cieee_float | |
| Cscfx_ieee_float | |
| Cscfx_mant | |
| Cscfx_mant_ref | |
| Cscfx_params | |
| Cscfx_pow10 | |
| Cscfx_index | |
| Cscfx_rep | |
| Cscfx_string | |
| Csc_bigint | |
| Csc_biguint | |
| Csc_int | |
| Csc_int_bitref_r | |
| Csc_int_bitref | |
| Csc_int_subref_r | |
| Csc_int_subref | |
| Csc_int_base | |
| Csc_length_param | |
| Csc_signed_bitref_r | |
| Csc_signed_bitref | |
| Csc_signed_subref_r | |
| Csc_signed_subref | |
| Csc_signed | |
| Csc_uint | |
| Csc_uint_bitref_r | |
| Csc_uint_bitref | |
| Csc_uint_subref_r | |
| Csc_uint_subref | |
| Csc_uint_base | |
| Csc_unsigned_bitref_r | |
| Csc_unsigned_bitref | |
| Csc_unsigned_subref_r | |
| Csc_unsigned_subref | |
| Csc_unsigned | |
| Csc_concatref | |
| Csc_concat_bool | |
| Csc_value_base | |
| Csc_generic_base | |
| ►Nsc_gem5 | |
| CClockTick | |
| CChannel | |
| CEvent | |
| CKernel | |
| CListNode | |
| CNodeList | |
| CUniqueNameGen | |
| CModule | |
| CObject | |
| ►CPort | |
| CBinding | |
| CSensitivity | |
| CUnwindExceptionReset | |
| CUnwindExceptionKill | |
| CBuiltinExceptionWrapper | |
| CScHalt | |
| CProcess | |
| CReset | |
| CMethod | |
| ►CThread | |
| CContext | |
| CCThread | |
| CPythonInitFunc | |
| CScMainFiber | |
| CScEvent | |
| ►CScheduler | |
| CTimeSlot | |
| CSensitivity | |
| CDynamicSensitivity | |
| CStaticSensitivity | |
| CSensitivityEvent | |
| CSensitivityEvents | |
| CStaticSensitivityEvent | |
| CStaticSensitivityInterface | |
| CStaticSensitivityPort | |
| CStaticSensitivityExport | |
| CStaticSensitivityFinder | |
| CDynamicSensitivityEvent | |
| CDynamicSensitivityEventOrList | |
| CDynamicSensitivityEventAndList | |
| CScSignalBase | |
| CScSignalBaseBinary | |
| CScSignalBasePicker | |
| CScSignalBasePicker< bool > | |
| CScSignalBasePicker< sc_dt::sc_logic > | |
| CWriteChecker | |
| CWriteChecker< sc_core::SC_ONE_WRITER > | |
| CWriteChecker< sc_core::SC_MANY_WRITERS > | |
| CScSignalBaseT | |
| CScSignalBinary | |
| CInternalScEvent | |
| CProcessFuncWrapper | |
| CProcessMemberFuncWrapper | |
| CExceptionWrapperBase | |
| CExceptionWrapper | |
| CProcessObjFuncWrapper | |
| CProcessObjRetFuncWrapper | |
| CTraceValFxnumBase | |
| Cenable_if | |
| Cenable_if< true, T > | |
| Cremove_const | |
| Cremove_const< const T > | |
| Cis_same | |
| Cis_same< T, T > | |
| Cis_const | |
| Cis_const< const T > | |
| Cis_more_const | |
| Cspecial_result | |
| Cremove_special_fptr | |
| Cremove_special_fptr< special_result &(*)(T)> | |
| CScPortWrapper | |
| CScInterfaceWrapper | |
| CScExportWrapper | |
| CGem5ToTlmBridgeBase | |
| ►CGem5ToTlmBridge | |
| CBridgeResponsePort | |
| CTlmToGem5BridgeBase | |
| ►CTlmToGem5Bridge | |
| CBridgeRequestPort | |
| CTlmInitiatorBaseWrapper | |
| CTlmTargetBaseWrapper | |
| CReportMsgInfo | |
| CReportSevInfo | |
| CDefaultReportMessages | |
| CTraceValBase | |
| CTraceVal | |
| CTraceVal<::sc_core::sc_signal_in_if< T >, Base > | |
| CTraceVal<::sc_core::sc_event, Base > | |
| CTraceVal<::sc_dt::sc_fxnum, Base > | |
| CTraceVal<::sc_dt::sc_fxnum_fast, Base > | |
| CTraceFile | |
| CVcdTraceValBase | |
| CVcdTraceVal | |
| CVcdTraceValBool | |
| CVcdTraceValFloat | |
| CVcdTraceValScLogic | |
| CVcdTraceValFinite | |
| CVcdTraceValLogic | |
| CVcdTraceValFxval | |
| CVcdTraceValFxnum | |
| CVcdTraceValEvent | |
| CVcdTraceValTime | |
| CVcdTraceValInt | |
| CVcdTraceScope | |
| CVcdTraceFile | |
| ►Nstd | Overload hash function for BasicBlockRange type |
| Chash< gem5::ArmISA::MiscRegNum32 > | |
| Chash< gem5::ArmISA::MiscRegNum64 > | |
| Chash< gem5::PowerISA::ExtMachInst > | |
| Chash< gem5::X86ISA::ExtMachInst > | |
| Chash< gem5::BitUnionType< T > > | |
| Chash< gem5::ChannelAddr > | |
| Chash< gem5::RegId > | |
| Chash< gem5::BasicBlockRange > | |
| Cvector | STL vector class |
| Cdeque | STL deque class |
| Clist | STL list class |
| Cpair | STL pair class |
| Chash< gem5::ruby::MachineID > | |
| Chash< gem5::FutexKey > | The unordered_map structure needs the parenthesis operator defined for std::hash if a user defined key is used |
| ►Ntlm | |
| Ctlm_analysis_fifo | |
| Ctlm_analysis_if | |
| Ctlm_delayed_analysis_if | |
| Ctlm_analysis_port | |
| Ctlm_analysis_triple | |
| Ctlm_write_if | |
| Ctlm_delayed_write_if | |
| Ctlm_transport_to_master | |
| Ctlm_slave_to_transport | |
| Ccircular_buffer | |
| Ctlm_fifo | |
| Ctlm_put_get_imp | |
| Ctlm_master_imp | |
| Ctlm_slave_imp | |
| Ctlm_req_rsp_channel | |
| Ctlm_transport_channel | |
| Ctlm_transport_if | |
| Ctlm_blocking_get_if | |
| Ctlm_blocking_put_if | |
| Ctlm_nonblocking_get_if | |
| Ctlm_nonblocking_put_if | |
| Ctlm_get_if | |
| Ctlm_put_if | |
| Ctlm_blocking_peek_if | |
| Ctlm_nonblocking_peek_if | |
| Ctlm_peek_if | |
| Ctlm_blocking_get_peek_if | |
| Ctlm_nonblocking_get_peek_if | |
| Ctlm_get_peek_if | |
| Ctlm_fifo_debug_if | |
| Ctlm_fifo_put_if | |
| Ctlm_fifo_get_if | |
| Ctlm_fifo_config_size_if | |
| Ctlm_blocking_master_if | |
| Ctlm_blocking_slave_if | |
| Ctlm_nonblocking_master_if | |
| Ctlm_nonblocking_slave_if | |
| Ctlm_master_if | |
| Ctlm_slave_if | |
| Ctlm_tag | |
| Ctlm_event_finder_t | |
| Ctlm_nonblocking_get_port | |
| Ctlm_nonblocking_peek_port | |
| Ctlm_nonblocking_put_port | |
| Ctlm_array | |
| Ctlm_endian_context_pool | |
| Ctlm_endian_context | |
| Ctlm_bool | |
| Ctlm_mm_interface | |
| Ctlm_extension_base | |
| Ctlm_extension | |
| Ctlm_generic_payload | |
| Ctlm_phase | |
| Ctlm_dmi | |
| Ctlm_fw_nonblocking_transport_if | |
| Ctlm_bw_nonblocking_transport_if | |
| Ctlm_blocking_transport_if | |
| Ctlm_fw_direct_mem_if | |
| Ctlm_bw_direct_mem_if | |
| Ctlm_transport_dbg_if | |
| Ctlm_base_protocol_types | |
| Ctlm_fw_transport_if | |
| Ctlm_bw_transport_if | |
| Ctlm_global_quantum | |
| Ctlm_base_socket_if | |
| Ctlm_base_initiator_socket_b | |
| Ctlm_base_target_socket_b | |
| Ctlm_base_target_socket | |
| Ctlm_base_initiator_socket | |
| Ctlm_initiator_socket | |
| Ctlm_target_socket | |
| ►Ntlm_utils | |
| Cconvenience_socket_base | |
| Csimple_socket_base | |
| Cpassthrough_socket_base | |
| Cmulti_socket_base | |
| Cconvenience_socket_cb_holder | |
| Cinstance_specific_extension | |
| Cinstance_specific_extension_carrier | |
| Cispex_base | |
| Cinstance_specific_extensions_per_accessor | |
| Cinstance_specific_extension_container | |
| Cinstance_specific_extension_accessor | |
| Cmulti_passthrough_initiator_socket | |
| Cmulti_passthrough_initiator_socket_optional | |
| Cmulti_passthrough_target_socket | |
| Cmulti_passthrough_target_socket_optional | |
| Cfn_container | |
| Ccallback_binder_fw | |
| Ccallback_binder_bw | |
| Cmulti_init_base_if | |
| Cmulti_init_base | |
| Cmulti_target_base_if | |
| Cmulti_target_base | |
| Cmulti_to_multi_bind_base | |
| ►Cpassthrough_target_socket_b | |
| Cprocess | |
| Cpassthrough_target_socket | |
| Cpassthrough_target_socket_optional | |
| ►Cpassthrough_target_socket_tagged_b | |
| Cprocess | |
| Cpassthrough_target_socket_tagged | |
| Cpassthrough_target_socket_tagged_optional | |
| ►Ctime_ordered_list | |
| Celement | |
| ►Cpeq_with_cb_and_phase | An event queue that can contain any number of pending notifications |
| Cdelta_list | |
| Cpeq_with_get | |
| ►Csimple_initiator_socket_b | |
| Cprocess | |
| Csimple_initiator_socket | |
| Csimple_initiator_socket_optional | |
| ►Csimple_initiator_socket_tagged_b | |
| Cprocess | |
| Csimple_initiator_socket_tagged | |
| Csimple_initiator_socket_tagged_optional | |
| ►Csimple_target_socket_b | |
| Cbw_process | |
| ►Cfw_process | |
| Cmm_end_event_ext | |
| Cprocess_handle_class | |
| Cprocess_handle_list | |
| Csimple_target_socket | |
| Csimple_target_socket_optional | |
| ►Csimple_target_socket_tagged_b | |
| Cbw_process | |
| ►Cfw_process | |
| Cmm_end_event_ext | |
| Cprocess_handle_class | |
| Cprocess_handle_list | |
| Csimple_target_socket_tagged | |
| Csimple_target_socket_tagged_optional | |
| Ctlm_quantumkeeper | |
| Cinstance_specific_extension_container_pool | |
| Ca_new_struct | |
| CAccess | |
| Cadapt_ext2gp | |
| Cadapt_gp2ext | |
| Carr_struct1 | |
| Carr_struct2 | |
| Cataparams | |
| Cb_new_struct | |
| CBackingStore | |
| CBitUnionData | |
| CBlock | |
| CCheckpointInFixture | |
| CCoeff8 | |
| CCoeff8x8 | |
| CCompressed | |
| CCoreDecouplingLTInitiator | |
| CDuelingMonitorTest | |
| CDummyInfo | |
| CExplicitATTarget | |
| CExplicitLTTarget | |
| ►CExtensionPool | |
| Centry | |
| Cfun | |
| Chsa_agent_dispatch_packet_s | Agent dispatch packet |
| Chsa_agent_s | Struct containing an opaque handle to an agent, a device that participates in the HSA memory model |
| Chsa_barrier_and_packet_s | Barrier-AND packet |
| Chsa_barrier_or_packet_s | Barrier-OR packet |
| Chsa_cache_s | Cache handle |
| Chsa_callback_data_s | Application data handle that is passed to the serialization and deserialization functions |
| Chsa_code_object_reader_s | Code object reader handle |
| Chsa_code_object_s | Struct containing an opaque handle to a code object, which contains ISA for finalized kernels and indirect functions together with information about the global or readonly segment variables they reference |
| Chsa_code_symbol_s | Code object symbol handle |
| Chsa_dim3_s | Three-dimensional coordinate |
| Chsa_executable_s | Struct containing an opaque handle to an executable, which contains ISA for finalized kernels and indirect functions together with the allocated global or readonly segment variables they reference |
| Chsa_executable_symbol_s | Executable symbol handle |
| Chsa_isa_s | Instruction set architecture |
| Chsa_kernel_dispatch_packet_s | AQL kernel dispatch packet |
| Chsa_loaded_code_object_s | Loaded code object handle |
| Chsa_queue_s | User mode queue |
| Chsa_region_s | A memory region represents a block of virtual memory with certain properties |
| Chsa_signal_group_s | Group of signals |
| Chsa_signal_s | Signal handle |
| Chsa_wavefront_s | Wavefront handle |
| CHUFFMTBL_ENTRY | |
| Cinstr | |
| CLinkedFiber | |
| CLoggingFixture | Temporarily redirects cerr to gtestLogOutput |
| CMatrix64x12 | |
| Cmemory | |
| CMipsAccess | |
| ►Cmm | |
| Caccess | |
| CMockListenSocket | |
| CMSICAP | Defines the MSI Capability register and its associated bitfields for the a PCI/PCIe device |
| CMSIX | Defines the MSI-X Capability register and its associated bitfields for a PCIe device |
| CMSIXCAP | |
| CMSIXPbaEntry | |
| CMSIXTable | |
| ►CMultiSocketSimpleSwitchAT | |
| CBTag | |
| CConnectionInfo | |
| CinternalPEQTypes | |
| Cmy_extended_payload_types | |
| Cmy_extension | |
| Coperand | |
| Cpipeline | |
| CPMCAP | Defines the Power Management capability register and all its associated bitfields for a PCIe device |
| CProtoInputStream | A ProtoInputStream wraps a coded stream, potentially with decompression, based on looking at the file name |
| CProtoOutputStream | A ProtoOutputStream wraps a coded stream, potentially with compression, based on looking at the file name |
| CProtoStream | A ProtoStream provides the shared functionality of the input and output streams |
| CPXCAP | Defines the PCI Express capability register and its associated bitfields for a PCIe device |
| ►CQTIsaac | |
| Crandctx | |
| ►CRegisterBankTest | |
| CAccess | |
| CTestReg | |
| CTestRegBank | |
| CRegisterBufTest | |
| CRegisterLBufTest | |
| CRegisterRaoTest | |
| CRegisterRazTest | |
| Crgb_t | |
| CSerializableFixture | A fixture to handle checkpoint in and out variables, as well as the testing of the temporary directory |
| CSerializableType | |
| CSimpleAddressMap | Simple address map implementation for the generic protocol |
| ►CSimpleATInitiator1 | |
| CMyTransaction | |
| CSimplePool | |
| ►CSimpleATInitiator2 | |
| CMyTransaction | |
| CSimplePool | |
| CSimpleATTarget1 | |
| CSimpleATTarget2 | |
| ►CSimpleBusAT | |
| CConnectionInfo | |
| CSimpleBusLT | |
| CSimpleInitiatorWrapper | |
| CSimpleLTInitiator1 | TLM definitions |
| CSimpleLTInitiator1_dmi | |
| CSimpleLTInitiator2 | |
| CSimpleLTInitiator2_dmi | |
| CSimpleLTInitiator3 | |
| CSimpleLTInitiator3_dmi | |
| CSimpleLTInitiator_ext | |
| CSimpleLTTarget1 | |
| CSimpleLTTarget2 | |
| CSimpleLTTarget_ext | |
| CSimpleTargetWrapper | |
| Cstack_el | |
| Cstage1_2 | |
| CSwitchingFiber | |
| Ctest | |
| CTestABI | |
| CTestABI_1D | |
| CTestABI_2D | |
| CTestABI_Prepare | |
| ►CTestABI_TcInit | |
| CState | |
| Ctestbench | |
| CTestInfo | |
| CTestPort | |
| CTestProxy | |
| CTestTranslationGen | |
| Ctop | |
| CTrieTestData | |
| CTwoDifferentVecPredRegsBase | |
| CTwoDifferentVecRegs | |
| CTypedRegisterTest | |
| CValueSamples | A pair of value and its number of samples, used for sampling |
| Cvring | |
| Cvring_avail | |
| Cvring_desc | |
| Cvring_used | |
| Cvring_used_elem | |
| Cwriter | |
