gem5
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arch
arm
reg_abi.cc
Go to the documentation of this file.
1
/*
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* Copyright 2020 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/arm/reg_abi.hh
"
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#include "
arch/arm/regs/int.hh
"
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namespace
gem5
32
{
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34
namespace
ArmISA
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{
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const
std::vector<RegId>
RegABI32::ArgumentRegs
= {
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int_reg::R0
,
int_reg::R1
,
int_reg::R2
,
int_reg::R3
,
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int_reg::R4
,
int_reg::R5
,
int_reg::R6
40
};
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const
std::vector<RegId>
RegABI64::ArgumentRegs
= {
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int_reg::X0
,
int_reg::X1
,
int_reg::X2
,
int_reg::X3
,
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int_reg::X4
,
int_reg::X5
,
int_reg::X6
44
};
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}
// namespace ArmISA
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}
// namespace gem5
reg_abi.hh
int.hh
std::vector
STL vector class.
Definition
stl.hh:37
gem5::ArmISA::int_reg::X0
constexpr RegId X0
Definition
int.hh:240
gem5::ArmISA::int_reg::R4
constexpr RegId R4
Definition
int.hh:190
gem5::ArmISA::int_reg::X6
constexpr RegId X6
Definition
int.hh:246
gem5::ArmISA::int_reg::R6
constexpr RegId R6
Definition
int.hh:192
gem5::ArmISA::int_reg::X1
constexpr RegId X1
Definition
int.hh:241
gem5::ArmISA::int_reg::X3
constexpr RegId X3
Definition
int.hh:243
gem5::ArmISA::int_reg::X4
constexpr RegId X4
Definition
int.hh:244
gem5::ArmISA::int_reg::R3
constexpr RegId R3
Definition
int.hh:189
gem5::ArmISA::int_reg::R5
constexpr RegId R5
Definition
int.hh:191
gem5::ArmISA::int_reg::X2
constexpr RegId X2
Definition
int.hh:242
gem5::ArmISA::int_reg::R2
constexpr RegId R2
Definition
int.hh:188
gem5::ArmISA::int_reg::R1
constexpr RegId R1
Definition
int.hh:187
gem5::ArmISA::int_reg::X5
constexpr RegId X5
Definition
int.hh:245
gem5::ArmISA::int_reg::R0
constexpr RegId R0
Definition
int.hh:186
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition
gpu_translation_state.hh:38
gem5::ArmISA::RegABI32::ArgumentRegs
static const std::vector< RegId > ArgumentRegs
Definition
reg_abi.hh:44
gem5::ArmISA::RegABI64::ArgumentRegs
static const std::vector< RegId > ArgumentRegs
Definition
reg_abi.hh:49
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