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dev
amdgpu
sdma_mmio.hh
Go to the documentation of this file.
1
/*
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* Copyright (c) 2021 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DEV_AMDGPU_SDMA_MMIO_HH__
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#define __DEV_AMDGPU_SDMA_MMIO_HH__
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#define mmSDMA_GFX_RB_CNTL 0x0080
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#define mmSDMA_GFX_RB_BASE 0x0081
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#define mmSDMA_GFX_RB_BASE_HI 0x0082
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#define mmSDMA_GFX_RB_RPTR_ADDR_HI 0x0088
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#define mmSDMA_GFX_RB_RPTR_ADDR_LO 0x0089
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#define mmSDMA_GFX_DOORBELL 0x0092
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#define mmSDMA_GFX_DOORBELL_OFFSET 0x00ab
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#define mmSDMA_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2
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#define mmSDMA_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3
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#define mmSDMA_PAGE_RB_CNTL 0x00e0
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#define mmSDMA_PAGE_RB_BASE 0x00e1
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#define mmSDMA_PAGE_RB_RPTR_ADDR_HI 0x00e8
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#define mmSDMA_PAGE_RB_RPTR_ADDR_LO 0x00e9
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#define mmSDMA_PAGE_DOORBELL 0x00f2
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#define mmSDMA_PAGE_DOORBELL_OFFSET 0x010b
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#define mmSDMA_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113
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#endif
// __DEV_AMDGPU_SDMA_MMIO_HH__
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