cpu.cc

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#include "arch/arm/fastmodel/iris/cpu.hh"
 
#include "arch/arm/fastmodel/iris/thread_context.hh"
#include "cpu/thread_context.hh"
#include "scx/scx.h"
#include "sim/serialize.hh"
 
namespace gem5
{
 
namespace Iris
{
 
BaseCPU::BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs) :
    gem5::BaseCPU::BaseCPU(params), evs(_evs),
    evs_base_cpu(dynamic_cast<Iris::BaseCpuEvs *>(_evs))
{
    panic_if(!evs_base_cpu, "EVS should be of type BaseCpuEvs");
 
    // Make sure fast model knows we're using debugging mechanisms to control
    // the simulation, and it shouldn't shut down if simulation time stops
    // for some reason. Despite the misleading name, this doesn't start a CADI
    // server because it's first parameter is false.
    scx::scx_start_cadi_server(false, false, true);
}
 
BaseCPU::~BaseCPU()
{
    for (auto &tc: threadContexts)
        delete tc;
    threadContexts.clear();
}
 
void
BaseCPU::wakeup(ThreadID tid)
{
    auto *tc = threadContexts.at(tid);
    if (tc->status() == gem5::ThreadContext::Suspended) {
        tc->activate();
    }
}
 
Counter
BaseCPU::totalInsts() const
{
    Counter count = 0;
    for (auto *tc: threadContexts)
        count += tc->getCurrentInstCount();
    return count;
}
 
void
BaseCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
{
    gem5::serialize(*threadContexts[tid], cp);
}
 
} // namespace Iris
} // namespace gem5