gem5
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arch
power
faults.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2021 IBM Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/power/faults.hh
"
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#include <csignal>
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#include "
cpu/base.hh
"
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#include "
cpu/thread_context.hh
"
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#include "
sim/system.hh
"
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namespace
gem5
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{
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namespace
PowerISA
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{
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void
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UnimplementedOpcodeFault::invoke
(
ThreadContext
*tc,
const
StaticInstPtr
&inst)
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{
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if
(! tc->
getSystemPtr
()->
trapToGdb
(GDBSignal::ILL, tc->
contextId
()) ) {
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panic
(
"Unimplemented opcode encountered at virtual address %#x\n"
,
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tc->
pcState
().
instAddr
());
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}
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}
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void
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AlignmentFault::invoke
(
ThreadContext
*tc,
const
StaticInstPtr
&inst)
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{
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if
(! tc->
getSystemPtr
()->
trapToGdb
(GDBSignal::BUS, tc->
contextId
()) ) {
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panic
(
"Alignment fault when accessing virtual address %#x\n"
,
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vaddr
);
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}
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}
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void
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TrapFault::invoke
(
ThreadContext
*tc,
const
StaticInstPtr
&inst)
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{
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if
(! tc->
getSystemPtr
()->
trapToGdb
(GDBSignal::TRAP, tc->
contextId
()) ) {
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panic
(
"Trap encountered at virtual address %#x\n"
,
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tc->
pcState
().
instAddr
());
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}
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}
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}
// namespace PowerISA
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}
// namespace gem5
faults.hh
gem5::PCStateBase::instAddr
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition
pcstate.hh:108
gem5::PowerISA::AlignmentFault::vaddr
Addr vaddr
Definition
faults.hh:85
gem5::PowerISA::AlignmentFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition
faults.cc:53
gem5::PowerISA::TrapFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition
faults.cc:62
gem5::PowerISA::UnimplementedOpcodeFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition
faults.cc:44
gem5::System::trapToGdb
bool trapToGdb(GDBSignal signal, ContextID ctx_id) const
Definition
system.cc:407
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
thread_context.hh:89
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
base.hh
thread_context.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition
logging.hh:220
gem5::PowerISA
Definition
decoder.cc:35
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition
binary32.hh:36
gem5::StaticInstPtr
RefCountingPtr< StaticInst > StaticInstPtr
Definition
static_inst_fwd.hh:38
system.hh
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