gem5 [DEVELOP-FOR-25.1]
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interrupts.cc
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1/*
2 * Copyright (c) 2009, 2012-2013, 2016, 2019, 2023 Arm Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include "arch/arm/interrupts.hh"
39
40#include "arch/arm/system.hh"
41#include "params/ArmInterrupts.hh"
42
43namespace gem5
44{
45
50
51bool
52ArmISA::Interrupts::takeInt32(InterruptTypes int_type) const
53{
54 InterruptMask mask;
55 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
56 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);;
57 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
58 ExceptionLevel el = currEL(tc);
59 bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
60 bool is_secure = isSecure(tc);
61
62 switch(int_type) {
63 case INT_FIQ:
64 cpsr_mask_bit = cpsr.f;
65 scr_routing_bit = scr.fiq;
66 scr_fwaw_bit = scr.fw;
67 hcr_mask_override_bit = hcr.fmo;
68 break;
69 case INT_IRQ:
70 cpsr_mask_bit = cpsr.i;
71 scr_routing_bit = scr.irq;
72 scr_fwaw_bit = 1;
73 hcr_mask_override_bit = hcr.imo;
74 break;
75 case INT_ABT:
76 cpsr_mask_bit = cpsr.a;
77 scr_routing_bit = scr.ea;
78 scr_fwaw_bit = scr.aw;
79 hcr_mask_override_bit = hcr.amo;
80 break;
81 default:
82 panic("Unhandled interrupt type!");
83 }
84
85 if (hcr.tge)
86 hcr_mask_override_bit = 1;
87
88 if (!scr_routing_bit) {
89 // SCR IRQ == 0
90 if (!hcr_mask_override_bit)
91 mask = INT_MASK_M;
92 else {
93 if (!is_secure && (el == EL0 || el == EL1))
94 mask = INT_MASK_T;
95 else
96 mask = INT_MASK_M;
97 }
98 } else {
99 // SCR IRQ == 1
100 if ((!is_secure) &&
101 (hcr_mask_override_bit ||
102 (!scr_fwaw_bit && !hcr_mask_override_bit)))
103 mask = INT_MASK_T;
104 else
105 mask = INT_MASK_M;
106 }
107 return ((mask == INT_MASK_T) ||
108 ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
109 (mask != INT_MASK_P);
110}
111
112
113bool
114ArmISA::Interrupts::takeInt64(InterruptTypes int_type) const
115{
116 InterruptMask mask;
117 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
118 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);;
119 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
120 ExceptionLevel el = currEL(tc);
121 bool cpsr_mask_bit, scr_routing_bit, hcr_mask_override_bit;
122 bool is_secure = isSecureBelowEL3(tc);
123
124 switch(int_type) {
125 case INT_FIQ:
126 cpsr_mask_bit = cpsr.f;
127 scr_routing_bit = scr.fiq;
128 hcr_mask_override_bit = hcr.fmo;
129 break;
130 case INT_IRQ:
131 cpsr_mask_bit = cpsr.i;
132 scr_routing_bit = scr.irq;
133 hcr_mask_override_bit = hcr.imo;
134 break;
135 case INT_ABT:
136 cpsr_mask_bit = cpsr.a;
137 scr_routing_bit = scr.ea;
138 hcr_mask_override_bit = hcr.amo;
139 break;
140 default:
141 panic("Unhandled interrupt type!");
142 }
143
144 if (is_secure) {
145 if (!scr.eel2) {
146 if (!scr_routing_bit) {
147 // NS=0,EEL2=0,EAI/IRQ/FIQ=0
148 if (el == EL3)
149 mask = INT_MASK_P;
150 else
151 mask = INT_MASK_M;
152 } else {
153 // NS=0,EEL2=0,EAI/IRQ/FIQ=1
154 if (el == EL3)
155 mask = INT_MASK_M;
156 else
157 mask = INT_MASK_T;
158 }
159 } else {
160 if (!scr_routing_bit) {
161 if (!hcr.tge) {
162 if (!hcr_mask_override_bit) {
163 // NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=0,AMO/IMO/FMO=0
164 if (el == EL3 || el == EL2)
165 mask = INT_MASK_P;
166 else
167 mask = INT_MASK_M;
168 } else {
169 // NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=0,AMO/IMO/FMO=1
170 if (el == EL3)
171 mask = INT_MASK_P;
172 else if (el == EL2)
173 mask = INT_MASK_M;
174 else
175 mask = INT_MASK_T;
176 }
177 } else {
178 if (!hcr.e2h) {
179 // NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=1,E2H=0
180 if (el == EL3)
181 mask = INT_MASK_P;
182 else if (el == EL2)
183 mask = INT_MASK_M;
184 else
185 mask = INT_MASK_T;
186 } else {
187 // NS=0,EEL2=1,EAI/IRQ/FIQ=0,TGE=1,E2H=1
188 if (el == EL3)
189 mask = INT_MASK_P;
190 else
191 mask = INT_MASK_M;
192 }
193 }
194 } else {
195 if (!hcr.tge) {
196 // NS=0,EEL2=1,EAI/IRQ/FIQ=1,TGE=0
197 if (el == EL3)
198 mask = INT_MASK_M;
199 else
200 mask = INT_MASK_T;
201 } else {
202 // NS=0,EEL2=1,EAI/IRQ/FIQ=1,TGE=1
203 if (el == EL3)
204 mask = INT_MASK_M;
205 else
206 mask = INT_MASK_T;
207 }
208 }
209 }
210 } else {
211 if (!scr_routing_bit) {
212 if (!scr.rw) {
213 if (!hcr.tge) {
214 if (!hcr_mask_override_bit) {
215 // NS=1,EAI/IRQ/FIQ=0,RW=0,TGE=0,AMO/IMO?/FMO=0
216 if (el == EL3)
217 mask = INT_MASK_P;
218 else
219 mask = INT_MASK_M;
220 } else {
221 // NS=1,EAI/IRQ/FIQ=0,RW=0,TGE=0,AMO/IMO?/FMO=1
222 if (el == EL3)
223 mask = INT_MASK_P;
224 else if (el == EL2)
225 mask = INT_MASK_M;
226 else
227 mask = INT_MASK_T;
228 }
229 } else {
230 // NS=1,EAI/IRQ/FIQ=0,RW=0,TGE=1
231 if (el == EL3)
232 mask = INT_MASK_P;
233 else if (el == EL2)
234 mask = INT_MASK_M;
235 else
236 mask = INT_MASK_T;
237 }
238 } else {
239 if (!hcr.tge) {
240 if (!hcr_mask_override_bit) {
241 // NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=0,AMO/IMO/FMO=0
242 if (el == EL3 || el == EL2)
243 mask = INT_MASK_P;
244 else
245 mask = INT_MASK_M;
246 } else {
247 // NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=0,AMO/IMO/FMO=1
248 if (el == EL3)
249 mask = INT_MASK_P;
250 else if (el == EL2)
251 mask = INT_MASK_M;
252 else
253 mask = INT_MASK_T;
254 }
255 } else {
256 if (!hcr.e2h) {
257 // NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=1,E2H=0
258 if (el == EL3)
259 mask = INT_MASK_P;
260 else if (el == EL2)
261 mask = INT_MASK_M;
262 else
263 mask = INT_MASK_T;
264 } else {
265 // NS=1,EAI/IRQ/FIQ=0,RW=1,TGE=1,E2H=1
266 if (el == EL3)
267 mask = INT_MASK_P;
268 else
269 mask = INT_MASK_M;
270 }
271 }
272 }
273 } else {
274 if (el == EL3)
275 mask = INT_MASK_M;
276 else
277 mask = INT_MASK_T;
278 }
279 }
280 return ((mask == INT_MASK_T) ||
281 ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
282 (mask != INT_MASK_P);
283}
284
285bool
286ArmISA::Interrupts::takeInt(InterruptTypes int_type) const
287{
288 // Table G1-17~19 of ARM V8 ARM
289 return ArmSystem::highestELIs64(tc) ? takeInt64(int_type) :
290 takeInt32(int_type);
291
292}
293
294bool
295ArmISA::Interrupts::takeVirtualInt(InterruptTypes int_type) const
296{
297 return ArmSystem::highestELIs64(tc) ? takeVirtualInt64(int_type) :
298 takeVirtualInt32(int_type);
299
300}
301
302bool
303ArmISA::Interrupts::takeVirtualInt32(InterruptTypes int_type) const
304{
305 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
306 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
307
308 bool no_vhe = !HaveExt(tc, ArmExtension::FEAT_VHE);
309 bool amo, fmo, imo;
310 bool cpsr_mask_bit, hcr_mask_override_bit;
311
312 if (hcr.tge == 1){
313 amo = (no_vhe || hcr.e2h == 0);
314 fmo = (no_vhe || hcr.e2h == 0);
315 imo = (no_vhe || hcr.e2h == 0);
316 } else {
317 amo = hcr.amo;
318 fmo = hcr.fmo;
319 imo = hcr.imo;
320 }
321
322 bool is_hyp_mode = currEL(tc) == EL2;
323 bool is_secure = ArmISA::isSecure(tc);
324
325 switch(int_type) {
326 case INT_VIRT_FIQ:
327 cpsr_mask_bit = cpsr.f;
328 hcr_mask_override_bit = fmo;
329 break;
330 case INT_VIRT_IRQ:
331 cpsr_mask_bit = cpsr.i;
332 hcr_mask_override_bit = imo;
333 break;
334 case INT_VIRT_ABT:
335 cpsr_mask_bit = cpsr.a;
336 hcr_mask_override_bit = amo;
337 break;
338 default:
339 panic("Unhandled interrupt type!");
340 }
341 return !cpsr_mask_bit && hcr_mask_override_bit &&
342 !is_secure && !is_hyp_mode;
343}
344
345bool
346ArmISA::Interrupts::takeVirtualInt64(InterruptTypes int_type) const
347{
348 InterruptMask mask;
349 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
350 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
351 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
352
353 ExceptionLevel el = currEL(tc);
354 bool cpsr_mask_bit, hcr_mask_override_bit;
355 bool is_secure = ArmISA::isSecureBelowEL3(tc);
356
357 switch(int_type) {
358 case INT_VIRT_FIQ:
359 cpsr_mask_bit = cpsr.f;
360 hcr_mask_override_bit = hcr.fmo;
361 break;
362 case INT_VIRT_IRQ:
363 cpsr_mask_bit = cpsr.i;
364 hcr_mask_override_bit = hcr.imo;
365 break;
366 case INT_VIRT_ABT:
367 cpsr_mask_bit = cpsr.a;
368 hcr_mask_override_bit = hcr.amo;
369 break;
370 default:
371 panic("Unhandled interrupt type!");
372 }
373
374 if (is_secure) {
375 if (!scr.eel2) {
376 // NS=0,EEL2=0
377 mask = INT_MASK_P;
378 } else {
379 if (!hcr.tge) {
380 if (!hcr_mask_override_bit) {
381 // NS=0,EEL2=1,TGE=0,AMO/IMO/FMO=0
382 mask = INT_MASK_P;
383 } else {
384 // NS=0,EEL2=1,TGE=0,AMO/IMO/FMO=1
385 if (el == EL2 || el == EL3)
386 mask = INT_MASK_P;
387 else
388 mask = INT_MASK_M;
389 }
390 } else {
391 // NS=0,EEL2=1,TGE=1
392 mask = INT_MASK_P;
393 }
394 }
395 } else {
396 if (!hcr.tge) {
397 if (!hcr_mask_override_bit) {
398 // NS=1,TGE=0,AMO/IMO/FMO=0
399 mask = INT_MASK_P;
400 } else {
401 // NS=1,TGE=0,AMO/IMO/FMO=1
402 if (el == EL2 || el == EL3)
403 mask = INT_MASK_P;
404 else
405 mask = INT_MASK_M;
406 }
407 } else {
408 // NS=1,TGE=1
409 mask = INT_MASK_P;
410 }
411 }
412
413 return ((mask == INT_MASK_T) ||
414 ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
415 (mask != INT_MASK_P);
416}
417
418} // namespace gem5
gem5::ArmISA::Interrupts::clearAll
void clearAll() override
Definition interrupts.hh:118
gem5::ArmISA::Interrupts::takeInt64
bool takeInt64(InterruptTypes int_type) const
Definition interrupts.cc:114
gem5::ArmISA::Interrupts::takeInt
bool takeInt(InterruptTypes int_type) const
Definition interrupts.cc:286
gem5::ArmISA::Interrupts::takeInt32
bool takeInt32(InterruptTypes int_type) const
Definition interrupts.cc:52
gem5::ArmISA::Interrupts::takeVirtualInt64
bool takeVirtualInt64(InterruptTypes int_type) const
Definition interrupts.cc:346
gem5::ArmISA::Interrupts::takeVirtualInt
bool takeVirtualInt(InterruptTypes int_type) const
Definition interrupts.cc:295
gem5::ArmISA::Interrupts::Params
ArmInterruptsParams Params
Definition interrupts.hh:83
gem5::ArmISA::Interrupts::takeVirtualInt32
bool takeVirtualInt32(InterruptTypes int_type) const
Definition interrupts.cc:303
gem5::ArmISA::Interrupts::Interrupts
Interrupts(const Params &p)
Definition interrupts.cc:46
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition system.hh:188
gem5::BaseInterrupts::tc
ThreadContext * tc
Definition interrupts.hh:44
gem5::BaseInterrupts::BaseInterrupts
BaseInterrupts(const Params &p)
Definition interrupts.hh:49
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:220
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition utility.cc:134
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition utility.cc:74
gem5::ArmISA::imo
Bitfield< 4 > imo
Definition misc_types.hh:364
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition utility.cc:86
gem5::ArmISA::fmo
Bitfield< 3 > fmo
Definition misc_types.hh:365
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition misc.hh:628
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition misc.hh:79
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition misc.hh:619
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition misc_types.hh:73
gem5::ArmISA::amo
Bitfield< 5 > amo
Definition misc_types.hh:363
gem5::ArmISA::HaveExt
bool HaveExt(ThreadContext *tc, ArmExtension ext)
Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.
Definition utility.cc:232
gem5::MipsISA::p
Bitfield< 0 > p
Definition pra_constants.hh:326
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
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