bridge.hh

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#ifndef __MEM_BRIDGE_HH__
#define __MEM_BRIDGE_HH__
 
#include <deque>
 
#include "base/types.hh"
#include "mem/port.hh"
#include "params/Bridge.hh"
#include "params/BridgeBase.hh"
#include "sim/clocked_object.hh"
 
namespace gem5
{

class BridgeBase : public ClockedObject
{
  protected:

    class DeferredPacket
    {
 
      public:
 
        const Tick tick;
        const PacketPtr pkt;
 
        DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
        { }
    };
 
    // Forward declaration to allow the response port to have a pointer
    class BridgeRequestPort;

    class BridgeResponsePort : public ResponsePort
    {
 
      private:

        BridgeBase& bridge;

        BridgeRequestPort& memSidePort;

        const Cycles delay;

        std::deque<DeferredPacket> transmitList;

        unsigned int outstandingResponses;

        bool retryReq;

        unsigned int respQueueLimit;

        std::unique_ptr<Packet> pendingDelete;

        bool respQueueFull() const;

        void trySendTiming();

        EventFunctionWrapper sendEvent;
 
      public:

        BridgeResponsePort(const std::string& _name, BridgeBase& _bridge,
                           BridgeRequestPort& _memSidePort, Cycles _delay,
                           int _resp_limit);

        void schedTimingResp(PacketPtr pkt, Tick when);

        void retryStalledReq();
 
      protected:

        bool recvTimingReq(PacketPtr pkt) override;

        void recvRespRetry() override;

        Tick recvAtomic(PacketPtr pkt) override;

        Tick recvAtomicBackdoor(
            PacketPtr pkt, MemBackdoorPtr &backdoor) override;
 

        void recvFunctional(PacketPtr pkt) override;

        void recvMemBackdoorReq(
            const MemBackdoorReq &req, MemBackdoorPtr &backdoor) override;
 

        AddrRangeList getAddrRanges() const override;
    };
 

    class BridgeRequestPort : public RequestPort
    {
 
      private:

        BridgeBase& bridge;

        BridgeResponsePort& cpuSidePort;

        const Cycles delay;

        std::deque<DeferredPacket> transmitList;

        const unsigned int reqQueueLimit;

        void trySendTiming();

        EventFunctionWrapper sendEvent;
 
      public:

        BridgeRequestPort(const std::string& _name, BridgeBase& _bridge,
                          BridgeResponsePort& _cpuSidePort, Cycles _delay,
                          int _req_limit);

        bool reqQueueFull() const;

        void schedTimingReq(PacketPtr pkt, Tick when);

        bool trySatisfyFunctional(PacketPtr pkt);
 
      protected:

        bool recvTimingResp(PacketPtr pkt) override;

        void recvReqRetry() override;

        void recvRangeChange() override;
    };

    BridgeResponsePort cpuSidePort;

    BridgeRequestPort memSidePort;
 
  protected:
    virtual AddrRangeList getAddrRanges() const = 0;

    virtual void recvRangeChange() {};
 
  public:
    Port& getPort(const std::string& if_name,
                  PortID idx=InvalidPortID) override;
 
    void init() override;
 
    PARAMS(BridgeBase);
 
    BridgeBase(const Params &p);
};

class Bridge : public BridgeBase
{
    const AddrRangeList ranges;
 
  protected:
    AddrRangeList getAddrRanges() const override;
 
  public:
    PARAMS(Bridge);
 
    Bridge(const Params &p);
};
 
} // namespace gem5
 
#endif //__MEM_BRIDGE_HH__