clint.cc

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#include "dev/riscv/clint.hh"
 
#include "cpu/base.hh"
#include "debug/Clint.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/Clint.hh"
#include "sim/system.hh"
 
namespace gem5
{
 
using namespace RiscvISA;
 
Clint::Clint(const Params &params) :
    BasicPioDevice(params, params.pio_size),
    system(params.system),
    nThread(params.num_threads),
    signal(params.name + ".signal", 0, this, INT_RTC),
    reset(params.name + ".reset"),
    resetMtimecmp(params.reset_mtimecmp),
    registers(params.name + ".registers", params.pio_addr, this,
              params.mtimecmp_reset_value)
{
      reset.onChange([this](const bool& new_val){
          if (new_val) {
              doReset();
          }
      });
}
 
void
Clint::raiseInterruptPin(int id)
{
    // Increment mtime when received RTC signal
    uint64_t& mtime = registers.mtime.get();
    if (id == INT_RTC) {
        mtime++;
    }
 
    for (int context_id = 0; context_id < nThread; context_id++) {
 
        auto tc = system->threads[context_id];
 
        // Update misc reg file
        ISA* isa = dynamic_cast<ISA*>(tc->getIsaPtr());
        if (isa->rvType() == RV32) {
            isa->setMiscRegNoEffect(MISCREG_TIME, bits(mtime, 31, 0));
            isa->setMiscRegNoEffect(MISCREG_TIMEH, bits(mtime, 63, 32));
        } else {
            isa->setMiscRegNoEffect(MISCREG_TIME, mtime);
        }
 
        // Post timer interrupt
        uint64_t mtimecmp = registers.mtimecmp[context_id].get();
        if (mtime >= mtimecmp) {
            if (mtime == mtimecmp) {
                DPRINTF(Clint,
                    "MTIP posted - thread: %d, mtime: %d, mtimecmp: %d\n",
                    context_id, mtime, mtimecmp);
            }
            tc->getCpuPtr()->postInterrupt(tc->threadId(),
                    ExceptionCode::INT_TIMER_MACHINE, 0);
        } else {
            tc->getCpuPtr()->clearInterrupt(tc->threadId(),
                    ExceptionCode::INT_TIMER_MACHINE, 0);
        }
    }
}
 
void
Clint::ClintRegisters::init()
{
    using namespace std::placeholders;
 
    // Sanity check
    assert(clint->pioSize >= minBankSize);
 
    // Calculate reserved space size
    const size_t reserved0_size = mtimecmpStart - clint->nThread * 4;
    reserved.emplace_back("reserved0", reserved0_size);
    const size_t reserved1_size = mtimeStart
        - mtimecmpStart - clint->nThread * 8;
    reserved.emplace_back("reserved1", reserved1_size);
    const size_t reserved2_size = clint->pioSize - minBankSize;
    if (reserved2_size > 0) {
        reserved.emplace_back("reserved2", reserved2_size);
    }
 
    // Initialize registers
    for (int i = 0; i < clint->nThread; i++) {
        msip.emplace_back(std::string("msip") + std::to_string(i), 0);
        mtimecmp.emplace_back(
            std::string("mtimecmp") + std::to_string(i), mtimecmpResetValue);
    }
 
    // Add registers to bank
    for (int i = 0; i < clint->nThread; i++) {
        auto write_cb = std::bind(&Clint::writeMSIP, clint, _1, _2, i);
        msip[i].writeable(0x1);
        msip[i].writer(write_cb);
        addRegister(msip[i]);
    }
    addRegister(reserved[0]);
    for (int i = 0; i < clint->nThread; i++) {
        addRegister(mtimecmp[i]);
    }
    addRegister(reserved[1]);
    mtime.readonly();
    addRegister(mtime);
    if (reserved2_size > 0) {
        addRegister(reserved[2]);
    }
}
 
void
Clint::writeMSIP(Register32& reg, const uint32_t& data, const int thread_id)
{
    reg.update(data);
    updateMSIP(thread_id);
};
 
Tick
Clint::read(PacketPtr pkt)
{
    // Check for atomic operation
    bool is_atomic = pkt->isAtomicOp() && pkt->cmd == MemCmd::SwapReq;
    DPRINTF(Clint,
        "Read request - addr: %#x, size: %#x, atomic:%d\n",
        pkt->getAddr(), pkt->getSize(), is_atomic);
 
    // Perform register read
    registers.read(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
 
    if (is_atomic) {
        // Perform atomic operation
        (*(pkt->getAtomicOp()))(pkt->getPtr<uint8_t>());
        return write(pkt);
    } else {
        pkt->makeResponse();
        return pioDelay;
    }
}
 
Tick
Clint::write(PacketPtr pkt)
{
    DPRINTF(Clint,
        "Write request - addr: %#x, size: %#x\n",
        pkt->getAddr(), pkt->getSize());
 
    // Perform register write
    registers.write(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
 
    pkt->makeResponse();
    return pioDelay;
}
 
void
Clint::init()
{
    registers.init();
    BasicPioDevice::init();
}
 
Port &
Clint::getPort(const std::string &if_name, PortID idx)
{
    if (if_name == "int_pin")
        return signal;
    else if (if_name == "reset")
        return reset;
    else
        return BasicPioDevice::getPort(if_name, idx);
}
 
void
Clint::serialize(CheckpointOut &cp) const
{
    for (auto const &reg: registers.msip) {
        paramOut(cp, reg.name(), reg);
    }
    for (auto const &reg: registers.mtimecmp) {
        paramOut(cp, reg.name(), reg);
    }
    paramOut(cp, "mtime", registers.mtime);
}
 
void
Clint::unserialize(CheckpointIn &cp)
{
    for (auto &reg: registers.msip) {
        paramIn(cp, reg.name(), reg);
    }
    for (auto &reg: registers.mtimecmp) {
        paramIn(cp, reg.name(), reg);
    }
    paramIn(cp, "mtime", registers.mtime);
}
 
void
Clint::updateMSIP(const int thread_id)
{
    auto tc = system->threads[thread_id];
    if (registers.msip[thread_id].get()) {
        DPRINTF(Clint, "MSIP posted - thread: %d\n", thread_id);
        tc->getCpuPtr()->postInterrupt(tc->threadId(),
            ExceptionCode::INT_SOFTWARE_MACHINE, 0);
    } else {
        DPRINTF(Clint, "MSIP cleared - thread: %d\n", thread_id);
        tc->getCpuPtr()->clearInterrupt(tc->threadId(),
            ExceptionCode::INT_SOFTWARE_MACHINE, 0);
    }
}
 
void
Clint::doReset() {
    registers.mtime.reset();
    for (int i = 0; i < nThread; i++) {
        // According to the spec, the mtimecmp is in unknown state
        // Assume we will change the mtimecmp registers to specify value
        // if the mtimecmp registers accept the reset signal.
        if (resetMtimecmp) {
            registers.mtimecmp[i].reset();
        }
        registers.msip[i].reset();
        updateMSIP(i);
    }
    // We need to update the mtip interrupt bits when reset
    raiseInterruptPin(INT_RESET);
}
 
} // namespace gem5