fetch1.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2013-2014 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

 
#ifndef __CPU_MINOR_FETCH1_HH__
#define __CPU_MINOR_FETCH1_HH__
 
#include <vector>
 
#include "arch/generic/mmu.hh"
#include "base/named.hh"
#include "cpu/base.hh"
#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/pipe_data.hh"
#include "mem/packet.hh"
 
namespace gem5
{
 
namespace minor
{

class Fetch1 : public Named
{
  protected:
    class IcachePort : public MinorCPU::MinorCPUPort
    {
      protected:
        Fetch1 &fetch;
 
      public:
        IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) :
            MinorCPU::MinorCPUPort(name, cpu), fetch(fetch_)
        { }
 
      protected:
        bool recvTimingResp(PacketPtr pkt)
        { return fetch.recvTimingResp(pkt); }
 
        void recvReqRetry() { fetch.recvReqRetry(); }
    };


    class FetchRequest :
        public BaseMMU::Translation, /* For TLB lookups */
        public Packet::SenderState /* For packing into a Packet */
    {
      protected:
        Fetch1 &fetch;
 
      public:
        enum FetchRequestState
        {
            NotIssued, /* Just been made */
            InTranslation, /* Issued to ITLB, must wait for reqply */
            Translated, /* Translation complete */
            RequestIssuing, /* Issued to memory, must wait for response */
            Complete /* Complete.  Either a fault, or a fetched line */
        };
 
        FetchRequestState state;

        InstId id;

        PacketPtr packet;

        RequestPtr request;

        Addr pc;

        Fault fault;

        void makePacket();

        void reportData(std::ostream &os) const;

        bool isDiscardable() const;

        bool isComplete() const { return state == Complete; }
 
      protected:

        void markDelayed() { }

        void finish(const Fault &fault_, const RequestPtr &request_,
                    ThreadContext *tc, BaseMMU::Mode mode);
 
      public:
        FetchRequest(Fetch1 &fetch_, InstId id_, Addr pc_) :
            SenderState(),
            fetch(fetch_),
            state(NotIssued),
            id(id_),
            packet(NULL),
            request(),
            pc(pc_),
            fault(NoFault)
        {
            request = std::make_shared<Request>();
        }
 
        ~FetchRequest();
    };
 
    typedef FetchRequest *FetchRequestPtr;
 
  protected:

    MinorCPU &cpu;

    Latch<BranchData>::Output inp;
    Latch<ForwardLineData>::Input out;
    Latch<BranchData>::Output prediction;

    std::vector<InputBuffer<ForwardLineData>> &nextStageReserve;

    IcachePort icachePort;

    Addr lineSnap;

    Addr maxLineWidth;

    unsigned int fetchLimit;
 
  protected:

    enum FetchState
    {
        FetchHalted, /* Not fetching, waiting to be woken by transition
            to FetchWaitingForPC.  The PC is not valid in this state */
        FetchWaitingForPC, /* Not fetching, waiting for stream change.
            This doesn't stop issued fetches from being returned and
            processed or for branches to change the state to Running. */
        FetchRunning /* Try to fetch, when possible */
    };

 
    struct Fetch1ThreadInfo
    {
        // All fields have default initializers.
        Fetch1ThreadInfo() {}
 
        Fetch1ThreadInfo(const Fetch1ThreadInfo& other) :
            state(other.state),
            pc(other.pc->clone()),
            streamSeqNum(other.streamSeqNum),
            predictionSeqNum(other.predictionSeqNum),
            blocked(other.blocked)
        { }
 
        FetchState state = FetchWaitingForPC;

        std::unique_ptr<PCStateBase> pc;

        Addr fetchAddr = 0;

        InstSeqNum streamSeqNum = InstId::firstStreamSeqNum;

        InstSeqNum predictionSeqNum = InstId::firstPredictionSeqNum;

        bool blocked = false;

        bool wakeupGuard = false;
    };
 
    std::vector<Fetch1ThreadInfo> fetchInfo;
    ThreadID threadPriority;

    enum IcacheState
    {
        IcacheRunning, /* Default. Step icache queues when possible */
        IcacheNeedsRetry /* Request rejected, will be asked to retry */
    };
 
    typedef Queue<FetchRequestPtr,
        ReportTraitsPtrAdaptor<FetchRequestPtr>,
        NoBubbleTraits<FetchRequestPtr> >
        FetchQueue;

    FetchQueue requests;

    FetchQueue transfers;

    IcacheState icacheState;

    InstSeqNum lineSeqNum;

    unsigned int numFetchesInMemorySystem;
    unsigned int numFetchesInITLB;
 
  protected:
    friend std::ostream &operator <<(std::ostream &os,
        Fetch1::FetchState state);

    void changeStream(const BranchData &branch);

    void updateExpectedSeqNums(const BranchData &branch);

    void processResponse(FetchRequestPtr response,
        ForwardLineData &line);
 
    friend std::ostream &operator <<(std::ostream &os,
        IcacheState state);
 

    ThreadID getScheduledThread();

    void fetchLine(ThreadID tid);

    void tryToSendToTransfers(FetchRequestPtr request);

    bool tryToSend(FetchRequestPtr request);

    void moveFromRequestsToTransfers(FetchRequestPtr request);

    void stepQueues();

    void popAndDiscard(FetchQueue &queue);

    void handleTLBResponse(FetchRequestPtr response);

    unsigned int numInFlightFetches();

    void minorTraceResponseLine(const std::string &name,
        FetchRequestPtr response) const;

    virtual bool recvTimingResp(PacketPtr pkt);
    virtual void recvReqRetry();
 
  public:
    Fetch1(const std::string &name_,
        MinorCPU &cpu_,
        const BaseMinorCPUParams &params,
        Latch<BranchData>::Output inp_,
        Latch<ForwardLineData>::Input out_,
        Latch<BranchData>::Output prediction_,
        std::vector<InputBuffer<ForwardLineData>> &next_stage_input_buffer);
 
  public:
    MinorCPU::MinorCPUPort &getIcachePort() { return icachePort; }

    void evaluate();

    void wakeupFetch(ThreadID tid);
 
    void minorTrace() const;

    bool isDrained();
};
 
} // namespace minor
} // namespace gem5
 
#endif /* __CPU_MINOR_FETCH1_HH__ */