intelmp.cc

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#include "arch/x86/bios/intelmp.hh"
 
#include "base/logging.hh"
#include "base/types.hh"
#include "mem/port_proxy.hh"
#include "sim/byteswap.hh"
 
// Config entry types
#include "params/X86IntelMPBaseConfigEntry.hh"
#include "params/X86IntelMPExtConfigEntry.hh"
 
// General table structures
#include "params/X86IntelMPConfigTable.hh"
#include "params/X86IntelMPFloatingPointer.hh"
 
// Base entry types
#include "params/X86IntelMPBus.hh"
#include "params/X86IntelMPIOAPIC.hh"
#include "params/X86IntelMPIOIntAssignment.hh"
#include "params/X86IntelMPLocalIntAssignment.hh"
#include "params/X86IntelMPProcessor.hh"
 
// Extended entry types
#include "params/X86IntelMPAddrSpaceMapping.hh"
#include "params/X86IntelMPBusHierarchy.hh"
#include "params/X86IntelMPCompatAddrSpaceMod.hh"
 
namespace gem5
{
 
const char X86ISA::intelmp::FloatingPointer::signature[] = "_MP_";
 
template<class T>
uint8_t
writeOutField(PortProxy& proxy, Addr addr, T val)
{
    uint64_t guestVal = htole(val);
    proxy.writeBlob(addr, &guestVal, sizeof(T));
 
    uint8_t checkSum = 0;
    while (guestVal) {
        checkSum += guestVal;
        guestVal >>= 8;
    }
    return checkSum;
}
 
uint8_t
writeOutString(PortProxy& proxy, Addr addr, std::string str, int length)
{
    std::string nullPadded(length, '\0');
    memcpy(nullPadded.data(), str.data(), std::min<int>(str.length(), length));
    if (str.length() > length) {
        warn("Intel MP configuration table string \"%s\" "
             "will be truncated to \"%s\".\n", str, nullPadded);
    }
    proxy.writeBlob(addr, nullPadded.data(), length);
 
    uint8_t checkSum = 0;
    for (int i = 0; i < length; i++)
        checkSum += nullPadded[i];
 
    return checkSum;
}
 
Addr
X86ISA::intelmp::FloatingPointer::writeOut(PortProxy& proxy, Addr addr)
{
    // Make sure that either a config table is present or a default
    // configuration was found but not both.
    if (!tableAddr && !defaultConfig)
        fatal("Either an MP configuration table or a default configuration "
                "must be used.");
    if (tableAddr && defaultConfig)
        fatal("Both an MP configuration table and a default configuration "
                "were set.");
 
    uint8_t checkSum = 0;
 
    proxy.writeBlob(addr, signature, 4);
    for (int i = 0; i < 4; i++)
        checkSum += signature[i];
 
    checkSum += writeOutField(proxy, addr + 4, tableAddr);
 
    // The length of the structure in paragraphs, aka 16 byte chunks.
    uint8_t length = 1;
    proxy.writeBlob(addr + 8, &length, 1);
    checkSum += length;
 
    proxy.writeBlob(addr + 9, &specRev, 1);
    checkSum += specRev;
 
    proxy.writeBlob(addr + 11, &defaultConfig, 1);
    checkSum += defaultConfig;
 
    uint32_t features2_5 = imcrPresent ? (1 << 7) : 0;
    checkSum += writeOutField(proxy, addr + 12, features2_5);
 
    checkSum = -checkSum;
    proxy.writeBlob(addr + 10, &checkSum, 1);
 
    return 16;
}
 
X86ISA::intelmp::FloatingPointer::FloatingPointer(const Params &p) :
    SimObject(p), tableAddr(0), specRev(p.spec_rev),
    defaultConfig(p.default_config), imcrPresent(p.imcr_present)
{}
 
Addr
X86ISA::intelmp::BaseConfigEntry::writeOut(PortProxy& proxy,
        Addr addr, uint8_t &checkSum)
{
    proxy.writeBlob(addr, &type, 1);
    checkSum += type;
    return 1;
}
 
X86ISA::intelmp::BaseConfigEntry::BaseConfigEntry(
        const Params &p, uint8_t _type) :
    SimObject(p), type(_type)
{}
 
Addr
X86ISA::intelmp::ExtConfigEntry::writeOut(PortProxy& proxy,
        Addr addr, uint8_t &checkSum)
{
    proxy.writeBlob(addr, &type, 1);
    checkSum += type;
    proxy.writeBlob(addr + 1, &length, 1);
    checkSum += length;
    return 1;
}
 
X86ISA::intelmp::ExtConfigEntry::ExtConfigEntry(const Params &p,
        uint8_t _type, uint8_t _length) :
    SimObject(p), type(_type), length(_length)
{}
 
const char X86ISA::intelmp::ConfigTable::signature[] = "PCMP";
 
Addr
X86ISA::intelmp::ConfigTable::writeOut(PortProxy& proxy, Addr addr)
{
    uint8_t checkSum = 0;
 
    proxy.writeBlob(addr, signature, 4);
    for (int i = 0; i < 4; i++)
        checkSum += signature[i];
 
    // Base table length goes here but will be calculated later.
 
    proxy.writeBlob(addr + 6, &specRev, 1);
    checkSum += specRev;
 
    // The checksum goes here but is still being calculated.
 
    checkSum += writeOutString(proxy, addr + 8, oemID, 8);
    checkSum += writeOutString(proxy, addr + 16, productID, 12);
 
    checkSum += writeOutField(proxy, addr + 28, oemTableAddr);
    checkSum += writeOutField(proxy, addr + 32, oemTableSize);
    checkSum += writeOutField(proxy, addr + 34, (uint16_t)baseEntries.size());
    checkSum += writeOutField(proxy, addr + 36, localApic);
 
    uint8_t reserved = 0;
    proxy.writeBlob(addr + 43, &reserved, 1);
    checkSum += reserved;
 
    std::vector<BaseConfigEntry *>::iterator baseEnt;
    uint16_t offset = 44;
    for (baseEnt = baseEntries.begin();
            baseEnt != baseEntries.end(); baseEnt++) {
        offset += (*baseEnt)->writeOut(proxy, addr + offset, checkSum);
    }
 
    // We've found the end of the base table this point.
    checkSum += writeOutField(proxy, addr + 4, offset);
 
    std::vector<ExtConfigEntry *>::iterator extEnt;
    uint16_t extOffset = 0;
    uint8_t extCheckSum = 0;
    for (extEnt = extEntries.begin();
            extEnt != extEntries.end(); extEnt++) {
        extOffset += (*extEnt)->writeOut(proxy,
                addr + offset + extOffset, extCheckSum);
    }
 
    checkSum += writeOutField(proxy, addr + 40, extOffset);
    extCheckSum = -extCheckSum;
    checkSum += writeOutField(proxy, addr + 42, extCheckSum);
 
    // And now, we finally have the whole check sum completed.
    checkSum = -checkSum;
    writeOutField(proxy, addr + 7, checkSum);
 
    return offset + extOffset;
};
 
X86ISA::intelmp::ConfigTable::ConfigTable(const Params &p) : SimObject(p),
    specRev(p.spec_rev), oemID(p.oem_id), productID(p.product_id),
    oemTableAddr(p.oem_table_addr), oemTableSize(p.oem_table_size),
    localApic(p.local_apic),
    baseEntries(p.base_entries), extEntries(p.ext_entries)
{}
 
Addr
X86ISA::intelmp::Processor::writeOut(
        PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
    BaseConfigEntry::writeOut(proxy, addr, checkSum);
    checkSum += writeOutField(proxy, addr + 1, localApicID);
    checkSum += writeOutField(proxy, addr + 2, localApicVersion);
    checkSum += writeOutField(proxy, addr + 3, cpuFlags);
    checkSum += writeOutField(proxy, addr + 4, cpuSignature);
    checkSum += writeOutField(proxy, addr + 8, featureFlags);
 
    uint32_t reserved = 0;
    proxy.writeBlob(addr + 12, &reserved, 4);
    proxy.writeBlob(addr + 16, &reserved, 4);
    return 20;
}
 
X86ISA::intelmp::Processor::Processor(const Params &p) : BaseConfigEntry(p, 0),
    localApicID(p.local_apic_id), localApicVersion(p.local_apic_version),
    cpuFlags(0), cpuSignature(0), featureFlags(p.feature_flags)
{
    if (p.enable)
        cpuFlags |= (1 << 0);
    if (p.bootstrap)
        cpuFlags |= (1 << 1);
 
    replaceBits(cpuSignature, 3, 0, p.stepping);
    replaceBits(cpuSignature, 7, 4, p.model);
    replaceBits(cpuSignature, 11, 8, p.family);
}
 
Addr
X86ISA::intelmp::Bus::writeOut(
        PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
    BaseConfigEntry::writeOut(proxy, addr, checkSum);
    checkSum += writeOutField(proxy, addr + 1, busID);
    checkSum += writeOutString(proxy, addr + 2, busType, 6);
    return 8;
}
 
X86ISA::intelmp::Bus::Bus(const Params &p) : BaseConfigEntry(p, 1),
    busID(p.bus_id), busType(p.bus_type)
{}
 
Addr
X86ISA::intelmp::IOAPIC::writeOut(
        PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
    BaseConfigEntry::writeOut(proxy, addr, checkSum);
    checkSum += writeOutField(proxy, addr + 1, id);
    checkSum += writeOutField(proxy, addr + 2, version);
    checkSum += writeOutField(proxy, addr + 3, flags);
    checkSum += writeOutField(proxy, addr + 4, address);
    return 8;
}
 
X86ISA::intelmp::IOAPIC::IOAPIC(const Params &p) : BaseConfigEntry(p, 2),
    id(p.id), version(p.version), flags(0), address(p.address)
{
    if (p.enable)
        flags |= 1;
}
 
Addr
X86ISA::intelmp::IntAssignment::writeOut(
        PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
    BaseConfigEntry::writeOut(proxy, addr, checkSum);
    checkSum += writeOutField(proxy, addr + 1, interruptType);
    checkSum += writeOutField(proxy, addr + 2, flags);
    checkSum += writeOutField(proxy, addr + 4, sourceBusID);
    checkSum += writeOutField(proxy, addr + 5, sourceBusIRQ);
    checkSum += writeOutField(proxy, addr + 6, destApicID);
    checkSum += writeOutField(proxy, addr + 7, destApicIntIn);
    return 8;
}
 
X86ISA::intelmp::IOIntAssignment::IOIntAssignment(const Params &p) :
    IntAssignment(p, p.interrupt_type, p.polarity, p.trigger, 3,
            p.source_bus_id, p.source_bus_irq,
            p.dest_io_apic_id, p.dest_io_apic_intin)
{}
 
X86ISA::intelmp::LocalIntAssignment::LocalIntAssignment(const Params &p) :
    IntAssignment(p, p.interrupt_type, p.polarity, p.trigger, 4,
            p.source_bus_id, p.source_bus_irq,
            p.dest_local_apic_id, p.dest_local_apic_intin)
{}
 
Addr
X86ISA::intelmp::AddrSpaceMapping::writeOut(
        PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
    ExtConfigEntry::writeOut(proxy, addr, checkSum);
    checkSum += writeOutField(proxy, addr + 2, busID);
    checkSum += writeOutField(proxy, addr + 3, addrType);
    checkSum += writeOutField(proxy, addr + 4, addr);
    checkSum += writeOutField(proxy, addr + 12, addrLength);
    return length;
}
 
X86ISA::intelmp::AddrSpaceMapping::AddrSpaceMapping(const Params &p) :
    ExtConfigEntry(p, 128, 20),
    busID(p.bus_id), addrType(p.address_type),
    addr(p.address), addrLength(p.length)
{}
 
Addr
X86ISA::intelmp::BusHierarchy::writeOut(
        PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
    ExtConfigEntry::writeOut(proxy, addr, checkSum);
    checkSum += writeOutField(proxy, addr + 2, busID);
    checkSum += writeOutField(proxy, addr + 3, info);
    checkSum += writeOutField(proxy, addr + 4, parentBus);
 
    uint32_t reserved = 0;
    proxy.writeBlob(addr + 5, &reserved, 3);
 
    return length;
}
 
X86ISA::intelmp::BusHierarchy::BusHierarchy(const Params &p) :
    ExtConfigEntry(p, 129, 8),
    busID(p.bus_id), info(0), parentBus(p.parent_bus)
{
    if (p.subtractive_decode)
        info |= 1;
}
 
Addr
X86ISA::intelmp::CompatAddrSpaceMod::writeOut(
        PortProxy& proxy, Addr addr, uint8_t &checkSum)
{
    ExtConfigEntry::writeOut(proxy, addr, checkSum);
    checkSum += writeOutField(proxy, addr + 2, busID);
    checkSum += writeOutField(proxy, addr + 3, mod);
    checkSum += writeOutField(proxy, addr + 4, rangeList);
    return length;
}
 
X86ISA::intelmp::CompatAddrSpaceMod::CompatAddrSpaceMod(const Params &p) :
    ExtConfigEntry(p, 130, 8),
    busID(p.bus_id), mod(0), rangeList(p.range_list)
{
    if (p.add)
        mod |= 1;
}
 
} // namespace gem5