45#include "debug/MemCheckerMonitor.hh"
66 fatal(
"Communication monitor is not connected on both sides.\n");
72 if (if_name ==
"request" || if_name ==
"mem_side_port") {
74 }
else if (if_name ==
"response" || if_name ==
"cpu_side_port") {
95 "Forwarded functional access: addr = %#llx, size = %d\n",
103 unsigned size = pkt->
getSize();
111 "Received functional snoop: addr = %#llx, size = %d\n",
118 panic(
"Atomic not supported");
124 panic(
"Atomic not supported");
138 bool is_read = pkt->
isRead() && !pkt->
req->isPrefetch();
139 bool is_write = pkt->
isWrite();
140 unsigned size = pkt->
getSize();
143 std::unique_ptr<uint8_t[]> pkt_data;
146 if (expects_response && is_write) {
150 pkt_data.reset(
new uint8_t[size]);
158 if (expects_response && (is_read || is_write)) {
167 if (!successful && expects_response && (is_read || is_write)) {
171 if (successful && expects_response) {
191 "Forwarded read request: serial = %d, addr = %#llx, "
194 }
else if (is_write) {
203 "Forwarded write request: serial = %d, addr = %#llx, "
208 "Forwarded non read/write request: addr = %#llx\n",
addr);
210 }
else if (successful) {
212 "Forwarded request marked for cache response: addr = %#llx\n",
227 bool is_read = pkt->
isRead() && !pkt->
req->isPrefetch();
228 bool is_write = pkt->
isWrite();
229 bool is_failed_LLSC = pkt->
isLLSC() && pkt->
req->getExtraData() == 0;
230 unsigned size = pkt->
getSize();
232 std::unique_ptr<uint8_t[]> pkt_data;
239 pkt_data.reset(
new uint8_t[size]);
243 if (is_read || is_write) {
249 "Monitor got a response without monitor sender state\n");
263 "Received read response: serial = %d, addr = %#llx, "
274 warn(
"%s: read of %#llx @ cycle %d failed:\n%s\n",
282 delete received_state;
283 }
else if (is_write) {
285 "Received write response: serial = %d, addr = %#llx, "
289 if (is_failed_LLSC) {
301 delete received_state;
304 "Received non read/write response: addr = %#llx\n",
addr);
306 }
else if (is_read || is_write) {
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
void recvFunctionalSnoop(PacketPtr pkt)
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
bool recvTimingSnoopResp(PacketPtr pkt)
Tick recvAtomicSnoop(PacketPtr pkt)
MemCheckerMonitorParams Params
Parameters of memchecker monitor.
bool recvTimingResp(PacketPtr pkt)
MemCheckerMonitor(const Params ¶ms)
Constructor based on the Python params.
void recvTimingSnoopReq(PacketPtr pkt)
void recvFunctional(PacketPtr pkt)
MonitorResponsePort cpuSidePort
Instance of response port, i.e.
~MemCheckerMonitor()
Destructor.
MonitorRequestPort memSidePort
Instance of request port, facing the memory side.
bool recvTimingReq(PacketPtr pkt)
AddrRangeList getAddrRanges() const
Tick recvAtomic(PacketPtr pkt)
uint64_t Serial
The Serial type is used to be able to uniquely identify a transaction as it passes through the system...
virtual std::string name() const
bool needsResponse() const
SenderState * senderState
This packet's sender state.
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
RequestPtr req
A pointer to the original request.
bool cacheResponding() const
void writeData(uint8_t *p) const
Copy data from the packet to the memory at the provided pointer.
Ports are used to interface objects to each other.
std::list< AddrRange > AddrRangeList
Convenience typedef for a collection of address ranges.
#define panic(...)
This implements a cprintf based panic() function.
#define fatal(...)
This implements a cprintf based fatal() function.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
const Params & params() const
SimObject(const Params &p)
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Copyright (c) 2024 Arm Limited All rights reserved.
Tick curTick()
The universal simulation clock.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
uint64_t Tick
Tick count type.
MemChecker::Serial serial
SenderState * predecessor