57 burstSize((_p.devices_per_rank * _p.burst_length *
58 _p.device_bus_width) / 8),
78 uint8_t pseudo_channel)
AbstractMemory(const AbstractMemory &)
The memory controller is a single-channel memory controller capturing the most important timing const...
const uint32_t burstsPerStripe
enums::AddrMap addrMapping
Memory controller configuration initialized based on parameter values.
const uint32_t devicesPerRank
MemCtrl * ctrl
A pointer to the parent memory controller instance.
const uint32_t writeBufferSize
const uint32_t ranksPerChannel
uint8_t pseudoChannel
pseudo channel number used for HBM modeling
const uint64_t deviceSize
const uint32_t burstSize
General device and channel characteristics The rowsPerBank is determined based on the capacity,...
const uint32_t banksPerRank
unsigned int maxCommandsPerWindow
Number of commands that can issue in the defined controller command window, used to verify command ba...
void setCtrl(MemCtrl *_ctrl, unsigned int command_window, uint8_t pseudo_channel=0)
Set a pointer to the controller and initialize interface based on controller parameters.
const uint32_t burstsPerRowBuffer
const uint32_t readBufferSize
Buffer sizes for read and write queues in the controller These are passed to the controller on instan...
GEM5_CLASS_VAR_USED const Tick tCK
General timing requirements.
const uint32_t rowBufferSize
MemInterface(const Params &_p)
uint32_t numWritesQueued
NVM specific variable, but declaring it here allows treating different interfaces in a more genral wa...
const uint32_t deviceRowBufferSize
MemInterface declaration.
Bitfield< 6 > granularity
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