44#include "debug/Decode.hh"
54 const BaseMinorCPUParams ¶ms,
71 if (params.decodeInputBufferSize < 1) {
72 fatal(
"%s: decodeInputBufferSize must be >= 1 (%d)\n", name,
73 params.decodeInputBufferSize);
77 for (
ThreadID tid = 0; tid < params.numThreads; tid++) {
80 name +
".inputBuffer" + std::to_string(tid),
"insts",
81 params.decodeInputBufferSize));
131 if (!
inp.outputWire->isBubble())
138 for (
ThreadID tid = 0; tid <
cpu.numThreads; tid++)
147 unsigned int output_index = 0;
157 if (inst->isBubble()) {
168 cpu.getContext(inst->id.threadId)->getDecoderPtr();
170 if (inst->isFault()) {
172 inst->fault->name());
187 static_micro_inst = dec_ptr->fetchRomMicroop(
188 decode_info.
microopPC->microPC(), static_inst);
204 output_inst->predictedTaken = inst->predictedTaken;
205 set(output_inst->predictedTarget,
206 inst->predictedTarget);
210 " %d output_index: %d lastMicroop: %s microopPC:"
220 parent_static_inst = static_inst;
232 " %d output_index: %d\n",
233 *output_inst, decode_info.
inputIndex, output_index);
235 parent_static_inst = static_inst;
243 output_inst->id.execSeqNum = decode_info.
execSeqNum;
246 dynInstAddTracing(output_inst, parent_static_inst,
cpu);
255 insts_out.
insts[output_index] = output_inst;
287 cpu.activityRecorder->activity();
303 if (!
inp.outputWire->isBubble())
313 switch (
cpu.threadPolicy) {
314 case enums::SingleThreaded:
315 priority_list.push_back(0);
317 case enums::RoundRobin:
321 priority_list =
cpu.randomPriority();
324 panic(
"Unknown fetch policy");
327 for (
auto tid : priority_list) {
345 return (*
inp.outputWire).isBubble();
351 std::ostringstream
data;
356 (*
out.inputWire).reportData(
data);
virtual ThreadContext * getContext(int tn)
Given a thread num get tho thread context for it.
trace::InstTracer * getTracer()
Provide access to the tracer pointer.
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Named(std::string_view name_)
virtual std::string name() const
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
virtual void advancePC(PCStateBase &pc_state) const =0
bool isLastMicroop() const
void evaluate()
Pass on input/buffer data to the output if you can.
bool isDrained()
Is this stage drained?
std::vector< InputBuffer< ForwardInstData > > inputBuffer
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on, or 0 if there is no data.
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
std::vector< InputBuffer< ForwardInstData > > & nextStageReserve
Interface to reserve space in the next stage.
Latch< ForwardInstData >::Output inp
Input port carrying macro instructions from Fetch2.
std::vector< DecodeThreadInfo > decodeInfo
unsigned int outputWidth
Width of output of this stage/input of next in instructions.
Decode(const std::string &name, MinorCPU &cpu_, const BaseMinorCPUParams ¶ms, Latch< ForwardInstData >::Output inp_, Latch< ForwardInstData >::Input out_, std::vector< InputBuffer< ForwardInstData > > &next_stage_input_buffer)
Latch< ForwardInstData >::Input out
Output port carrying micro-op decomposed instructions to Execute.
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to decode from.
MinorCPU & cpu
Pointer back to the containing CPU.
bool processMoreThanOneInput
If true, more than one input word can be processed each cycle if there is room in the output to conta...
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
ThreadID threadId
Thread associated with these instructions.
void resize(unsigned int width)
Resize a bubble/empty ForwardInstData and fill with bubbles.
bool isBubble() const
BubbleIF interface.
MinorDynInstPtr insts[MAX_FORWARD_INSTS]
Array of carried insts, ref counted.
unsigned int width() const
Number of instructions carried by this object.
ThreadID threadId
The thread to which this line/instruction belongs.
InstSeqNum execSeqNum
'Execute' sequence number.
Dynamic instruction for Minor.
trace::InstRecord * traceData
Trace information for this instruction's execution.
std::unique_ptr< PCStateBase > pc
The fetch address of this instruction.
const StaticInstPtr staticInst
void setFetchSeq(InstSeqNum seq)
virtual InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, const PCStateBase &pc, const StaticInstPtr macroStaticInst=nullptr)=0
#define panic(...)
This implements a cprintf based panic() function.
#define fatal(...)
This implements a cprintf based fatal() function.
Decode collects macro-ops from Fetch2 and splits them into micro-ops passed to Execute.
RefCountingPtr< MinorDynInst > MinorDynInstPtr
MinorDynInsts are currently reference counted.
void minorTrace(const char *fmt, Args ...args)
DPRINTFN for MinorTrace reporting.
Copyright (c) 2024 Arm Limited All rights reserved.
int16_t ThreadID
Thread index/ID type.
const ThreadID InvalidThreadID
Tick curTick()
The universal simulation clock.
RefCountingPtr< StaticInst > StaticInstPtr
static bool isRomMicroPC(MicroPC upc)
constexpr decltype(nullptr) NoFault
The constructed pipeline.
Data members after this line are cycle-to-cycle state.
InstSeqNum execSeqNum
Source of execSeqNums to number instructions.
bool inMacroop
True when we're in the process of decomposing a micro-op and microopPC will be valid.
std::unique_ptr< PCStateBase > microopPC
unsigned int inputIndex
Index into the inputBuffer's head marking the start of unhandled instructions.