gem5 [DEVELOP-FOR-25.0]
Loading...
Searching...
No Matches
noncoherent_xbar.hh
Go to the documentation of this file.
1/*
2 * Copyright (c) 2011-2015, 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
45
46#ifndef __MEM_NONCOHERENT_XBAR_HH__
47#define __MEM_NONCOHERENT_XBAR_HH__
48
49#include "mem/xbar.hh"
50#include "params/NoncoherentXBar.hh"
51
52namespace gem5
53{
54
69{
70
71 protected:
72
79
86 {
87 private:
88
91
94
95 public:
96
98 NoncoherentXBar &_xbar, PortID _id)
99 : QueuedResponsePort(_name, queue, _id), xbar(_xbar),
100 queue(_xbar, *this)
101 { }
102
103 protected:
104
105 bool
107 {
108 return xbar.recvTimingReq(pkt, id);
109 }
110
111 Tick
112 recvAtomic(PacketPtr pkt) override
113 {
114 return xbar.recvAtomicBackdoor(pkt, id);
115 }
116
117 Tick
119 {
120 return xbar.recvAtomicBackdoor(pkt, id, &backdoor);
121 }
122
123 void
125 {
126 xbar.recvFunctional(pkt, id);
127 }
128
129 void
131 MemBackdoorPtr &backdoor) override
132 {
133 xbar.recvMemBackdoorReq(req, backdoor);
134 }
135
137 getAddrRanges() const override
138 {
139 return xbar.getAddrRanges();
140 }
141 };
142
149 {
150 private:
151
154
155 public:
156
158 NoncoherentXBar &_xbar, PortID _id)
159 : RequestPort(_name, _id), xbar(_xbar)
160 { }
161
162 protected:
163
164 bool
166 {
167 return xbar.recvTimingResp(pkt, id);
168 }
169
170 void
172 {
173 xbar.recvRangeChange(id);
174 }
175
176 void
177 recvReqRetry() override
178 {
179 xbar.recvReqRetry(id);
180 }
181 };
182
183 virtual bool recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id);
184 virtual bool recvTimingResp(PacketPtr pkt, PortID mem_side_port_id);
185 void recvReqRetry(PortID mem_side_port_id);
186 Tick recvAtomicBackdoor(PacketPtr pkt, PortID cpu_side_port_id,
187 MemBackdoorPtr *backdoor=nullptr);
188 void recvFunctional(PacketPtr pkt, PortID cpu_side_port_id);
189 void recvMemBackdoorReq(const MemBackdoorReq &req,
190 MemBackdoorPtr &backdoor);
191
192 public:
193
194 NoncoherentXBar(const NoncoherentXBarParams &p);
195
196 virtual ~NoncoherentXBar();
197};
198
199} // namespace gem5
200
201#endif //__MEM_NONCOHERENT_XBAR_HH__
BaseXBar(const BaseXBarParams &p)
Definition xbar.cc:60
const std::string _name
Definition named.hh:54
NoncoherentXBar & xbar
A reference to the crossbar to which this port belongs.
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
void recvRangeChange() override
Called to receive an address range change from the peer response port.
NoncoherentXBarRequestPort(const std::string &_name, NoncoherentXBar &_xbar, PortID _id)
void recvReqRetry() override
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
NoncoherentXBar & xbar
A reference to the crossbar to which this port belongs.
void recvMemBackdoorReq(const MemBackdoorReq &req, MemBackdoorPtr &backdoor) override
Receive a request for a back door to a range of memory.
bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the peer.
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &backdoor) override
Receive an atomic request packet from the peer, and optionally provide a backdoor to the data being a...
AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
RespPacketQueue queue
A normal packet queue used to store responses.
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
NoncoherentXBarResponsePort(const std::string &_name, NoncoherentXBar &_xbar, PortID _id)
NoncoherentXBar(const NoncoherentXBarParams &p)
std::vector< RespLayer * > respLayers
Tick recvAtomicBackdoor(PacketPtr pkt, PortID cpu_side_port_id, MemBackdoorPtr *backdoor=nullptr)
void recvReqRetry(PortID mem_side_port_id)
virtual bool recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id)
virtual bool recvTimingResp(PacketPtr pkt, PortID mem_side_port_id)
void recvMemBackdoorReq(const MemBackdoorReq &req, MemBackdoorPtr &backdoor)
void recvFunctional(PacketPtr pkt, PortID cpu_side_port_id)
std::vector< ReqLayer * > reqLayers
Declare the layers of this crossbar, one vector for requests and one for responses.
QueuedResponsePort(const std::string &name, RespPacketQueue &resp_queue, PortID id=InvalidPortID)
Create a QueuedPort with a given name, owner, and a supplied implementation of a packet queue.
Definition qport.hh:80
RequestPort(const std::string &name, SimObject *_owner, PortID id=InvalidPortID)
Request port.
Definition port.cc:125
STL vector class.
Definition stl.hh:37
std::list< AddrRange > AddrRangeList
Convenience typedef for a collection of address ranges.
Definition addr_range.hh:64
Bitfield< 0 > p
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
MemBackdoor * MemBackdoorPtr
Definition backdoor.hh:127
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
uint64_t Tick
Tick count type.
Definition types.hh:58
Packet * PacketPtr
Declaration of an abstract crossbar base class.

Generated on Mon May 26 2025 09:19:12 for gem5 by doxygen 1.13.2