interrupts.hh

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/*
 * Copyright (c) 2011 Google
 * Copyright (c) 2024 University of Rostock
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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 */
 
#ifndef __ARCH_RISCV_INTERRUPT_HH__
#define __ARCH_RISCV_INTERRUPT_HH__
 
#include <bitset>
#include <memory>
 
#include "arch/generic/interrupts.hh"
#include "arch/riscv/faults.hh"
#include "arch/riscv/regs/misc.hh"
#include "base/logging.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Interrupt.hh"
#include "dev/intpin.hh"
#include "params/RiscvInterrupts.hh"
#include "sim/sim_object.hh"
 
namespace gem5
{
 
class BaseCPU;
class ThreadContext;
 
namespace RiscvISA {
 
/*
 * This is based on version 1.10 of the RISC-V privileged ISA reference,
 * chapter 3.1.14.
 */
class Interrupts : public BaseInterrupts
{
  private:
    std::bitset<NumInterruptTypes> ip;
    std::bitset<NumInterruptTypes> ie;
 
    std::vector<gem5::IntSinkPin<Interrupts>*> localInterruptPins;
  protected:
    int nmi_cause;
 
  public:
    using Params = RiscvInterruptsParams;
 
    Interrupts(const Params &p);
 
    std::bitset<NumInterruptTypes> globalMask() const;
 
    bool
    checkNonMaskableInterrupt() const
    {
        return tc->readMiscReg(MISCREG_NMIP) & tc->readMiscReg(MISCREG_NMIE);
    }
 
    bool checkInterrupt(int num) const { return ip[num] && ie[num]; }
    bool checkInterrupts() const override
    {
        ISA* isa = static_cast<ISA*>(tc->getIsaPtr());
        if (isa->enableSmrnmi() && tc->readMiscReg(MISCREG_NMIE) == 0) {
            return false;
        }
        return checkNonMaskableInterrupt() || (ip & ie & globalMask()).any();
    }
 
    Fault getInterrupt() override;
 
    void updateIntrInfo() override {}
 
    void post(int int_num, int index) override;
 
    void clear(int int_num, int index) override;
 
    void postNMI() { tc->setMiscReg(MISCREG_NMIP, 1); }
    void clearNMI() { tc->setMiscReg(MISCREG_NMIP, 0); }
 
    void clearAll() override;
 
    bool isWakeUp() const override
    {
        return checkNonMaskableInterrupt() || (ip & ie).any();
    }
 
    uint64_t readIP() const { return (uint64_t)ip.to_ulong(); }
    uint64_t readIE() const { return (uint64_t)ie.to_ulong(); }
    void setIP(const uint64_t& val) { ip = val; }
    void setIE(const uint64_t& val) { ie = val; }
 
    void serialize(CheckpointOut &cp) const override;
 
    void unserialize(CheckpointIn &cp) override;
 
    Port &getPort(const std::string &if_name, PortID idx) override;
 
    void raiseInterruptPin(uint32_t num);
    void lowerInterruptPin(uint32_t num) {};
};
 
} // namespace RiscvISA
} // namespace gem5
 
#endif // __ARCH_RISCV_INTERRUPT_HH__