system.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2012, 2014, 2018 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2002-2005 The Regents of The University of Michigan
 * Copyright (c) 2011 Regents of the University of California
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __SYSTEM_HH__
#define __SYSTEM_HH__
 
#include <set>
#include <string>
#include <unordered_map>
#include <utility>
#include <vector>
 
#include "base/loader/memory_image.hh"
#include "base/loader/symtab.hh"
#include "base/statistics.hh"
#include "cpu/pc_event.hh"
#include "enums/MemoryMode.hh"
#include "mem/mem_requestor.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "mem/port_proxy.hh"
#include "params/System.hh"
#include "sim/futex_map.hh"
#include "sim/redirect_path.hh"
#include "sim/se_signal.hh"
#include "sim/sim_object.hh"
#include "sim/workload.hh"
 
namespace gem5
{
 
class BaseRemoteGDB;
class KvmVM;
class ThreadContext;
 
class System : public SimObject, public PCEventScope
{
  private:

    class SystemPort : public RequestPort
    {
      public:

        SystemPort(const std::string &_name)
            : RequestPort(_name)
        { }
 
        bool
        recvTimingResp(PacketPtr pkt) override
        {
            panic("SystemPort does not receive timing!");
        }
 
        void
        recvReqRetry() override
        {
            panic("SystemPort does not expect retry!");
        }
    };
 
    std::list<PCEvent *> liveEvents;
    SystemPort _systemPort;
 
    // Map of memory address ranges for devices with their own backing stores
    std::unordered_map<RequestorID, std::vector<memory::AbstractMemory *>>
        deviceMemMap;
 
    // List of address ranges that are have valid physical addresses but
    // don't appear in the physical memory map. Note that these are assumed
    // to be coherent addresses, not I/O or device addresses
    AddrRangeList externalMemRanges;
 
  public:
 
    class Threads
    {
      private:
        struct Thread
        {
            ThreadContext *context = nullptr;
            bool active = false;
            Event *resumeEvent = nullptr;
 
            void resume();
            std::string name() const;
            void quiesce() const;
        };
 
        std::vector<Thread> threads;
 
        Thread &
        thread(ContextID id)
        {
            assert(id < size());
            return threads[id];
        }
 
        const Thread &
        thread(ContextID id) const
        {
            assert(id < size());
            return threads[id];
        }
 
        void insert(ThreadContext *tc);
        void replace(ThreadContext *tc, ContextID id);
 
        friend class System;
 
      public:
        class const_iterator
        {
          private:
            Threads const* threads;
            int pos;
 
            friend class Threads;
 
            const_iterator(const Threads &_threads, int _pos) :
                threads(&_threads), pos(_pos)
            {}
 
          public:
            using iterator_category = std::forward_iterator_tag;
            using value_type = ThreadContext *;
            using difference_type = int;
            using pointer = const value_type *;
            using reference = const value_type &;
 
            const_iterator &
            operator ++ ()
            {
                pos++;
                return *this;
            }
 
            const_iterator
            operator ++ (int)
            {
                return const_iterator(*threads, pos++);
            }
 
            reference operator * () { return threads->thread(pos).context; }
            pointer operator -> () { return &threads->thread(pos).context; }
 
            bool
            operator == (const const_iterator &other) const
            {
                return threads == other.threads && pos == other.pos;
            }
 
            bool
            operator != (const const_iterator &other) const
            {
                return !(*this == other);
            }
        };
 
        ThreadContext *findFree();
 
        ThreadContext *
        operator [](ContextID id) const
        {
            return thread(id).context;
        }
 
        void markActive(ContextID id) { thread(id).active = true; }
 
        int size() const { return threads.size(); }
        bool empty() const { return threads.empty(); }
        int numRunning() const;
        int
        numActive() const
        {
            int count = 0;
            for (auto &thread: threads) {
                if (thread.active)
                    count++;
            }
            return count;
        }
 
        void quiesce(ContextID id);
        void quiesceTick(ContextID id, Tick when);
 
        const_iterator begin() const { return const_iterator(*this, 0); }
        const_iterator end() const { return const_iterator(*this, size()); }
    };

    RequestPort& getSystemPort() { return _systemPort; }

    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;

    bool
    isAtomicMode() const
    {
        return memoryMode == enums::atomic ||
            memoryMode == enums::atomic_noncaching;
    }

    bool isTimingMode() const { return memoryMode == enums::timing; }

    bool
    bypassCaches() const
    {
        return memoryMode == enums::atomic_noncaching;
    }


    enums::MemoryMode getMemoryMode() const { return memoryMode; }

    void setMemoryMode(enums::MemoryMode mode);

    Addr cacheLineSize() const { return _cacheLineSize; }
 
    Threads threads;
 
    const bool multiThread;
 
    using SimObject::schedule;
 
    bool schedule(PCEvent *event) override;
    bool remove(PCEvent *event) override;
 
    uint64_t init_param;

    PortProxy physProxy;

    Workload *workload = nullptr;
 
  public:
    KvmVM *getKvmVM() const { return kvmVM; }

    void setKvmVM(KvmVM *const vm) { kvmVM = vm; }

    memory::PhysicalMemory& getPhysMem() { return physmem; }
    const memory::PhysicalMemory& getPhysMem() const { return physmem; }

    Addr memSize() const;

    bool isMemAddr(Addr addr) const;

    void addDeviceMemory(RequestorID requestorId,
        memory::AbstractMemory *deviceMemory);

    bool isDeviceMemAddr(const PacketPtr& pkt) const;

    memory::AbstractMemory *getDeviceMemory(const PacketPtr& pkt) const;
 
    /*
     * Return the list of address ranges backed by a shadowed ROM.
     *
     * @return List of address ranges backed by a shadowed ROM
     */
    AddrRangeList getShadowRomRanges() const { return ShadowRomRanges; }

    ByteOrder
    getGuestByteOrder() const
    {
        return workload->byteOrder();
    }

    ThermalModel * getThermalModel() const { return thermalModel; }
 
  protected:
 
    KvmVM *kvmVM = nullptr;
 
    memory::PhysicalMemory physmem;
 
    AddrRangeList ShadowRomRanges;
 
    enums::MemoryMode memoryMode;
 
    const Addr _cacheLineSize;
 
    uint64_t workItemsBegin = 0;
    uint64_t workItemsEnd = 0;
    uint32_t numWorkIds;

    std::vector<RequestorInfo> requestors;
 
    ThermalModel * thermalModel;
 
  protected:
    std::string stripSystemName(const std::string& requestor_name) const;
 
  public:

    RequestorID getRequestorId(const SimObject* requestor,
                         std::string subrequestor={});

    RequestorID getGlobalRequestorId(const std::string& requestor_name);

    std::string getRequestorName(RequestorID requestor_id);

    RequestorID lookupRequestorId(const SimObject* obj) const;

    RequestorID lookupRequestorId(const std::string& name) const;

    RequestorID maxRequestors() { return requestors.size(); }
 
  protected:
    RequestorID _getRequestorId(const SimObject* requestor,
                          const std::string& requestor_name);

    std::string leafRequestorName(const SimObject* requestor,
                               const std::string& subrequestor);
 
  public:
 
    void regStats() override;
    uint64_t
    incWorkItemsBegin()
    {
        return ++workItemsBegin;
    }

    uint64_t
    incWorkItemsEnd()
    {
        return ++workItemsEnd;
    }

    int
    markWorkItem(int index)
    {
        threads.markActive(index);
        return threads.numActive();
    }
 
    void
    workItemBegin(uint32_t tid, uint32_t workid)
    {
        std::pair<uint32_t, uint32_t> p(tid, workid);
        lastWorkItemStarted[p] = curTick();
    }
 
    void workItemEnd(uint32_t tid, uint32_t workid);
 
    /* Returns whether we successfully trapped into GDB. */
    bool trapToGdb(GDBSignal signal, ContextID ctx_id) const;
 
  protected:
    const AddrRange _m5opRange;
 
  public:
    PARAMS(System);
 
    System(const Params &p);
    ~System();

    const AddrRange &m5opRange() const { return _m5opRange; }
 
  public:
 
    void registerThreadContext(ThreadContext *tc);
    void replaceThreadContext(ThreadContext *tc, ContextID context_id);
 
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;
 
  public:
    std::map<std::pair<uint32_t, uint32_t>, Tick>  lastWorkItemStarted;
    std::map<uint32_t, statistics::Histogram*> workItemStats;

    //
    // STATIC GLOBAL SYSTEM LIST
    //
 
    static std::vector<System *> systemList;
    static int numSystemsRunning;
 
    static void printSystems();
 
    FutexMap futexMap;
 
    static const int maxPID = 32768;

    std::set<int> PIDs;
 
    // By convention, all signals are owned by the receiving process. The
    // receiver will delete the signal upon reception.
    std::list<BasicSignal> signalList;
 
    // Used by syscall-emulation mode. This member contains paths which need
    // to be redirected to the faux-filesystem (a duplicate filesystem
    // intended to replace certain files on the host filesystem).
    std::vector<RedirectPath*> redirectPaths;
};
 
void printSystems();
 
} // namespace gem5
 
#endif // __SYSTEM_HH__