gem5 [DEVELOP-FOR-25.0]
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simpoint.cc
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1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
39
40#include "base/output.hh"
41
42namespace gem5
43{
44
45SimPoint::SimPoint(const SimPointParams &p)
47 intervalSize(p.interval),
50 simpointStream(NULL),
51 currentBBV(0, 0),
53{
54 simpointStream = simout.create(p.profile_file, false);
55 if (!simpointStream)
56 fatal("unable to open SimPoint profile_file");
57}
58
63
64void
67
68void
75
76void
78{
79 SimpleThread* thread = p.first;
80 const StaticInstPtr &inst = p.second;
81
82 if (inst->isMicroop() && !inst->isLastMicroop())
83 return;
84
86 currentBBV.first = thread->pcState().instAddr();
87
90
91 // If inst is control inst, assume end of basic block.
92 if (inst->isControl()) {
93 currentBBV.second = thread->pcState().instAddr();
94
95 auto map_itr = bbMap.find(currentBBV);
96 if (map_itr == bbMap.end()){
97 // If a new (previously unseen) basic block is found,
98 // add a new unique id, record num of insts and insert
99 // into bbMap.
100 BBInfo info;
101 info.id = bbMap.size() + 1;
104 bbMap.insert(std::make_pair(currentBBV, info));
105 } else {
106 // If basic block is seen before, just increment the count by the
107 // number of insts in basic block.
108 BBInfo& info = map_itr->second;
110 }
112
113 // Reached end of interval if the sum of the current inst count
114 // (intervalCount) and the excessive inst count from the previous
115 // interval (intervalDrift) is greater than/equal to the interval size.
117 // summarize interval and display BBV info
119 for (auto map_itr = bbMap.begin(); map_itr != bbMap.end();
120 ++map_itr) {
121 BBInfo& info = map_itr->second;
122 if (info.count != 0) {
123 counts.push_back(std::make_pair(info.id, info.count));
124 info.count = 0;
125 }
126 }
127 std::sort(counts.begin(), counts.end());
128
129 // Print output BBV info
130 *simpointStream->stream() << "T";
131 for (auto cnt_itr = counts.begin(); cnt_itr != counts.end();
132 ++cnt_itr) {
133 *simpointStream->stream() << ":" << cnt_itr->first
134 << ":" << cnt_itr->second << " ";
135 }
136 *simpointStream->stream() << "\n";
137
139 intervalCount = 0;
140 }
141 }
142}
143
144} // namespace gem5
Addr instAddr() const
Returns the memory address of the instruction this PC points to.
Definition pcstate.hh:108
ProbeListenerArg generates a listener for the class of Arg and the class type T which is the class co...
Definition probe.hh:239
ProbeListenerObject(const ProbeListenerObjectParams &params)
void connectListener(Args &&...args)
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition simpoint.cc:65
uint64_t intervalDrift
Excess inst count from previous interval.
Definition simpoint.hh:106
void profile(const std::pair< SimpleThread *, StaticInstPtr > &)
Profile basic blocks for SimPoints.
Definition simpoint.cc:77
OutputStream * simpointStream
Pointer to SimPoint BBV output stream.
Definition simpoint.hh:108
std::unordered_map< BasicBlockRange, BBInfo > bbMap
Hash table containing all previously seen basic blocks.
Definition simpoint.hh:122
uint64_t currentBBVInstCount
inst count in current basic block
Definition simpoint.hh:126
virtual ~SimPoint()
Definition simpoint.cc:59
SimPoint(const SimPointParams &params)
Definition simpoint.cc:45
const uint64_t intervalSize
SimPoint profiling interval size in instructions.
Definition simpoint.hh:101
uint64_t intervalCount
Inst count in current basic block.
Definition simpoint.hh:104
virtual void regProbeListeners()
Register probe listeners for this object.
Definition simpoint.cc:69
BasicBlockRange currentBBV
Currently executing basic block.
Definition simpoint.hh:124
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
const PCStateBase & pcState() const override
bool isLastMicroop() const
bool isMicroop() const
bool isControl() const
STL pair class.
Definition stl.hh:58
STL vector class.
Definition stl.hh:37
#define fatal(...)
This implements a cprintf based fatal() function.
Definition logging.hh:232
Bitfield< 0 > p
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
OutputDirectory simout
Definition output.cc:62
RefCountingPtr< StaticInst > StaticInstPtr
Basic Block information.
Definition simpoint.hh:112
uint64_t insts
Num of static insts in BB.
Definition simpoint.hh:116
uint64_t count
Accumulated dynamic inst count executed by BB.
Definition simpoint.hh:118
uint64_t id
Unique ID.
Definition simpoint.hh:114

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