vec.hh File Reference

#include "arch/arm/types.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "cpu/reg_class.hh"
#include "debug/VecPredRegs.hh"
#include "debug/VecRegs.hh"

Go to the source code of this file.

Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.
namespace	gem5::ArmISA

Typedefs
using	gem5::ArmISA::VecElem = uint32_t
using	gem5::ArmISA::VecRegContainer
using	gem5::ArmISA::VecPredReg
using	gem5::ArmISA::ConstVecPredReg
using	gem5::ArmISA::VecPredRegContainer = VecPredReg::Container

Variables
constexpr unsigned	gem5::ArmISA::NumVecElemPerNeonVecReg = 4
constexpr unsigned	gem5::ArmISA::NumVecElemPerVecReg = MaxSveVecLenInWords
const int	gem5::ArmISA::NumFloatV7ArchRegs = 64
const int	gem5::ArmISA::NumVecV7ArchRegs = 16
const int	gem5::ArmISA::NumVecV8ArchRegs = 32
const int	gem5::ArmISA::NumVecSpecialRegs = 8
const int	gem5::ArmISA::NumVecIntrlvRegs = 4
const int	gem5::ArmISA::NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs
const int	gem5::ArmISA::NumVecPredRegs = 18
const int	gem5::ArmISA::VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg
const int	gem5::ArmISA::INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs
const int	gem5::ArmISA::INTRLVREG1 = INTRLVREG0 + 1
const int	gem5::ArmISA::INTRLVREG2 = INTRLVREG0 + 2
const int	gem5::ArmISA::INTRLVREG3 = INTRLVREG0 + 3
const int	gem5::ArmISA::VECREG_UREG0 = 32
const int	gem5::ArmISA::PREDREG_FFR = 16
const int	gem5::ArmISA::PREDREG_UREG0 = 17
static VecElemRegClassOps< RegVal >	gem5::ArmISA::vecRegElemClassOps (NumVecElemPerVecReg)
static TypedRegClassOps< ArmISA::VecRegContainer >	gem5::ArmISA::vecRegClassOps
static TypedRegClassOps< ArmISA::VecPredRegContainer >	gem5::ArmISA::vecPredRegClassOps
constexpr RegClass	gem5::ArmISA::vecRegClass
constexpr RegClass	gem5::ArmISA::vecElemClass
constexpr RegClass	gem5::ArmISA::vecPredRegClass