vector_register_file.hh

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/*
 * Copyright (c) 2015-2017 Advanced Micro Devices, Inc.
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are met:
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 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
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 * software without specific prior written permission.
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#ifndef __VECTOR_REGISTER_FILE_HH__
#define __VECTOR_REGISTER_FILE_HH__
 
#include "arch/gpu_isa.hh"
#include "config/the_gpu_isa.hh"
#include "debug/GPUTrace.hh"
#include "debug/GPUVRF.hh"
#include "gpu-compute/register_file.hh"
#include "gpu-compute/wavefront.hh"
 
namespace gem5
{
 
struct VectorRegisterFileParams;
 
// Vector Register File
class VectorRegisterFile : public RegisterFile
{
  public:
    using VecRegContainer = TheGpuISA::VecRegContainerU32;
 
    VectorRegisterFile(const VectorRegisterFileParams &p);
    ~VectorRegisterFile() { }
 
    virtual bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const override;
    virtual void scheduleWriteOperands(Wavefront *w,
                                       GPUDynInstPtr ii) override;
    virtual void scheduleWriteOperandsFromLoad(Wavefront *w,
                                               GPUDynInstPtr ii) override;
    virtual void waveExecuteInst(Wavefront *w, GPUDynInstPtr ii) override;
 
    void
    setParent(ComputeUnit *_computeUnit) override
    {
        RegisterFile::setParent(_computeUnit);
    }
 
    // Read a register that is writeable (e.g., a DST operand)
    VecRegContainer&
    readWriteable(int regIdx)
    {
        return regFile[regIdx];
    }
 
    // Read a register that is not writeable (e.g., src operand)
    const VecRegContainer&
    read(int regIdx) const
    {
        return regFile[regIdx];
    }
 
    // Write a register
    void
    write(int regIdx, const VecRegContainer &value)
    {
        regFile[regIdx] = value;
    }
 
    void
    printReg(Wavefront *wf, int regIdx) const
    {
#ifndef NDEBUG
        const auto &vec_reg_cont = regFile[regIdx];
        auto vgpr = vec_reg_cont.as<TheGpuISA::VecElemU32>();
 
        for (int lane = 0; lane < TheGpuISA::NumVecElemPerVecReg; ++lane) {
            if (wf->execMask(lane)) {
                DPRINTF(GPUVRF, "WF[%d][%d]: WV[%d] v[%d][%d] = %#x\n",
                    wf->simdId, wf->wfSlotId, wf->wfDynId, regIdx, lane,
                    vgpr[lane]);
                DPRINTF(GPUTrace, "WF[%d][%d]: WV[%d] v[%d][%d] = %#x (%f)\n",
                    wf->simdId, wf->wfSlotId, wf->wfDynId, regIdx, lane,
                    vgpr[lane], *reinterpret_cast<const float*>(&vgpr[lane]));
            }
        }
#endif
    }
 
  private:
    std::vector<VecRegContainer> regFile;
};
 
} // namespace gem5
 
#endif // __VECTOR_REGISTER_FILE_HH__