gem5 [DEVELOP-FOR-25.1]
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vop3_cmp.cc
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1/*
2 * Copyright (c) 2024 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include "arch/amdgpu/vega/insts/inst_util.hh"
33#include "arch/amdgpu/vega/insts/instructions.hh"
34
35namespace gem5
36{
37
38namespace VegaISA
39{
40 // --- Inst_VOP3__V_CMP_CLASS_F32 class methods ---
41
42 Inst_VOP3__V_CMP_CLASS_F32::Inst_VOP3__V_CMP_CLASS_F32(
43 InFmt_VOP3A *iFmt)
44 : Inst_VOP3A(iFmt, "v_cmp_class_f32", true)
45 {
46 setFlag(ALU);
47 setFlag(F32);
48 } // Inst_VOP3__V_CMP_CLASS_F32
49
50 Inst_VOP3__V_CMP_CLASS_F32::~Inst_VOP3__V_CMP_CLASS_F32()
51 {
52 } // ~Inst_VOP3__V_CMP_CLASS_F32
53
54 // --- description from .arch file ---
55 // VCC = IEEE numeric class function specified in S1.u, performed on S0.f
56 // The function reports true if the floating point value is *any* of the
57 // --- numeric types selected in S1.u according to the following list:
58 // S1.u[0] -- value is a signaling NaN.
59 // S1.u[1] -- value is a quiet NaN.
60 // S1.u[2] -- value is negative infinity.
61 // S1.u[3] -- value is a negative normal value.
62 // S1.u[4] -- value is a negative denormal value.
63 // S1.u[5] -- value is negative zero.
64 // S1.u[6] -- value is positive zero.
65 // S1.u[7] -- value is a positive denormal value.
66 // S1.u[8] -- value is a positive normal value.
67 // S1.u[9] -- value is positive infinity.
68 void
69 Inst_VOP3__V_CMP_CLASS_F32::execute(GPUDynInstPtr gpuDynInst)
70 {
71 Wavefront *wf = gpuDynInst->wavefront();
72 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
73 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
74 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
75
76 src0.readSrc();
77 src1.readSrc();
78
79 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
80 if (wf->execMask(lane)) {
81 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
82 // is NaN
83 if (std::isnan(src0[lane])) {
84 sdst.setBit(lane, 1);
85 continue;
86 }
87 }
88 if (bits(src1[lane], 2)) {
89 // is -infinity
90 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
91 sdst.setBit(lane, 1);
92 continue;
93 }
94 }
95 if (bits(src1[lane], 3)) {
96 // is -normal
97 if (std::isnormal(src0[lane])
98 && std::signbit(src0[lane])) {
99 sdst.setBit(lane, 1);
100 continue;
101 }
102 }
103 if (bits(src1[lane], 4)) {
104 // is -denormal
105 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
106 && std::signbit(src0[lane])) {
107 sdst.setBit(lane, 1);
108 continue;
109 }
110 }
111 if (bits(src1[lane], 5)) {
112 // is -zero
113 if (std::fpclassify(src0[lane]) == FP_ZERO
114 && std::signbit(src0[lane])) {
115 sdst.setBit(lane, 1);
116 continue;
117 }
118 }
119 if (bits(src1[lane], 6)) {
120 // is +zero
121 if (std::fpclassify(src0[lane]) == FP_ZERO
122 && !std::signbit(src0[lane])) {
123 sdst.setBit(lane, 1);
124 continue;
125 }
126 }
127 if (bits(src1[lane], 7)) {
128 // is +denormal
129 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
130 && !std::signbit(src0[lane])) {
131 sdst.setBit(lane, 1);
132 continue;
133 }
134 }
135 if (bits(src1[lane], 8)) {
136 // is +normal
137 if (std::isnormal(src0[lane])
138 && !std::signbit(src0[lane])) {
139 sdst.setBit(lane, 1);
140 continue;
141 }
142 }
143 if (bits(src1[lane], 9)) {
144 // is +infinity
145 if (std::isinf(src0[lane])
146 && !std::signbit(src0[lane])) {
147 sdst.setBit(lane, 1);
148 continue;
149 }
150 }
151 }
152 }
153
154 sdst.write();
155 } // execute
156 // --- Inst_VOP3__V_CMPX_CLASS_F32 class methods ---
157
158 Inst_VOP3__V_CMPX_CLASS_F32::Inst_VOP3__V_CMPX_CLASS_F32(
159 InFmt_VOP3A *iFmt)
160 : Inst_VOP3A(iFmt, "v_cmpx_class_f32", true)
161 {
162 setFlag(ALU);
163 setFlag(F32);
164 setFlag(WritesEXEC);
165 } // Inst_VOP3__V_CMPX_CLASS_F32
166
167 Inst_VOP3__V_CMPX_CLASS_F32::~Inst_VOP3__V_CMPX_CLASS_F32()
168 {
169 } // ~Inst_VOP3__V_CMPX_CLASS_F32
170
171 // --- description from .arch file ---
172 // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
173 // S0.f
174 // The function reports true if the floating point value is *any* of the
175 // numeric types selected in S1.u according to the following list:
176 // S1.u[0] -- value is a signaling NaN.
177 // S1.u[1] -- value is a quiet NaN.
178 // S1.u[2] -- value is negative infinity.
179 // S1.u[3] -- value is a negative normal value.
180 // S1.u[4] -- value is a negative denormal value.
181 // S1.u[5] -- value is negative zero.
182 // S1.u[6] -- value is positive zero.
183 // S1.u[7] -- value is a positive denormal value.
184 // S1.u[8] -- value is a positive normal value.
185 // S1.u[9] -- value is positive infinity.
186 void
187 Inst_VOP3__V_CMPX_CLASS_F32::execute(GPUDynInstPtr gpuDynInst)
188 {
189 Wavefront *wf = gpuDynInst->wavefront();
190 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
191 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
192 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
193
194 src0.readSrc();
195 src1.readSrc();
196
197 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
198 if (wf->execMask(lane)) {
199 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
200 // is NaN
201 if (std::isnan(src0[lane])) {
202 sdst.setBit(lane, 1);
203 continue;
204 }
205 }
206 if (bits(src1[lane], 2)) {
207 // is -infinity
208 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
209 sdst.setBit(lane, 1);
210 continue;
211 }
212 }
213 if (bits(src1[lane], 3)) {
214 // is -normal
215 if (std::isnormal(src0[lane])
216 && std::signbit(src0[lane])) {
217 sdst.setBit(lane, 1);
218 continue;
219 }
220 }
221 if (bits(src1[lane], 4)) {
222 // is -denormal
223 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
224 && std::signbit(src0[lane])) {
225 sdst.setBit(lane, 1);
226 continue;
227 }
228 }
229 if (bits(src1[lane], 5)) {
230 // is -zero
231 if (std::fpclassify(src0[lane]) == FP_ZERO
232 && std::signbit(src0[lane])) {
233 sdst.setBit(lane, 1);
234 continue;
235 }
236 }
237 if (bits(src1[lane], 6)) {
238 // is +zero
239 if (std::fpclassify(src0[lane]) == FP_ZERO
240 && !std::signbit(src0[lane])) {
241 sdst.setBit(lane, 1);
242 continue;
243 }
244 }
245 if (bits(src1[lane], 7)) {
246 // is +denormal
247 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
248 && !std::signbit(src0[lane])) {
249 sdst.setBit(lane, 1);
250 continue;
251 }
252 }
253 if (bits(src1[lane], 8)) {
254 // is +normal
255 if (std::isnormal(src0[lane])
256 && !std::signbit(src0[lane])) {
257 sdst.setBit(lane, 1);
258 continue;
259 }
260 }
261 if (bits(src1[lane], 9)) {
262 // is +infinity
263 if (std::isinf(src0[lane])
264 && !std::signbit(src0[lane])) {
265 sdst.setBit(lane, 1);
266 continue;
267 }
268 }
269 }
270 }
271
272 wf->execMask() = sdst.rawData();
273 sdst.write();
274 } // execute
275 // --- Inst_VOP3__V_CMP_CLASS_F64 class methods ---
276
277 Inst_VOP3__V_CMP_CLASS_F64::Inst_VOP3__V_CMP_CLASS_F64(
278 InFmt_VOP3A *iFmt)
279 : Inst_VOP3A(iFmt, "v_cmp_class_f64", true)
280 {
281 setFlag(ALU);
282 setFlag(F64);
283 } // Inst_VOP3__V_CMP_CLASS_F64
284
285 Inst_VOP3__V_CMP_CLASS_F64::~Inst_VOP3__V_CMP_CLASS_F64()
286 {
287 } // ~Inst_VOP3__V_CMP_CLASS_F64
288
289 // --- description from .arch file ---
290 // VCC = IEEE numeric class function specified in S1.u, performed on S0.d
291 // The function reports true if the floating point value is *any* of the
292 // --- numeric types selected in S1.u according to the following list:
293 // S1.u[0] -- value is a signaling NaN.
294 // S1.u[1] -- value is a quiet NaN.
295 // S1.u[2] -- value is negative infinity.
296 // S1.u[3] -- value is a negative normal value.
297 // S1.u[4] -- value is a negative denormal value.
298 // S1.u[5] -- value is negative zero.
299 // S1.u[6] -- value is positive zero.
300 // S1.u[7] -- value is a positive denormal value.
301 // S1.u[8] -- value is a positive normal value.
302 // S1.u[9] -- value is positive infinity.
303 void
304 Inst_VOP3__V_CMP_CLASS_F64::execute(GPUDynInstPtr gpuDynInst)
305 {
306 Wavefront *wf = gpuDynInst->wavefront();
307 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
308 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
309 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
310
311 src0.readSrc();
312 src1.readSrc();
313
314 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
315 if (wf->execMask(lane)) {
316 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
317 // is NaN
318 if (std::isnan(src0[lane])) {
319 sdst.setBit(lane, 1);
320 continue;
321 }
322 }
323 if (bits(src1[lane], 2)) {
324 // is -infinity
325 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
326 sdst.setBit(lane, 1);
327 continue;
328 }
329 }
330 if (bits(src1[lane], 3)) {
331 // is -normal
332 if (std::isnormal(src0[lane])
333 && std::signbit(src0[lane])) {
334 sdst.setBit(lane, 1);
335 continue;
336 }
337 }
338 if (bits(src1[lane], 4)) {
339 // is -denormal
340 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
341 && std::signbit(src0[lane])) {
342 sdst.setBit(lane, 1);
343 continue;
344 }
345 }
346 if (bits(src1[lane], 5)) {
347 // is -zero
348 if (std::fpclassify(src0[lane]) == FP_ZERO
349 && std::signbit(src0[lane])) {
350 sdst.setBit(lane, 1);
351 continue;
352 }
353 }
354 if (bits(src1[lane], 6)) {
355 // is +zero
356 if (std::fpclassify(src0[lane]) == FP_ZERO
357 && !std::signbit(src0[lane])) {
358 sdst.setBit(lane, 1);
359 continue;
360 }
361 }
362 if (bits(src1[lane], 7)) {
363 // is +denormal
364 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
365 && !std::signbit(src0[lane])) {
366 sdst.setBit(lane, 1);
367 continue;
368 }
369 }
370 if (bits(src1[lane], 8)) {
371 // is +normal
372 if (std::isnormal(src0[lane])
373 && !std::signbit(src0[lane])) {
374 sdst.setBit(lane, 1);
375 continue;
376 }
377 }
378 if (bits(src1[lane], 9)) {
379 // is +infinity
380 if (std::isinf(src0[lane])
381 && !std::signbit(src0[lane])) {
382 sdst.setBit(lane, 1);
383 continue;
384 }
385 }
386 }
387 }
388
389 sdst.write();
390 } // execute
391 // --- Inst_VOP3__V_CMPX_CLASS_F64 class methods ---
392
393 Inst_VOP3__V_CMPX_CLASS_F64::Inst_VOP3__V_CMPX_CLASS_F64(
394 InFmt_VOP3A *iFmt)
395 : Inst_VOP3A(iFmt, "v_cmpx_class_f64", true)
396 {
397 setFlag(ALU);
398 setFlag(F64);
399 setFlag(WritesEXEC);
400 } // Inst_VOP3__V_CMPX_CLASS_F64
401
402 Inst_VOP3__V_CMPX_CLASS_F64::~Inst_VOP3__V_CMPX_CLASS_F64()
403 {
404 } // ~Inst_VOP3__V_CMPX_CLASS_F64
405
406 // --- description from .arch file ---
407 // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
408 // S0.d
409 // The function reports true if the floating point value is *any* of the
410 // numeric types selected in S1.u according to the following list:
411 // S1.u[0] -- value is a signaling NaN.
412 // S1.u[1] -- value is a quiet NaN.
413 // S1.u[2] -- value is negative infinity.
414 // S1.u[3] -- value is a negative normal value.
415 // S1.u[4] -- value is a negative denormal value.
416 // S1.u[5] -- value is negative zero.
417 // S1.u[6] -- value is positive zero.
418 // S1.u[7] -- value is a positive denormal value.
419 // S1.u[8] -- value is a positive normal value.
420 // S1.u[9] -- value is positive infinity.
421 void
422 Inst_VOP3__V_CMPX_CLASS_F64::execute(GPUDynInstPtr gpuDynInst)
423 {
424 Wavefront *wf = gpuDynInst->wavefront();
425 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
426 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
427 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
428
429 src0.readSrc();
430 src1.readSrc();
431
432 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
433 if (wf->execMask(lane)) {
434 if (bits(src1[lane], 0) || bits(src1[lane], 1)) {
435 // is NaN
436 if (std::isnan(src0[lane])) {
437 sdst.setBit(lane, 1);
438 continue;
439 }
440 }
441 if (bits(src1[lane], 2)) {
442 // is -infinity
443 if (std::isinf(src0[lane]) && std::signbit(src0[lane])) {
444 sdst.setBit(lane, 1);
445 continue;
446 }
447 }
448 if (bits(src1[lane], 3)) {
449 // is -normal
450 if (std::isnormal(src0[lane])
451 && std::signbit(src0[lane])) {
452 sdst.setBit(lane, 1);
453 continue;
454 }
455 }
456 if (bits(src1[lane], 4)) {
457 // is -denormal
458 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
459 && std::signbit(src0[lane])) {
460 sdst.setBit(lane, 1);
461 continue;
462 }
463 }
464 if (bits(src1[lane], 5)) {
465 // is -zero
466 if (std::fpclassify(src0[lane]) == FP_ZERO
467 && std::signbit(src0[lane])) {
468 sdst.setBit(lane, 1);
469 continue;
470 }
471 }
472 if (bits(src1[lane], 6)) {
473 // is +zero
474 if (std::fpclassify(src0[lane]) == FP_ZERO
475 && !std::signbit(src0[lane])) {
476 sdst.setBit(lane, 1);
477 continue;
478 }
479 }
480 if (bits(src1[lane], 7)) {
481 // is +denormal
482 if (std::fpclassify(src0[lane]) == FP_SUBNORMAL
483 && !std::signbit(src0[lane])) {
484 sdst.setBit(lane, 1);
485 continue;
486 }
487 }
488 if (bits(src1[lane], 8)) {
489 // is +normal
490 if (std::isnormal(src0[lane])
491 && !std::signbit(src0[lane])) {
492 sdst.setBit(lane, 1);
493 continue;
494 }
495 }
496 if (bits(src1[lane], 9)) {
497 // is +infinity
498 if (std::isinf(src0[lane])
499 && !std::signbit(src0[lane])) {
500 sdst.setBit(lane, 1);
501 continue;
502 }
503 }
504 }
505 }
506
507 wf->execMask() = sdst.rawData();
508 sdst.write();
509 } // execute
510 // --- Inst_VOP3__V_CMP_CLASS_F16 class methods ---
511
512 Inst_VOP3__V_CMP_CLASS_F16::Inst_VOP3__V_CMP_CLASS_F16(
513 InFmt_VOP3A *iFmt)
514 : Inst_VOP3A(iFmt, "v_cmp_class_f16", true)
515 {
516 setFlag(ALU);
517 setFlag(F16);
518 } // Inst_VOP3__V_CMP_CLASS_F16
519
520 Inst_VOP3__V_CMP_CLASS_F16::~Inst_VOP3__V_CMP_CLASS_F16()
521 {
522 } // ~Inst_VOP3__V_CMP_CLASS_F16
523
524 // --- description from .arch file ---
525 // VCC = IEEE numeric class function specified in S1.u, performed on S0.f16
526 // The function reports true if the floating point value is *any* of the
527 // --- numeric types selected in S1.u according to the following list:
528 // S1.u[0] -- value is a signaling NaN.
529 // S1.u[1] -- value is a quiet NaN.
530 // S1.u[2] -- value is negative infinity.
531 // S1.u[3] -- value is a negative normal value.
532 // S1.u[4] -- value is a negative denormal value.
533 // S1.u[5] -- value is negative zero.
534 // S1.u[6] -- value is positive zero.
535 // S1.u[7] -- value is a positive denormal value.
536 // S1.u[8] -- value is a positive normal value.
537 // S1.u[9] -- value is positive infinity.
538 void
543 // --- Inst_VOP3__V_CMPX_CLASS_F16 class methods ---
544
545 Inst_VOP3__V_CMPX_CLASS_F16::Inst_VOP3__V_CMPX_CLASS_F16(
546 InFmt_VOP3A *iFmt)
547 : Inst_VOP3A(iFmt, "v_cmpx_class_f16", true)
548 {
549 setFlag(ALU);
550 setFlag(F16);
551 setFlag(WritesEXEC);
552 } // Inst_VOP3__V_CMPX_CLASS_F16
553
554 Inst_VOP3__V_CMPX_CLASS_F16::~Inst_VOP3__V_CMPX_CLASS_F16()
555 {
556 } // ~Inst_VOP3__V_CMPX_CLASS_F16
557
558 // --- description from .arch file ---
559 // EXEC, VCC = IEEE numeric class function specified in S1.u, performed on
560 // --- S0.f16
561 // The function reports true if the floating point value is *any* of the
562 // --- numeric types selected in S1.u according to the following list:
563 // S1.u[0] -- value is a signaling NaN.
564 // S1.u[1] -- value is a quiet NaN.
565 // S1.u[2] -- value is negative infinity.
566 // S1.u[3] -- value is a negative normal value.
567 // S1.u[4] -- value is a negative denormal value.
568 // S1.u[5] -- value is negative zero.
569 // S1.u[6] -- value is positive zero.
570 // S1.u[7] -- value is a positive denormal value.
571 // S1.u[8] -- value is a positive normal value.
572 // S1.u[9] -- value is positive infinity.
573 void
578 // --- Inst_VOP3__V_CMP_F_F16 class methods ---
579
580 Inst_VOP3__V_CMP_F_F16::Inst_VOP3__V_CMP_F_F16(InFmt_VOP3A *iFmt)
581 : Inst_VOP3A(iFmt, "v_cmp_f_f16", true)
582 {
583 setFlag(ALU);
584 setFlag(F16);
585 } // Inst_VOP3__V_CMP_F_F16
586
587 Inst_VOP3__V_CMP_F_F16::~Inst_VOP3__V_CMP_F_F16()
588 {
589 } // ~Inst_VOP3__V_CMP_F_F16
590
591 // --- description from .arch file ---
592 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
593 void
594 Inst_VOP3__V_CMP_F_F16::execute(GPUDynInstPtr gpuDynInst)
595 {
596 panicUnimplemented();
597 } // execute
598 // --- Inst_VOP3__V_CMP_LT_F16 class methods ---
599
600 Inst_VOP3__V_CMP_LT_F16::Inst_VOP3__V_CMP_LT_F16(
601 InFmt_VOP3A *iFmt)
602 : Inst_VOP3A(iFmt, "v_cmp_lt_f16", true)
603 {
604 setFlag(ALU);
605 setFlag(F16);
606 } // Inst_VOP3__V_CMP_LT_F16
607
608 Inst_VOP3__V_CMP_LT_F16::~Inst_VOP3__V_CMP_LT_F16()
609 {
610 } // ~Inst_VOP3__V_CMP_LT_F16
611
612 // --- description from .arch file ---
613 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
614 void
615 Inst_VOP3__V_CMP_LT_F16::execute(GPUDynInstPtr gpuDynInst)
616 {
617 panicUnimplemented();
618 } // execute
619 // --- Inst_VOP3__V_CMP_EQ_F16 class methods ---
620
621 Inst_VOP3__V_CMP_EQ_F16::Inst_VOP3__V_CMP_EQ_F16(
622 InFmt_VOP3A *iFmt)
623 : Inst_VOP3A(iFmt, "v_cmp_eq_f16", true)
624 {
625 setFlag(ALU);
626 setFlag(F16);
627 } // Inst_VOP3__V_CMP_EQ_F16
628
629 Inst_VOP3__V_CMP_EQ_F16::~Inst_VOP3__V_CMP_EQ_F16()
630 {
631 } // ~Inst_VOP3__V_CMP_EQ_F16
632
633 // --- description from .arch file ---
634 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
635 void
636 Inst_VOP3__V_CMP_EQ_F16::execute(GPUDynInstPtr gpuDynInst)
637 {
638 panicUnimplemented();
639 } // execute
640 // --- Inst_VOP3__V_CMP_LE_F16 class methods ---
641
642 Inst_VOP3__V_CMP_LE_F16::Inst_VOP3__V_CMP_LE_F16(
643 InFmt_VOP3A *iFmt)
644 : Inst_VOP3A(iFmt, "v_cmp_le_f16", true)
645 {
646 setFlag(ALU);
647 setFlag(F16);
648 } // Inst_VOP3__V_CMP_LE_F16
649
650 Inst_VOP3__V_CMP_LE_F16::~Inst_VOP3__V_CMP_LE_F16()
651 {
652 } // ~Inst_VOP3__V_CMP_LE_F16
653
654 // --- description from .arch file ---
655 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
656 void
657 Inst_VOP3__V_CMP_LE_F16::execute(GPUDynInstPtr gpuDynInst)
658 {
659 panicUnimplemented();
660 } // execute
661 // --- Inst_VOP3__V_CMP_GT_F16 class methods ---
662
663 Inst_VOP3__V_CMP_GT_F16::Inst_VOP3__V_CMP_GT_F16(
664 InFmt_VOP3A *iFmt)
665 : Inst_VOP3A(iFmt, "v_cmp_gt_f16", true)
666 {
667 setFlag(ALU);
668 setFlag(F16);
669 } // Inst_VOP3__V_CMP_GT_F16
670
671 Inst_VOP3__V_CMP_GT_F16::~Inst_VOP3__V_CMP_GT_F16()
672 {
673 } // ~Inst_VOP3__V_CMP_GT_F16
674
675 // --- description from .arch file ---
676 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
677 void
678 Inst_VOP3__V_CMP_GT_F16::execute(GPUDynInstPtr gpuDynInst)
679 {
680 panicUnimplemented();
681 } // execute
682 // --- Inst_VOP3__V_CMP_LG_F16 class methods ---
683
684 Inst_VOP3__V_CMP_LG_F16::Inst_VOP3__V_CMP_LG_F16(
685 InFmt_VOP3A *iFmt)
686 : Inst_VOP3A(iFmt, "v_cmp_lg_f16", true)
687 {
688 setFlag(ALU);
689 setFlag(F16);
690 } // Inst_VOP3__V_CMP_LG_F16
691
692 Inst_VOP3__V_CMP_LG_F16::~Inst_VOP3__V_CMP_LG_F16()
693 {
694 } // ~Inst_VOP3__V_CMP_LG_F16
695
696 // --- description from .arch file ---
697 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
698 void
699 Inst_VOP3__V_CMP_LG_F16::execute(GPUDynInstPtr gpuDynInst)
700 {
701 panicUnimplemented();
702 } // execute
703 // --- Inst_VOP3__V_CMP_GE_F16 class methods ---
704
705 Inst_VOP3__V_CMP_GE_F16::Inst_VOP3__V_CMP_GE_F16(
706 InFmt_VOP3A *iFmt)
707 : Inst_VOP3A(iFmt, "v_cmp_ge_f16", true)
708 {
709 setFlag(ALU);
710 setFlag(F16);
711 } // Inst_VOP3__V_CMP_GE_F16
712
713 Inst_VOP3__V_CMP_GE_F16::~Inst_VOP3__V_CMP_GE_F16()
714 {
715 } // ~Inst_VOP3__V_CMP_GE_F16
716
717 // --- description from .arch file ---
718 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
719 void
720 Inst_VOP3__V_CMP_GE_F16::execute(GPUDynInstPtr gpuDynInst)
721 {
722 panicUnimplemented();
723 } // execute
724 // --- Inst_VOP3__V_CMP_O_F16 class methods ---
725
726 Inst_VOP3__V_CMP_O_F16::Inst_VOP3__V_CMP_O_F16(InFmt_VOP3A *iFmt)
727 : Inst_VOP3A(iFmt, "v_cmp_o_f16", true)
728 {
729 setFlag(ALU);
730 setFlag(F16);
731 } // Inst_VOP3__V_CMP_O_F16
732
733 Inst_VOP3__V_CMP_O_F16::~Inst_VOP3__V_CMP_O_F16()
734 {
735 } // ~Inst_VOP3__V_CMP_O_F16
736
737 // --- description from .arch file ---
738 // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
739 void
740 Inst_VOP3__V_CMP_O_F16::execute(GPUDynInstPtr gpuDynInst)
741 {
742 panicUnimplemented();
743 } // execute
744 // --- Inst_VOP3__V_CMP_U_F16 class methods ---
745
746 Inst_VOP3__V_CMP_U_F16::Inst_VOP3__V_CMP_U_F16(InFmt_VOP3A *iFmt)
747 : Inst_VOP3A(iFmt, "v_cmp_u_f16", true)
748 {
749 setFlag(ALU);
750 setFlag(F16);
751 } // Inst_VOP3__V_CMP_U_F16
752
753 Inst_VOP3__V_CMP_U_F16::~Inst_VOP3__V_CMP_U_F16()
754 {
755 } // ~Inst_VOP3__V_CMP_U_F16
756
757 // --- description from .arch file ---
758 // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
759 void
760 Inst_VOP3__V_CMP_U_F16::execute(GPUDynInstPtr gpuDynInst)
761 {
762 panicUnimplemented();
763 } // execute
764 // --- Inst_VOP3__V_CMP_NGE_F16 class methods ---
765
766 Inst_VOP3__V_CMP_NGE_F16::Inst_VOP3__V_CMP_NGE_F16(
767 InFmt_VOP3A *iFmt)
768 : Inst_VOP3A(iFmt, "v_cmp_nge_f16", true)
769 {
770 setFlag(ALU);
771 setFlag(F16);
772 } // Inst_VOP3__V_CMP_NGE_F16
773
774 Inst_VOP3__V_CMP_NGE_F16::~Inst_VOP3__V_CMP_NGE_F16()
775 {
776 } // ~Inst_VOP3__V_CMP_NGE_F16
777
778 // --- description from .arch file ---
779 // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
780 void
781 Inst_VOP3__V_CMP_NGE_F16::execute(GPUDynInstPtr gpuDynInst)
782 {
783 panicUnimplemented();
784 } // execute
785 // --- Inst_VOP3__V_CMP_NLG_F16 class methods ---
786
787 Inst_VOP3__V_CMP_NLG_F16::Inst_VOP3__V_CMP_NLG_F16(
788 InFmt_VOP3A *iFmt)
789 : Inst_VOP3A(iFmt, "v_cmp_nlg_f16", true)
790 {
791 setFlag(ALU);
792 setFlag(F16);
793 } // Inst_VOP3__V_CMP_NLG_F16
794
795 Inst_VOP3__V_CMP_NLG_F16::~Inst_VOP3__V_CMP_NLG_F16()
796 {
797 } // ~Inst_VOP3__V_CMP_NLG_F16
798
799 // --- description from .arch file ---
800 // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
801 void
802 Inst_VOP3__V_CMP_NLG_F16::execute(GPUDynInstPtr gpuDynInst)
803 {
804 panicUnimplemented();
805 } // execute
806 // --- Inst_VOP3__V_CMP_NGT_F16 class methods ---
807
808 Inst_VOP3__V_CMP_NGT_F16::Inst_VOP3__V_CMP_NGT_F16(
809 InFmt_VOP3A *iFmt)
810 : Inst_VOP3A(iFmt, "v_cmp_ngt_f16", true)
811 {
812 setFlag(ALU);
813 setFlag(F16);
814 } // Inst_VOP3__V_CMP_NGT_F16
815
816 Inst_VOP3__V_CMP_NGT_F16::~Inst_VOP3__V_CMP_NGT_F16()
817 {
818 } // ~Inst_VOP3__V_CMP_NGT_F16
819
820 // --- description from .arch file ---
821 // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
822 void
823 Inst_VOP3__V_CMP_NGT_F16::execute(GPUDynInstPtr gpuDynInst)
824 {
825 panicUnimplemented();
826 } // execute
827 // --- Inst_VOP3__V_CMP_NLE_F16 class methods ---
828
829 Inst_VOP3__V_CMP_NLE_F16::Inst_VOP3__V_CMP_NLE_F16(
830 InFmt_VOP3A *iFmt)
831 : Inst_VOP3A(iFmt, "v_cmp_nle_f16", true)
832 {
833 setFlag(ALU);
834 setFlag(F16);
835 } // Inst_VOP3__V_CMP_NLE_F16
836
837 Inst_VOP3__V_CMP_NLE_F16::~Inst_VOP3__V_CMP_NLE_F16()
838 {
839 } // ~Inst_VOP3__V_CMP_NLE_F16
840
841 // --- description from .arch file ---
842 // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
843 void
844 Inst_VOP3__V_CMP_NLE_F16::execute(GPUDynInstPtr gpuDynInst)
845 {
846 panicUnimplemented();
847 } // execute
848 // --- Inst_VOP3__V_CMP_NEQ_F16 class methods ---
849
850 Inst_VOP3__V_CMP_NEQ_F16::Inst_VOP3__V_CMP_NEQ_F16(
851 InFmt_VOP3A *iFmt)
852 : Inst_VOP3A(iFmt, "v_cmp_neq_f16", true)
853 {
854 setFlag(ALU);
855 setFlag(F16);
856 } // Inst_VOP3__V_CMP_NEQ_F16
857
858 Inst_VOP3__V_CMP_NEQ_F16::~Inst_VOP3__V_CMP_NEQ_F16()
859 {
860 } // ~Inst_VOP3__V_CMP_NEQ_F16
861
862 // --- description from .arch file ---
863 // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
864 void
865 Inst_VOP3__V_CMP_NEQ_F16::execute(GPUDynInstPtr gpuDynInst)
866 {
867 panicUnimplemented();
868 } // execute
869 // --- Inst_VOP3__V_CMP_NLT_F16 class methods ---
870
871 Inst_VOP3__V_CMP_NLT_F16::Inst_VOP3__V_CMP_NLT_F16(
872 InFmt_VOP3A *iFmt)
873 : Inst_VOP3A(iFmt, "v_cmp_nlt_f16", true)
874 {
875 setFlag(ALU);
876 setFlag(F16);
877 } // Inst_VOP3__V_CMP_NLT_F16
878
879 Inst_VOP3__V_CMP_NLT_F16::~Inst_VOP3__V_CMP_NLT_F16()
880 {
881 } // ~Inst_VOP3__V_CMP_NLT_F16
882
883 // --- description from .arch file ---
884 // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
885 void
886 Inst_VOP3__V_CMP_NLT_F16::execute(GPUDynInstPtr gpuDynInst)
887 {
888 panicUnimplemented();
889 } // execute
890 // --- Inst_VOP3__V_CMP_TRU_F16 class methods ---
891
892 Inst_VOP3__V_CMP_TRU_F16::Inst_VOP3__V_CMP_TRU_F16(
893 InFmt_VOP3A *iFmt)
894 : Inst_VOP3A(iFmt, "v_cmp_tru_f16", true)
895 {
896 setFlag(ALU);
897 setFlag(F16);
898 } // Inst_VOP3__V_CMP_TRU_F16
899
900 Inst_VOP3__V_CMP_TRU_F16::~Inst_VOP3__V_CMP_TRU_F16()
901 {
902 } // ~Inst_VOP3__V_CMP_TRU_F16
903
904 // --- description from .arch file ---
905 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
906 void
907 Inst_VOP3__V_CMP_TRU_F16::execute(GPUDynInstPtr gpuDynInst)
908 {
909 Wavefront *wf = gpuDynInst->wavefront();
910 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
911
912 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
913 if (wf->execMask(lane)) {
914 sdst.setBit(lane, 1);
915 }
916 }
917
918 sdst.write();
919 } // execute
920 // --- Inst_VOP3__V_CMPX_F_F16 class methods ---
921
922 Inst_VOP3__V_CMPX_F_F16::Inst_VOP3__V_CMPX_F_F16(
923 InFmt_VOP3A *iFmt)
924 : Inst_VOP3A(iFmt, "v_cmpx_f_f16", true)
925 {
926 setFlag(ALU);
927 setFlag(WritesEXEC);
928 } // Inst_VOP3__V_CMPX_F_F16
929
930 Inst_VOP3__V_CMPX_F_F16::~Inst_VOP3__V_CMPX_F_F16()
931 {
932 } // ~Inst_VOP3__V_CMPX_F_F16
933
934 // --- description from .arch file ---
935 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
936 void
937 Inst_VOP3__V_CMPX_F_F16::execute(GPUDynInstPtr gpuDynInst)
938 {
939 Wavefront *wf = gpuDynInst->wavefront();
940 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
941
942 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
943 if (wf->execMask(lane)) {
944 sdst.setBit(lane, 0);
945 }
946 }
947
948 wf->execMask() = sdst.rawData();
949 sdst.write();
950 } // execute
951 // --- Inst_VOP3__V_CMPX_LT_F16 class methods ---
952
953 Inst_VOP3__V_CMPX_LT_F16::Inst_VOP3__V_CMPX_LT_F16(
954 InFmt_VOP3A *iFmt)
955 : Inst_VOP3A(iFmt, "v_cmpx_lt_f16", true)
956 {
957 setFlag(ALU);
958 setFlag(F16);
959 setFlag(WritesEXEC);
960 } // Inst_VOP3__V_CMPX_LT_F16
961
962 Inst_VOP3__V_CMPX_LT_F16::~Inst_VOP3__V_CMPX_LT_F16()
963 {
964 } // ~Inst_VOP3__V_CMPX_LT_F16
965
966 // --- description from .arch file ---
967 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
968 void
969 Inst_VOP3__V_CMPX_LT_F16::execute(GPUDynInstPtr gpuDynInst)
970 {
971 panicUnimplemented();
972 } // execute
973 // --- Inst_VOP3__V_CMPX_EQ_F16 class methods ---
974
975 Inst_VOP3__V_CMPX_EQ_F16::Inst_VOP3__V_CMPX_EQ_F16(
976 InFmt_VOP3A *iFmt)
977 : Inst_VOP3A(iFmt, "v_cmpx_eq_f16", true)
978 {
979 setFlag(ALU);
980 setFlag(F16);
981 setFlag(WritesEXEC);
982 } // Inst_VOP3__V_CMPX_EQ_F16
983
984 Inst_VOP3__V_CMPX_EQ_F16::~Inst_VOP3__V_CMPX_EQ_F16()
985 {
986 } // ~Inst_VOP3__V_CMPX_EQ_F16
987
988 // --- description from .arch file ---
989 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
990 void
991 Inst_VOP3__V_CMPX_EQ_F16::execute(GPUDynInstPtr gpuDynInst)
992 {
993 panicUnimplemented();
994 } // execute
995 // --- Inst_VOP3__V_CMPX_LE_F16 class methods ---
996
997 Inst_VOP3__V_CMPX_LE_F16::Inst_VOP3__V_CMPX_LE_F16(
998 InFmt_VOP3A *iFmt)
999 : Inst_VOP3A(iFmt, "v_cmpx_le_f16", true)
1000 {
1001 setFlag(ALU);
1002 setFlag(F16);
1003 setFlag(WritesEXEC);
1004 } // Inst_VOP3__V_CMPX_LE_F16
1005
1006 Inst_VOP3__V_CMPX_LE_F16::~Inst_VOP3__V_CMPX_LE_F16()
1007 {
1008 } // ~Inst_VOP3__V_CMPX_LE_F16
1009
1010 // --- description from .arch file ---
1011 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
1012 void
1013 Inst_VOP3__V_CMPX_LE_F16::execute(GPUDynInstPtr gpuDynInst)
1014 {
1015 panicUnimplemented();
1016 } // execute
1017 // --- Inst_VOP3__V_CMPX_GT_F16 class methods ---
1018
1019 Inst_VOP3__V_CMPX_GT_F16::Inst_VOP3__V_CMPX_GT_F16(
1020 InFmt_VOP3A *iFmt)
1021 : Inst_VOP3A(iFmt, "v_cmpx_gt_f16", true)
1022 {
1023 setFlag(ALU);
1024 setFlag(F16);
1025 setFlag(WritesEXEC);
1026 } // Inst_VOP3__V_CMPX_GT_F16
1027
1028 Inst_VOP3__V_CMPX_GT_F16::~Inst_VOP3__V_CMPX_GT_F16()
1029 {
1030 } // ~Inst_VOP3__V_CMPX_GT_F16
1031
1032 // --- description from .arch file ---
1033 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
1034 void
1035 Inst_VOP3__V_CMPX_GT_F16::execute(GPUDynInstPtr gpuDynInst)
1036 {
1037 panicUnimplemented();
1038 } // execute
1039 // --- Inst_VOP3__V_CMPX_LG_F16 class methods ---
1040
1041 Inst_VOP3__V_CMPX_LG_F16::Inst_VOP3__V_CMPX_LG_F16(
1042 InFmt_VOP3A *iFmt)
1043 : Inst_VOP3A(iFmt, "v_cmpx_lg_f16", true)
1044 {
1045 setFlag(ALU);
1046 setFlag(F16);
1047 setFlag(WritesEXEC);
1048 } // Inst_VOP3__V_CMPX_LG_F16
1049
1050 Inst_VOP3__V_CMPX_LG_F16::~Inst_VOP3__V_CMPX_LG_F16()
1051 {
1052 } // ~Inst_VOP3__V_CMPX_LG_F16
1053
1054 // --- description from .arch file ---
1055 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
1056 void
1057 Inst_VOP3__V_CMPX_LG_F16::execute(GPUDynInstPtr gpuDynInst)
1058 {
1059 panicUnimplemented();
1060 } // execute
1061 // --- Inst_VOP3__V_CMPX_GE_F16 class methods ---
1062
1063 Inst_VOP3__V_CMPX_GE_F16::Inst_VOP3__V_CMPX_GE_F16(
1064 InFmt_VOP3A *iFmt)
1065 : Inst_VOP3A(iFmt, "v_cmpx_ge_f16", true)
1066 {
1067 setFlag(ALU);
1068 setFlag(F16);
1069 setFlag(WritesEXEC);
1070 } // Inst_VOP3__V_CMPX_GE_F16
1071
1072 Inst_VOP3__V_CMPX_GE_F16::~Inst_VOP3__V_CMPX_GE_F16()
1073 {
1074 } // ~Inst_VOP3__V_CMPX_GE_F16
1075
1076 // --- description from .arch file ---
1077 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
1078 void
1079 Inst_VOP3__V_CMPX_GE_F16::execute(GPUDynInstPtr gpuDynInst)
1080 {
1081 panicUnimplemented();
1082 } // execute
1083 // --- Inst_VOP3__V_CMPX_O_F16 class methods ---
1084
1085 Inst_VOP3__V_CMPX_O_F16::Inst_VOP3__V_CMPX_O_F16(
1086 InFmt_VOP3A *iFmt)
1087 : Inst_VOP3A(iFmt, "v_cmpx_o_f16", true)
1088 {
1089 setFlag(ALU);
1090 setFlag(F16);
1091 setFlag(WritesEXEC);
1092 } // Inst_VOP3__V_CMPX_O_F16
1093
1094 Inst_VOP3__V_CMPX_O_F16::~Inst_VOP3__V_CMPX_O_F16()
1095 {
1096 } // ~Inst_VOP3__V_CMPX_O_F16
1097
1098 // --- description from .arch file ---
1099 // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
1100 // encoding.
1101 void
1102 Inst_VOP3__V_CMPX_O_F16::execute(GPUDynInstPtr gpuDynInst)
1103 {
1104 panicUnimplemented();
1105 } // execute
1106 // --- Inst_VOP3__V_CMPX_U_F16 class methods ---
1107
1108 Inst_VOP3__V_CMPX_U_F16::Inst_VOP3__V_CMPX_U_F16(
1109 InFmt_VOP3A *iFmt)
1110 : Inst_VOP3A(iFmt, "v_cmpx_u_f16", true)
1111 {
1112 setFlag(ALU);
1113 setFlag(F16);
1114 setFlag(WritesEXEC);
1115 } // Inst_VOP3__V_CMPX_U_F16
1116
1117 Inst_VOP3__V_CMPX_U_F16::~Inst_VOP3__V_CMPX_U_F16()
1118 {
1119 } // ~Inst_VOP3__V_CMPX_U_F16
1120
1121 // --- description from .arch file ---
1122 // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
1123 // encoding.
1124 void
1125 Inst_VOP3__V_CMPX_U_F16::execute(GPUDynInstPtr gpuDynInst)
1126 {
1127 panicUnimplemented();
1128 } // execute
1129 // --- Inst_VOP3__V_CMPX_NGE_F16 class methods ---
1130
1131 Inst_VOP3__V_CMPX_NGE_F16::Inst_VOP3__V_CMPX_NGE_F16(
1132 InFmt_VOP3A *iFmt)
1133 : Inst_VOP3A(iFmt, "v_cmpx_nge_f16", true)
1134 {
1135 setFlag(ALU);
1136 setFlag(F16);
1137 setFlag(WritesEXEC);
1138 } // Inst_VOP3__V_CMPX_NGE_F16
1139
1140 Inst_VOP3__V_CMPX_NGE_F16::~Inst_VOP3__V_CMPX_NGE_F16()
1141 {
1142 } // ~Inst_VOP3__V_CMPX_NGE_F16
1143
1144 // --- description from .arch file ---
1145 // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
1146 void
1147 Inst_VOP3__V_CMPX_NGE_F16::execute(GPUDynInstPtr gpuDynInst)
1148 {
1149 panicUnimplemented();
1150 } // execute
1151 // --- Inst_VOP3__V_CMPX_NLG_F16 class methods ---
1152
1153 Inst_VOP3__V_CMPX_NLG_F16::Inst_VOP3__V_CMPX_NLG_F16(
1154 InFmt_VOP3A *iFmt)
1155 : Inst_VOP3A(iFmt, "v_cmpx_nlg_f16", true)
1156 {
1157 setFlag(ALU);
1158 setFlag(F16);
1159 setFlag(WritesEXEC);
1160 } // Inst_VOP3__V_CMPX_NLG_F16
1161
1162 Inst_VOP3__V_CMPX_NLG_F16::~Inst_VOP3__V_CMPX_NLG_F16()
1163 {
1164 } // ~Inst_VOP3__V_CMPX_NLG_F16
1165
1166 // --- description from .arch file ---
1167 // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
1168 void
1169 Inst_VOP3__V_CMPX_NLG_F16::execute(GPUDynInstPtr gpuDynInst)
1170 {
1171 panicUnimplemented();
1172 } // execute
1173 // --- Inst_VOP3__V_CMPX_NGT_F16 class methods ---
1174
1175 Inst_VOP3__V_CMPX_NGT_F16::Inst_VOP3__V_CMPX_NGT_F16(
1176 InFmt_VOP3A *iFmt)
1177 : Inst_VOP3A(iFmt, "v_cmpx_ngt_f16", true)
1178 {
1179 setFlag(ALU);
1180 setFlag(F16);
1181 setFlag(WritesEXEC);
1182 } // Inst_VOP3__V_CMPX_NGT_F16
1183
1184 Inst_VOP3__V_CMPX_NGT_F16::~Inst_VOP3__V_CMPX_NGT_F16()
1185 {
1186 } // ~Inst_VOP3__V_CMPX_NGT_F16
1187
1188 // --- description from .arch file ---
1189 // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
1190 void
1191 Inst_VOP3__V_CMPX_NGT_F16::execute(GPUDynInstPtr gpuDynInst)
1192 {
1193 panicUnimplemented();
1194 } // execute
1195 // --- Inst_VOP3__V_CMPX_NLE_F16 class methods ---
1196
1197 Inst_VOP3__V_CMPX_NLE_F16::Inst_VOP3__V_CMPX_NLE_F16(
1198 InFmt_VOP3A *iFmt)
1199 : Inst_VOP3A(iFmt, "v_cmpx_nle_f16", true)
1200 {
1201 setFlag(ALU);
1202 setFlag(F16);
1203 setFlag(WritesEXEC);
1204 } // Inst_VOP3__V_CMPX_NLE_F16
1205
1206 Inst_VOP3__V_CMPX_NLE_F16::~Inst_VOP3__V_CMPX_NLE_F16()
1207 {
1208 } // ~Inst_VOP3__V_CMPX_NLE_F16
1209
1210 // --- description from .arch file ---
1211 // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
1212 void
1213 Inst_VOP3__V_CMPX_NLE_F16::execute(GPUDynInstPtr gpuDynInst)
1214 {
1215 panicUnimplemented();
1216 } // execute
1217 // --- Inst_VOP3__V_CMPX_NEQ_F16 class methods ---
1218
1219 Inst_VOP3__V_CMPX_NEQ_F16::Inst_VOP3__V_CMPX_NEQ_F16(
1220 InFmt_VOP3A *iFmt)
1221 : Inst_VOP3A(iFmt, "v_cmpx_neq_f16", true)
1222 {
1223 setFlag(ALU);
1224 setFlag(F16);
1225 setFlag(WritesEXEC);
1226 } // Inst_VOP3__V_CMPX_NEQ_F16
1227
1228 Inst_VOP3__V_CMPX_NEQ_F16::~Inst_VOP3__V_CMPX_NEQ_F16()
1229 {
1230 } // ~Inst_VOP3__V_CMPX_NEQ_F16
1231
1232 // --- description from .arch file ---
1233 // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
1234 void
1235 Inst_VOP3__V_CMPX_NEQ_F16::execute(GPUDynInstPtr gpuDynInst)
1236 {
1237 panicUnimplemented();
1238 } // execute
1239 // --- Inst_VOP3__V_CMPX_NLT_F16 class methods ---
1240
1241 Inst_VOP3__V_CMPX_NLT_F16::Inst_VOP3__V_CMPX_NLT_F16(
1242 InFmt_VOP3A *iFmt)
1243 : Inst_VOP3A(iFmt, "v_cmpx_nlt_f16", true)
1244 {
1245 setFlag(ALU);
1246 setFlag(F16);
1247 setFlag(WritesEXEC);
1248 } // Inst_VOP3__V_CMPX_NLT_F16
1249
1250 Inst_VOP3__V_CMPX_NLT_F16::~Inst_VOP3__V_CMPX_NLT_F16()
1251 {
1252 } // ~Inst_VOP3__V_CMPX_NLT_F16
1253
1254 // --- description from .arch file ---
1255 // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
1256 void
1257 Inst_VOP3__V_CMPX_NLT_F16::execute(GPUDynInstPtr gpuDynInst)
1258 {
1259 panicUnimplemented();
1260 } // execute
1261 // --- Inst_VOP3__V_CMPX_TRU_F16 class methods ---
1262
1263 Inst_VOP3__V_CMPX_TRU_F16::Inst_VOP3__V_CMPX_TRU_F16(
1264 InFmt_VOP3A *iFmt)
1265 : Inst_VOP3A(iFmt, "v_cmpx_tru_f16", true)
1266 {
1267 setFlag(ALU);
1268 setFlag(F16);
1269 setFlag(WritesEXEC);
1270 } // Inst_VOP3__V_CMPX_TRU_F16
1271
1272 Inst_VOP3__V_CMPX_TRU_F16::~Inst_VOP3__V_CMPX_TRU_F16()
1273 {
1274 } // ~Inst_VOP3__V_CMPX_TRU_F16
1275
1276 // --- description from .arch file ---
1277 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
1278 void
1279 Inst_VOP3__V_CMPX_TRU_F16::execute(GPUDynInstPtr gpuDynInst)
1280 {
1281 Wavefront *wf = gpuDynInst->wavefront();
1282 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1283
1284 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1285 if (wf->execMask(lane)) {
1286 sdst.setBit(lane, 1);
1287 }
1288 }
1289
1290 wf->execMask() = sdst.rawData();
1291 sdst.write();
1292 } // execute
1293 // --- Inst_VOP3__V_CMP_F_F32 class methods ---
1294
1295 Inst_VOP3__V_CMP_F_F32::Inst_VOP3__V_CMP_F_F32(InFmt_VOP3A *iFmt)
1296 : Inst_VOP3A(iFmt, "v_cmp_f_f32", true)
1297 {
1298 setFlag(ALU);
1299 setFlag(F32);
1300 } // Inst_VOP3__V_CMP_F_F32
1301
1302 Inst_VOP3__V_CMP_F_F32::~Inst_VOP3__V_CMP_F_F32()
1303 {
1304 } // ~Inst_VOP3__V_CMP_F_F32
1305
1306 // --- description from .arch file ---
1307 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
1308 void
1309 Inst_VOP3__V_CMP_F_F32::execute(GPUDynInstPtr gpuDynInst)
1310 {
1311 Wavefront *wf = gpuDynInst->wavefront();
1312 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1313
1314 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1315 if (wf->execMask(lane)) {
1316 sdst.setBit(lane, 0);
1317 }
1318 }
1319
1320 sdst.write();
1321 } // execute
1322 // --- Inst_VOP3__V_CMP_LT_F32 class methods ---
1323
1324 Inst_VOP3__V_CMP_LT_F32::Inst_VOP3__V_CMP_LT_F32(
1325 InFmt_VOP3A *iFmt)
1326 : Inst_VOP3A(iFmt, "v_cmp_lt_f32", true)
1327 {
1328 setFlag(ALU);
1329 setFlag(F32);
1330 } // Inst_VOP3__V_CMP_LT_F32
1331
1332 Inst_VOP3__V_CMP_LT_F32::~Inst_VOP3__V_CMP_LT_F32()
1333 {
1334 } // ~Inst_VOP3__V_CMP_LT_F32
1335
1336 // --- description from .arch file ---
1337 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
1338 void
1339 Inst_VOP3__V_CMP_LT_F32::execute(GPUDynInstPtr gpuDynInst)
1340 {
1341 Wavefront *wf = gpuDynInst->wavefront();
1342 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1343 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1344 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1345
1346 src0.readSrc();
1347 src1.readSrc();
1348
1349 if (instData.ABS & 0x1) {
1350 src0.absModifier();
1351 }
1352
1353 if (instData.ABS & 0x2) {
1354 src1.absModifier();
1355 }
1356
1357 if (extData.NEG & 0x1) {
1358 src0.negModifier();
1359 }
1360
1361 if (extData.NEG & 0x2) {
1362 src1.negModifier();
1363 }
1364
1368 assert(!(instData.ABS & 0x4));
1369 assert(!(extData.NEG & 0x4));
1370
1371 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1372 if (wf->execMask(lane)) {
1373 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
1374 }
1375 }
1376
1377 sdst.write();
1378 } // execute
1379 // --- Inst_VOP3__V_CMP_EQ_F32 class methods ---
1380
1381 Inst_VOP3__V_CMP_EQ_F32::Inst_VOP3__V_CMP_EQ_F32(
1382 InFmt_VOP3A *iFmt)
1383 : Inst_VOP3A(iFmt, "v_cmp_eq_f32", true)
1384 {
1385 setFlag(ALU);
1386 setFlag(F32);
1387 } // Inst_VOP3__V_CMP_EQ_F32
1388
1389 Inst_VOP3__V_CMP_EQ_F32::~Inst_VOP3__V_CMP_EQ_F32()
1390 {
1391 } // ~Inst_VOP3__V_CMP_EQ_F32
1392
1393 // --- description from .arch file ---
1394 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
1395 void
1396 Inst_VOP3__V_CMP_EQ_F32::execute(GPUDynInstPtr gpuDynInst)
1397 {
1398 Wavefront *wf = gpuDynInst->wavefront();
1399 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1400 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1401 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1402
1403 src0.readSrc();
1404 src1.readSrc();
1405
1406 if (instData.ABS & 0x1) {
1407 src0.absModifier();
1408 }
1409
1410 if (instData.ABS & 0x2) {
1411 src1.absModifier();
1412 }
1413
1414 if (extData.NEG & 0x1) {
1415 src0.negModifier();
1416 }
1417
1418 if (extData.NEG & 0x2) {
1419 src1.negModifier();
1420 }
1421
1425 assert(!(instData.ABS & 0x4));
1426 assert(!(extData.NEG & 0x4));
1427
1428 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1429 if (wf->execMask(lane)) {
1430 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
1431 }
1432 }
1433
1434 sdst.write();
1435 } // execute
1436 // --- Inst_VOP3__V_CMP_LE_F32 class methods ---
1437
1438 Inst_VOP3__V_CMP_LE_F32::Inst_VOP3__V_CMP_LE_F32(
1439 InFmt_VOP3A *iFmt)
1440 : Inst_VOP3A(iFmt, "v_cmp_le_f32", true)
1441 {
1442 setFlag(ALU);
1443 setFlag(F32);
1444 } // Inst_VOP3__V_CMP_LE_F32
1445
1446 Inst_VOP3__V_CMP_LE_F32::~Inst_VOP3__V_CMP_LE_F32()
1447 {
1448 } // ~Inst_VOP3__V_CMP_LE_F32
1449
1450 // --- description from .arch file ---
1451 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
1452 void
1453 Inst_VOP3__V_CMP_LE_F32::execute(GPUDynInstPtr gpuDynInst)
1454 {
1455 Wavefront *wf = gpuDynInst->wavefront();
1456 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1457 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1458 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1459
1460 src0.readSrc();
1461 src1.readSrc();
1462
1463 if (instData.ABS & 0x1) {
1464 src0.absModifier();
1465 }
1466
1467 if (instData.ABS & 0x2) {
1468 src1.absModifier();
1469 }
1470
1471 if (extData.NEG & 0x1) {
1472 src0.negModifier();
1473 }
1474
1475 if (extData.NEG & 0x2) {
1476 src1.negModifier();
1477 }
1478
1482 assert(!(instData.ABS & 0x4));
1483 assert(!(extData.NEG & 0x4));
1484
1485 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1486 if (wf->execMask(lane)) {
1487 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
1488 }
1489 }
1490
1491 sdst.write();
1492 } // execute
1493 // --- Inst_VOP3__V_CMP_GT_F32 class methods ---
1494
1495 Inst_VOP3__V_CMP_GT_F32::Inst_VOP3__V_CMP_GT_F32(
1496 InFmt_VOP3A *iFmt)
1497 : Inst_VOP3A(iFmt, "v_cmp_gt_f32", true)
1498 {
1499 setFlag(ALU);
1500 setFlag(F32);
1501 } // Inst_VOP3__V_CMP_GT_F32
1502
1503 Inst_VOP3__V_CMP_GT_F32::~Inst_VOP3__V_CMP_GT_F32()
1504 {
1505 } // ~Inst_VOP3__V_CMP_GT_F32
1506
1507 // --- description from .arch file ---
1508 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
1509 void
1510 Inst_VOP3__V_CMP_GT_F32::execute(GPUDynInstPtr gpuDynInst)
1511 {
1512 Wavefront *wf = gpuDynInst->wavefront();
1513 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1514 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1515 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1516
1517 src0.readSrc();
1518 src1.readSrc();
1519
1520 if (instData.ABS & 0x1) {
1521 src0.absModifier();
1522 }
1523
1524 if (instData.ABS & 0x2) {
1525 src1.absModifier();
1526 }
1527
1528 if (extData.NEG & 0x1) {
1529 src0.negModifier();
1530 }
1531
1532 if (extData.NEG & 0x2) {
1533 src1.negModifier();
1534 }
1535
1539 assert(!(instData.ABS & 0x4));
1540 assert(!(extData.NEG & 0x4));
1541
1542 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1543 if (wf->execMask(lane)) {
1544 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
1545 }
1546 }
1547
1548 sdst.write();
1549 } // execute
1550 // --- Inst_VOP3__V_CMP_LG_F32 class methods ---
1551
1552 Inst_VOP3__V_CMP_LG_F32::Inst_VOP3__V_CMP_LG_F32(
1553 InFmt_VOP3A *iFmt)
1554 : Inst_VOP3A(iFmt, "v_cmp_lg_f32", true)
1555 {
1556 setFlag(ALU);
1557 setFlag(F32);
1558 } // Inst_VOP3__V_CMP_LG_F32
1559
1560 Inst_VOP3__V_CMP_LG_F32::~Inst_VOP3__V_CMP_LG_F32()
1561 {
1562 } // ~Inst_VOP3__V_CMP_LG_F32
1563
1564 // --- description from .arch file ---
1565 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
1566 void
1567 Inst_VOP3__V_CMP_LG_F32::execute(GPUDynInstPtr gpuDynInst)
1568 {
1569 Wavefront *wf = gpuDynInst->wavefront();
1570 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1571 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1572 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1573
1574 src0.readSrc();
1575 src1.readSrc();
1576
1577 if (instData.ABS & 0x1) {
1578 src0.absModifier();
1579 }
1580
1581 if (instData.ABS & 0x2) {
1582 src1.absModifier();
1583 }
1584
1585 if (extData.NEG & 0x1) {
1586 src0.negModifier();
1587 }
1588
1589 if (extData.NEG & 0x2) {
1590 src1.negModifier();
1591 }
1592
1596 assert(!(instData.ABS & 0x4));
1597 assert(!(extData.NEG & 0x4));
1598
1599 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1600 if (wf->execMask(lane)) {
1601 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
1602 }
1603 }
1604
1605 sdst.write();
1606 } // execute
1607 // --- Inst_VOP3__V_CMP_GE_F32 class methods ---
1608
1609 Inst_VOP3__V_CMP_GE_F32::Inst_VOP3__V_CMP_GE_F32(
1610 InFmt_VOP3A *iFmt)
1611 : Inst_VOP3A(iFmt, "v_cmp_ge_f32", true)
1612 {
1613 setFlag(ALU);
1614 setFlag(F32);
1615 } // Inst_VOP3__V_CMP_GE_F32
1616
1617 Inst_VOP3__V_CMP_GE_F32::~Inst_VOP3__V_CMP_GE_F32()
1618 {
1619 } // ~Inst_VOP3__V_CMP_GE_F32
1620
1621 // --- description from .arch file ---
1622 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
1623 void
1624 Inst_VOP3__V_CMP_GE_F32::execute(GPUDynInstPtr gpuDynInst)
1625 {
1626 Wavefront *wf = gpuDynInst->wavefront();
1627 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1628 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1629 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1630
1631 src0.readSrc();
1632 src1.readSrc();
1633
1634 if (instData.ABS & 0x1) {
1635 src0.absModifier();
1636 }
1637
1638 if (instData.ABS & 0x2) {
1639 src1.absModifier();
1640 }
1641
1642 if (extData.NEG & 0x1) {
1643 src0.negModifier();
1644 }
1645
1646 if (extData.NEG & 0x2) {
1647 src1.negModifier();
1648 }
1649
1653 assert(!(instData.ABS & 0x4));
1654 assert(!(extData.NEG & 0x4));
1655
1656 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1657 if (wf->execMask(lane)) {
1658 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
1659 }
1660 }
1661
1662 sdst.write();
1663 } // execute
1664 // --- Inst_VOP3__V_CMP_O_F32 class methods ---
1665
1666 Inst_VOP3__V_CMP_O_F32::Inst_VOP3__V_CMP_O_F32(InFmt_VOP3A *iFmt)
1667 : Inst_VOP3A(iFmt, "v_cmp_o_f32", true)
1668 {
1669 setFlag(ALU);
1670 setFlag(F32);
1671 } // Inst_VOP3__V_CMP_O_F32
1672
1673 Inst_VOP3__V_CMP_O_F32::~Inst_VOP3__V_CMP_O_F32()
1674 {
1675 } // ~Inst_VOP3__V_CMP_O_F32
1676
1677 // --- description from .arch file ---
1678 // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
1679 void
1680 Inst_VOP3__V_CMP_O_F32::execute(GPUDynInstPtr gpuDynInst)
1681 {
1682 Wavefront *wf = gpuDynInst->wavefront();
1683 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1684 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1685 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1686
1687 src0.readSrc();
1688 src1.readSrc();
1689
1690 if (instData.ABS & 0x1) {
1691 src0.absModifier();
1692 }
1693
1694 if (instData.ABS & 0x2) {
1695 src1.absModifier();
1696 }
1697
1698 if (extData.NEG & 0x1) {
1699 src0.negModifier();
1700 }
1701
1702 if (extData.NEG & 0x2) {
1703 src1.negModifier();
1704 }
1705
1709 assert(!(instData.ABS & 0x4));
1710 assert(!(extData.NEG & 0x4));
1711
1712 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1713 if (wf->execMask(lane)) {
1714 sdst.setBit(lane, (!std::isnan(src0[lane])
1715 && !std::isnan(src1[lane])) ? 1 : 0);
1716 }
1717 }
1718
1719 sdst.write();
1720 } // execute
1721 // --- Inst_VOP3__V_CMP_U_F32 class methods ---
1722
1723 Inst_VOP3__V_CMP_U_F32::Inst_VOP3__V_CMP_U_F32(InFmt_VOP3A *iFmt)
1724 : Inst_VOP3A(iFmt, "v_cmp_u_f32", true)
1725 {
1726 setFlag(ALU);
1727 setFlag(F32);
1728 } // Inst_VOP3__V_CMP_U_F32
1729
1730 Inst_VOP3__V_CMP_U_F32::~Inst_VOP3__V_CMP_U_F32()
1731 {
1732 } // ~Inst_VOP3__V_CMP_U_F32
1733
1734 // --- description from .arch file ---
1735 // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
1736 void
1737 Inst_VOP3__V_CMP_U_F32::execute(GPUDynInstPtr gpuDynInst)
1738 {
1739 Wavefront *wf = gpuDynInst->wavefront();
1740 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1741 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1742 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1743
1744 src0.readSrc();
1745 src1.readSrc();
1746
1747 if (instData.ABS & 0x1) {
1748 src0.absModifier();
1749 }
1750
1751 if (instData.ABS & 0x2) {
1752 src1.absModifier();
1753 }
1754
1755 if (extData.NEG & 0x1) {
1756 src0.negModifier();
1757 }
1758
1759 if (extData.NEG & 0x2) {
1760 src1.negModifier();
1761 }
1762
1766 assert(!(instData.ABS & 0x4));
1767 assert(!(extData.NEG & 0x4));
1768
1769 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1770 if (wf->execMask(lane)) {
1771 sdst.setBit(lane, (std::isnan(src0[lane])
1772 || std::isnan(src1[lane])) ? 1 : 0);
1773 }
1774 }
1775
1776 sdst.write();
1777 } // execute
1778 // --- Inst_VOP3__V_CMP_NGE_F32 class methods ---
1779
1780 Inst_VOP3__V_CMP_NGE_F32::Inst_VOP3__V_CMP_NGE_F32(
1781 InFmt_VOP3A *iFmt)
1782 : Inst_VOP3A(iFmt, "v_cmp_nge_f32", true)
1783 {
1784 setFlag(ALU);
1785 setFlag(F32);
1786 } // Inst_VOP3__V_CMP_NGE_F32
1787
1788 Inst_VOP3__V_CMP_NGE_F32::~Inst_VOP3__V_CMP_NGE_F32()
1789 {
1790 } // ~Inst_VOP3__V_CMP_NGE_F32
1791
1792 // --- description from .arch file ---
1793 // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
1794 void
1795 Inst_VOP3__V_CMP_NGE_F32::execute(GPUDynInstPtr gpuDynInst)
1796 {
1797 Wavefront *wf = gpuDynInst->wavefront();
1798 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1799 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1800 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1801
1802 src0.readSrc();
1803 src1.readSrc();
1804
1805 if (instData.ABS & 0x1) {
1806 src0.absModifier();
1807 }
1808
1809 if (instData.ABS & 0x2) {
1810 src1.absModifier();
1811 }
1812
1813 if (extData.NEG & 0x1) {
1814 src0.negModifier();
1815 }
1816
1817 if (extData.NEG & 0x2) {
1818 src1.negModifier();
1819 }
1820
1824 assert(!(instData.ABS & 0x4));
1825 assert(!(extData.NEG & 0x4));
1826
1827 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1828 if (wf->execMask(lane)) {
1829 sdst.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
1830 }
1831 }
1832
1833 sdst.write();
1834 } // execute
1835 // --- Inst_VOP3__V_CMP_NLG_F32 class methods ---
1836
1837 Inst_VOP3__V_CMP_NLG_F32::Inst_VOP3__V_CMP_NLG_F32(
1838 InFmt_VOP3A *iFmt)
1839 : Inst_VOP3A(iFmt, "v_cmp_nlg_f32", true)
1840 {
1841 setFlag(ALU);
1842 setFlag(F32);
1843 } // Inst_VOP3__V_CMP_NLG_F32
1844
1845 Inst_VOP3__V_CMP_NLG_F32::~Inst_VOP3__V_CMP_NLG_F32()
1846 {
1847 } // ~Inst_VOP3__V_CMP_NLG_F32
1848
1849 // --- description from .arch file ---
1850 // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
1851 void
1852 Inst_VOP3__V_CMP_NLG_F32::execute(GPUDynInstPtr gpuDynInst)
1853 {
1854 Wavefront *wf = gpuDynInst->wavefront();
1855 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1856 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1857 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1858
1859 src0.readSrc();
1860 src1.readSrc();
1861
1862 if (instData.ABS & 0x1) {
1863 src0.absModifier();
1864 }
1865
1866 if (instData.ABS & 0x2) {
1867 src1.absModifier();
1868 }
1869
1870 if (extData.NEG & 0x1) {
1871 src0.negModifier();
1872 }
1873
1874 if (extData.NEG & 0x2) {
1875 src1.negModifier();
1876 }
1877
1881 assert(!(instData.ABS & 0x4));
1882 assert(!(extData.NEG & 0x4));
1883
1884 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1885 if (wf->execMask(lane)) {
1886 sdst.setBit(lane, !(src0[lane] < src1[lane]
1887 || src0[lane] > src1[lane]) ? 1 : 0);
1888 }
1889 }
1890
1891 sdst.write();
1892 } // execute
1893 // --- Inst_VOP3__V_CMP_NGT_F32 class methods ---
1894
1895 Inst_VOP3__V_CMP_NGT_F32::Inst_VOP3__V_CMP_NGT_F32(
1896 InFmt_VOP3A *iFmt)
1897 : Inst_VOP3A(iFmt, "v_cmp_ngt_f32", true)
1898 {
1899 setFlag(ALU);
1900 setFlag(F32);
1901 } // Inst_VOP3__V_CMP_NGT_F32
1902
1903 Inst_VOP3__V_CMP_NGT_F32::~Inst_VOP3__V_CMP_NGT_F32()
1904 {
1905 } // ~Inst_VOP3__V_CMP_NGT_F32
1906
1907 // --- description from .arch file ---
1908 // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
1909 void
1910 Inst_VOP3__V_CMP_NGT_F32::execute(GPUDynInstPtr gpuDynInst)
1911 {
1912 Wavefront *wf = gpuDynInst->wavefront();
1913 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1914 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1915 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1916
1917 src0.readSrc();
1918 src1.readSrc();
1919
1920 if (instData.ABS & 0x1) {
1921 src0.absModifier();
1922 }
1923
1924 if (instData.ABS & 0x2) {
1925 src1.absModifier();
1926 }
1927
1928 if (extData.NEG & 0x1) {
1929 src0.negModifier();
1930 }
1931
1932 if (extData.NEG & 0x2) {
1933 src1.negModifier();
1934 }
1935
1939 assert(!(instData.ABS & 0x4));
1940 assert(!(extData.NEG & 0x4));
1941
1942 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
1943 if (wf->execMask(lane)) {
1944 sdst.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
1945 }
1946 }
1947
1948 sdst.write();
1949 } // execute
1950 // --- Inst_VOP3__V_CMP_NLE_F32 class methods ---
1951
1952 Inst_VOP3__V_CMP_NLE_F32::Inst_VOP3__V_CMP_NLE_F32(
1953 InFmt_VOP3A *iFmt)
1954 : Inst_VOP3A(iFmt, "v_cmp_nle_f32", true)
1955 {
1956 setFlag(ALU);
1957 setFlag(F32);
1958 } // Inst_VOP3__V_CMP_NLE_F32
1959
1960 Inst_VOP3__V_CMP_NLE_F32::~Inst_VOP3__V_CMP_NLE_F32()
1961 {
1962 } // ~Inst_VOP3__V_CMP_NLE_F32
1963
1964 // --- description from .arch file ---
1965 // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
1966 void
1967 Inst_VOP3__V_CMP_NLE_F32::execute(GPUDynInstPtr gpuDynInst)
1968 {
1969 Wavefront *wf = gpuDynInst->wavefront();
1970 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
1971 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
1972 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
1973
1974 src0.readSrc();
1975 src1.readSrc();
1976
1977 if (instData.ABS & 0x1) {
1978 src0.absModifier();
1979 }
1980
1981 if (instData.ABS & 0x2) {
1982 src1.absModifier();
1983 }
1984
1985 if (extData.NEG & 0x1) {
1986 src0.negModifier();
1987 }
1988
1989 if (extData.NEG & 0x2) {
1990 src1.negModifier();
1991 }
1992
1996 assert(!(instData.ABS & 0x4));
1997 assert(!(extData.NEG & 0x4));
1998
1999 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2000 if (wf->execMask(lane)) {
2001 sdst.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
2002 }
2003 }
2004
2005 sdst.write();
2006 } // execute
2007 // --- Inst_VOP3__V_CMP_NEQ_F32 class methods ---
2008
2009 Inst_VOP3__V_CMP_NEQ_F32::Inst_VOP3__V_CMP_NEQ_F32(
2010 InFmt_VOP3A *iFmt)
2011 : Inst_VOP3A(iFmt, "v_cmp_neq_f32", true)
2012 {
2013 setFlag(ALU);
2014 setFlag(F32);
2015 } // Inst_VOP3__V_CMP_NEQ_F32
2016
2017 Inst_VOP3__V_CMP_NEQ_F32::~Inst_VOP3__V_CMP_NEQ_F32()
2018 {
2019 } // ~Inst_VOP3__V_CMP_NEQ_F32
2020
2021 // --- description from .arch file ---
2022 // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
2023 void
2024 Inst_VOP3__V_CMP_NEQ_F32::execute(GPUDynInstPtr gpuDynInst)
2025 {
2026 Wavefront *wf = gpuDynInst->wavefront();
2027 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2028 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2029 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2030
2031 src0.readSrc();
2032 src1.readSrc();
2033
2034 if (instData.ABS & 0x1) {
2035 src0.absModifier();
2036 }
2037
2038 if (instData.ABS & 0x2) {
2039 src1.absModifier();
2040 }
2041
2042 if (extData.NEG & 0x1) {
2043 src0.negModifier();
2044 }
2045
2046 if (extData.NEG & 0x2) {
2047 src1.negModifier();
2048 }
2049
2053 assert(!(instData.ABS & 0x4));
2054 assert(!(extData.NEG & 0x4));
2055
2056 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2057 if (wf->execMask(lane)) {
2058 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
2059 }
2060 }
2061
2062 sdst.write();
2063 } // execute
2064 // --- Inst_VOP3__V_CMP_NLT_F32 class methods ---
2065
2066 Inst_VOP3__V_CMP_NLT_F32::Inst_VOP3__V_CMP_NLT_F32(
2067 InFmt_VOP3A *iFmt)
2068 : Inst_VOP3A(iFmt, "v_cmp_nlt_f32", true)
2069 {
2070 setFlag(ALU);
2071 setFlag(F32);
2072 } // Inst_VOP3__V_CMP_NLT_F32
2073
2074 Inst_VOP3__V_CMP_NLT_F32::~Inst_VOP3__V_CMP_NLT_F32()
2075 {
2076 } // ~Inst_VOP3__V_CMP_NLT_F32
2077
2078 // --- description from .arch file ---
2079 // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
2080 void
2081 Inst_VOP3__V_CMP_NLT_F32::execute(GPUDynInstPtr gpuDynInst)
2082 {
2083 Wavefront *wf = gpuDynInst->wavefront();
2084 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2085 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2086 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2087
2088 src0.readSrc();
2089 src1.readSrc();
2090
2091 if (instData.ABS & 0x1) {
2092 src0.absModifier();
2093 }
2094
2095 if (instData.ABS & 0x2) {
2096 src1.absModifier();
2097 }
2098
2099 if (extData.NEG & 0x1) {
2100 src0.negModifier();
2101 }
2102
2103 if (extData.NEG & 0x2) {
2104 src1.negModifier();
2105 }
2106
2110 assert(!(instData.ABS & 0x4));
2111 assert(!(extData.NEG & 0x4));
2112
2113 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2114 if (wf->execMask(lane)) {
2115 sdst.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
2116 }
2117 }
2118
2119 sdst.write();
2120 } // execute
2121 // --- Inst_VOP3__V_CMP_TRU_F32 class methods ---
2122
2123 Inst_VOP3__V_CMP_TRU_F32::Inst_VOP3__V_CMP_TRU_F32(
2124 InFmt_VOP3A *iFmt)
2125 : Inst_VOP3A(iFmt, "v_cmp_tru_f32", true)
2126 {
2127 setFlag(ALU);
2128 setFlag(F32);
2129 } // Inst_VOP3__V_CMP_TRU_F32
2130
2131 Inst_VOP3__V_CMP_TRU_F32::~Inst_VOP3__V_CMP_TRU_F32()
2132 {
2133 } // ~Inst_VOP3__V_CMP_TRU_F32
2134
2135 // --- description from .arch file ---
2136 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
2137 void
2138 Inst_VOP3__V_CMP_TRU_F32::execute(GPUDynInstPtr gpuDynInst)
2139 {
2140 Wavefront *wf = gpuDynInst->wavefront();
2141 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2142
2143 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2144 if (wf->execMask(lane)) {
2145 sdst.setBit(lane, 1);
2146 }
2147 }
2148
2149 sdst.write();
2150 } // execute
2151 // --- Inst_VOP3__V_CMPX_F_F32 class methods ---
2152
2153 Inst_VOP3__V_CMPX_F_F32::Inst_VOP3__V_CMPX_F_F32(
2154 InFmt_VOP3A *iFmt)
2155 : Inst_VOP3A(iFmt, "v_cmpx_f_f32", true)
2156 {
2157 setFlag(ALU);
2158 setFlag(F32);
2159 setFlag(WritesEXEC);
2160 } // Inst_VOP3__V_CMPX_F_F32
2161
2162 Inst_VOP3__V_CMPX_F_F32::~Inst_VOP3__V_CMPX_F_F32()
2163 {
2164 } // ~Inst_VOP3__V_CMPX_F_F32
2165
2166 // --- description from .arch file ---
2167 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
2168 void
2169 Inst_VOP3__V_CMPX_F_F32::execute(GPUDynInstPtr gpuDynInst)
2170 {
2171 Wavefront *wf = gpuDynInst->wavefront();
2172 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2173
2174 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2175 if (wf->execMask(lane)) {
2176 sdst.setBit(lane, 0);
2177 }
2178 }
2179
2180 wf->execMask() = sdst.rawData();
2181 sdst.write();
2182 } // execute
2183 // --- Inst_VOP3__V_CMPX_LT_F32 class methods ---
2184
2185 Inst_VOP3__V_CMPX_LT_F32::Inst_VOP3__V_CMPX_LT_F32(
2186 InFmt_VOP3A *iFmt)
2187 : Inst_VOP3A(iFmt, "v_cmpx_lt_f32", true)
2188 {
2189 setFlag(ALU);
2190 setFlag(F32);
2191 setFlag(WritesEXEC);
2192 } // Inst_VOP3__V_CMPX_LT_F32
2193
2194 Inst_VOP3__V_CMPX_LT_F32::~Inst_VOP3__V_CMPX_LT_F32()
2195 {
2196 } // ~Inst_VOP3__V_CMPX_LT_F32
2197
2198 // --- description from .arch file ---
2199 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
2200 void
2201 Inst_VOP3__V_CMPX_LT_F32::execute(GPUDynInstPtr gpuDynInst)
2202 {
2203 Wavefront *wf = gpuDynInst->wavefront();
2204 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2205 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2206 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2207
2208 src0.readSrc();
2209 src1.readSrc();
2210
2211 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2212 if (wf->execMask(lane)) {
2213 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
2214 }
2215 }
2216
2217 wf->execMask() = sdst.rawData();
2218 sdst.write();
2219 } // execute
2220 // --- Inst_VOP3__V_CMPX_EQ_F32 class methods ---
2221
2222 Inst_VOP3__V_CMPX_EQ_F32::Inst_VOP3__V_CMPX_EQ_F32(
2223 InFmt_VOP3A *iFmt)
2224 : Inst_VOP3A(iFmt, "v_cmpx_eq_f32", true)
2225 {
2226 setFlag(ALU);
2227 setFlag(F32);
2228 setFlag(WritesEXEC);
2229 } // Inst_VOP3__V_CMPX_EQ_F32
2230
2231 Inst_VOP3__V_CMPX_EQ_F32::~Inst_VOP3__V_CMPX_EQ_F32()
2232 {
2233 } // ~Inst_VOP3__V_CMPX_EQ_F32
2234
2235 // --- description from .arch file ---
2236 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
2237 void
2238 Inst_VOP3__V_CMPX_EQ_F32::execute(GPUDynInstPtr gpuDynInst)
2239 {
2240 Wavefront *wf = gpuDynInst->wavefront();
2241 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2242 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2243 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2244
2245 src0.readSrc();
2246 src1.readSrc();
2247
2248 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2249 if (wf->execMask(lane)) {
2250 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
2251 }
2252 }
2253
2254 wf->execMask() = sdst.rawData();
2255 sdst.write();
2256 } // execute
2257 // --- Inst_VOP3__V_CMPX_LE_F32 class methods ---
2258
2259 Inst_VOP3__V_CMPX_LE_F32::Inst_VOP3__V_CMPX_LE_F32(
2260 InFmt_VOP3A *iFmt)
2261 : Inst_VOP3A(iFmt, "v_cmpx_le_f32", true)
2262 {
2263 setFlag(ALU);
2264 setFlag(F32);
2265 setFlag(WritesEXEC);
2266 } // Inst_VOP3__V_CMPX_LE_F32
2267
2268 Inst_VOP3__V_CMPX_LE_F32::~Inst_VOP3__V_CMPX_LE_F32()
2269 {
2270 } // ~Inst_VOP3__V_CMPX_LE_F32
2271
2272 // --- description from .arch file ---
2273 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
2274 void
2275 Inst_VOP3__V_CMPX_LE_F32::execute(GPUDynInstPtr gpuDynInst)
2276 {
2277 Wavefront *wf = gpuDynInst->wavefront();
2278 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2279 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2280 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2281
2282 src0.readSrc();
2283 src1.readSrc();
2284
2285 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2286 if (wf->execMask(lane)) {
2287 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
2288 }
2289 }
2290
2291 wf->execMask() = sdst.rawData();
2292 sdst.write();
2293 } // execute
2294 // --- Inst_VOP3__V_CMPX_GT_F32 class methods ---
2295
2296 Inst_VOP3__V_CMPX_GT_F32::Inst_VOP3__V_CMPX_GT_F32(
2297 InFmt_VOP3A *iFmt)
2298 : Inst_VOP3A(iFmt, "v_cmpx_gt_f32", true)
2299 {
2300 setFlag(ALU);
2301 setFlag(F32);
2302 setFlag(WritesEXEC);
2303 } // Inst_VOP3__V_CMPX_GT_F32
2304
2305 Inst_VOP3__V_CMPX_GT_F32::~Inst_VOP3__V_CMPX_GT_F32()
2306 {
2307 } // ~Inst_VOP3__V_CMPX_GT_F32
2308
2309 // --- description from .arch file ---
2310 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
2311 void
2312 Inst_VOP3__V_CMPX_GT_F32::execute(GPUDynInstPtr gpuDynInst)
2313 {
2314 Wavefront *wf = gpuDynInst->wavefront();
2315 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2316 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2317 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2318
2319 src0.readSrc();
2320 src1.readSrc();
2321
2322 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2323 if (wf->execMask(lane)) {
2324 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
2325 }
2326 }
2327
2328 wf->execMask() = sdst.rawData();
2329 sdst.write();
2330 } // execute
2331 // --- Inst_VOP3__V_CMPX_LG_F32 class methods ---
2332
2333 Inst_VOP3__V_CMPX_LG_F32::Inst_VOP3__V_CMPX_LG_F32(
2334 InFmt_VOP3A *iFmt)
2335 : Inst_VOP3A(iFmt, "v_cmpx_lg_f32", true)
2336 {
2337 setFlag(ALU);
2338 setFlag(F32);
2339 setFlag(WritesEXEC);
2340 } // Inst_VOP3__V_CMPX_LG_F32
2341
2342 Inst_VOP3__V_CMPX_LG_F32::~Inst_VOP3__V_CMPX_LG_F32()
2343 {
2344 } // ~Inst_VOP3__V_CMPX_LG_F32
2345
2346 // --- description from .arch file ---
2347 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
2348 void
2349 Inst_VOP3__V_CMPX_LG_F32::execute(GPUDynInstPtr gpuDynInst)
2350 {
2351 Wavefront *wf = gpuDynInst->wavefront();
2352 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2353 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2354 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2355
2356 src0.readSrc();
2357 src1.readSrc();
2358
2359 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2360 if (wf->execMask(lane)) {
2361 sdst.setBit(lane, (src0[lane] < src1[lane]
2362 || src0[lane] > src1[lane]) ? 1 : 0);
2363 }
2364 }
2365
2366 wf->execMask() = sdst.rawData();
2367 sdst.write();
2368 } // execute
2369 // --- Inst_VOP3__V_CMPX_GE_F32 class methods ---
2370
2371 Inst_VOP3__V_CMPX_GE_F32::Inst_VOP3__V_CMPX_GE_F32(
2372 InFmt_VOP3A *iFmt)
2373 : Inst_VOP3A(iFmt, "v_cmpx_ge_f32", true)
2374 {
2375 setFlag(ALU);
2376 setFlag(F32);
2377 setFlag(WritesEXEC);
2378 } // Inst_VOP3__V_CMPX_GE_F32
2379
2380 Inst_VOP3__V_CMPX_GE_F32::~Inst_VOP3__V_CMPX_GE_F32()
2381 {
2382 } // ~Inst_VOP3__V_CMPX_GE_F32
2383
2384 // --- description from .arch file ---
2385 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
2386 void
2387 Inst_VOP3__V_CMPX_GE_F32::execute(GPUDynInstPtr gpuDynInst)
2388 {
2389 Wavefront *wf = gpuDynInst->wavefront();
2390 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2391 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2392 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2393
2394 src0.readSrc();
2395 src1.readSrc();
2396
2397 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2398 if (wf->execMask(lane)) {
2399 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
2400 }
2401 }
2402
2403 wf->execMask() = sdst.rawData();
2404 sdst.write();
2405 } // execute
2406 // --- Inst_VOP3__V_CMPX_O_F32 class methods ---
2407
2408 Inst_VOP3__V_CMPX_O_F32::Inst_VOP3__V_CMPX_O_F32(
2409 InFmt_VOP3A *iFmt)
2410 : Inst_VOP3A(iFmt, "v_cmpx_o_f32", true)
2411 {
2412 setFlag(ALU);
2413 setFlag(F32);
2414 setFlag(WritesEXEC);
2415 } // Inst_VOP3__V_CMPX_O_F32
2416
2417 Inst_VOP3__V_CMPX_O_F32::~Inst_VOP3__V_CMPX_O_F32()
2418 {
2419 } // ~Inst_VOP3__V_CMPX_O_F32
2420
2421 // --- description from .arch file ---
2422 // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
2423 // encoding.
2424 void
2425 Inst_VOP3__V_CMPX_O_F32::execute(GPUDynInstPtr gpuDynInst)
2426 {
2427 Wavefront *wf = gpuDynInst->wavefront();
2428 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2429 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2430 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2431
2432 src0.readSrc();
2433 src1.readSrc();
2434
2435 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2436 if (wf->execMask(lane)) {
2437 sdst.setBit(lane, (!std::isnan(src0[lane])
2438 && !std::isnan(src1[lane])) ? 1 : 0);
2439 }
2440 }
2441
2442 wf->execMask() = sdst.rawData();
2443 sdst.write();
2444 } // execute
2445 // --- Inst_VOP3__V_CMPX_U_F32 class methods ---
2446
2447 Inst_VOP3__V_CMPX_U_F32::Inst_VOP3__V_CMPX_U_F32(
2448 InFmt_VOP3A *iFmt)
2449 : Inst_VOP3A(iFmt, "v_cmpx_u_f32", true)
2450 {
2451 setFlag(ALU);
2452 setFlag(F32);
2453 setFlag(WritesEXEC);
2454 } // Inst_VOP3__V_CMPX_U_F32
2455
2456 Inst_VOP3__V_CMPX_U_F32::~Inst_VOP3__V_CMPX_U_F32()
2457 {
2458 } // ~Inst_VOP3__V_CMPX_U_F32
2459
2460 // --- description from .arch file ---
2461 // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
2462 // encoding.
2463 void
2464 Inst_VOP3__V_CMPX_U_F32::execute(GPUDynInstPtr gpuDynInst)
2465 {
2466 Wavefront *wf = gpuDynInst->wavefront();
2467 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2468 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2469 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2470
2471 src0.readSrc();
2472 src1.readSrc();
2473
2474 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2475 if (wf->execMask(lane)) {
2476 sdst.setBit(lane, (std::isnan(src0[lane])
2477 || std::isnan(src1[lane])) ? 1 : 0);
2478 }
2479 }
2480
2481 wf->execMask() = sdst.rawData();
2482 sdst.write();
2483 } // execute
2484 // --- Inst_VOP3__V_CMPX_NGE_F32 class methods ---
2485
2486 Inst_VOP3__V_CMPX_NGE_F32::Inst_VOP3__V_CMPX_NGE_F32(
2487 InFmt_VOP3A *iFmt)
2488 : Inst_VOP3A(iFmt, "v_cmpx_nge_f32", true)
2489 {
2490 setFlag(ALU);
2491 setFlag(F32);
2492 setFlag(WritesEXEC);
2493 } // Inst_VOP3__V_CMPX_NGE_F32
2494
2495 Inst_VOP3__V_CMPX_NGE_F32::~Inst_VOP3__V_CMPX_NGE_F32()
2496 {
2497 } // ~Inst_VOP3__V_CMPX_NGE_F32
2498
2499 // --- description from .arch file ---
2500 // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
2501 void
2502 Inst_VOP3__V_CMPX_NGE_F32::execute(GPUDynInstPtr gpuDynInst)
2503 {
2504 Wavefront *wf = gpuDynInst->wavefront();
2505 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2506 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2507 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2508
2509 src0.readSrc();
2510 src1.readSrc();
2511
2512 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2513 if (wf->execMask(lane)) {
2514 sdst.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
2515 }
2516 }
2517
2518 wf->execMask() = sdst.rawData();
2519 sdst.write();
2520 } // execute
2521 // --- Inst_VOP3__V_CMPX_NLG_F32 class methods ---
2522
2523 Inst_VOP3__V_CMPX_NLG_F32::Inst_VOP3__V_CMPX_NLG_F32(
2524 InFmt_VOP3A *iFmt)
2525 : Inst_VOP3A(iFmt, "v_cmpx_nlg_f32", true)
2526 {
2527 setFlag(ALU);
2528 setFlag(F32);
2529 setFlag(WritesEXEC);
2530 } // Inst_VOP3__V_CMPX_NLG_F32
2531
2532 Inst_VOP3__V_CMPX_NLG_F32::~Inst_VOP3__V_CMPX_NLG_F32()
2533 {
2534 } // ~Inst_VOP3__V_CMPX_NLG_F32
2535
2536 // --- description from .arch file ---
2537 // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
2538 void
2539 Inst_VOP3__V_CMPX_NLG_F32::execute(GPUDynInstPtr gpuDynInst)
2540 {
2541 Wavefront *wf = gpuDynInst->wavefront();
2542 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2543 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2544 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2545
2546 src0.readSrc();
2547 src1.readSrc();
2548
2549 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2550 if (wf->execMask(lane)) {
2551 sdst.setBit(lane, !(src0[lane] < src1[lane]
2552 || src0[lane] > src1[lane]) ? 1 : 0);
2553 }
2554 }
2555
2556 wf->execMask() = sdst.rawData();
2557 sdst.write();
2558 } // execute
2559 // --- Inst_VOP3__V_CMPX_NGT_F32 class methods ---
2560
2561 Inst_VOP3__V_CMPX_NGT_F32::Inst_VOP3__V_CMPX_NGT_F32(
2562 InFmt_VOP3A *iFmt)
2563 : Inst_VOP3A(iFmt, "v_cmpx_ngt_f32", true)
2564 {
2565 setFlag(ALU);
2566 setFlag(F32);
2567 setFlag(WritesEXEC);
2568 } // Inst_VOP3__V_CMPX_NGT_F32
2569
2570 Inst_VOP3__V_CMPX_NGT_F32::~Inst_VOP3__V_CMPX_NGT_F32()
2571 {
2572 } // ~Inst_VOP3__V_CMPX_NGT_F32
2573
2574 // --- description from .arch file ---
2575 // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
2576 void
2577 Inst_VOP3__V_CMPX_NGT_F32::execute(GPUDynInstPtr gpuDynInst)
2578 {
2579 Wavefront *wf = gpuDynInst->wavefront();
2580 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2581 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2582 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2583
2584 src0.readSrc();
2585 src1.readSrc();
2586
2587 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2588 if (wf->execMask(lane)) {
2589 sdst.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
2590 }
2591 }
2592
2593 wf->execMask() = sdst.rawData();
2594 sdst.write();
2595 } // execute
2596 // --- Inst_VOP3__V_CMPX_NLE_F32 class methods ---
2597
2598 Inst_VOP3__V_CMPX_NLE_F32::Inst_VOP3__V_CMPX_NLE_F32(
2599 InFmt_VOP3A *iFmt)
2600 : Inst_VOP3A(iFmt, "v_cmpx_nle_f32", true)
2601 {
2602 setFlag(ALU);
2603 setFlag(F32);
2604 setFlag(WritesEXEC);
2605 } // Inst_VOP3__V_CMPX_NLE_F32
2606
2607 Inst_VOP3__V_CMPX_NLE_F32::~Inst_VOP3__V_CMPX_NLE_F32()
2608 {
2609 } // ~Inst_VOP3__V_CMPX_NLE_F32
2610
2611 // --- description from .arch file ---
2612 // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
2613 void
2614 Inst_VOP3__V_CMPX_NLE_F32::execute(GPUDynInstPtr gpuDynInst)
2615 {
2616 Wavefront *wf = gpuDynInst->wavefront();
2617 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2618 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2619 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2620
2621 src0.readSrc();
2622 src1.readSrc();
2623
2624 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2625 if (wf->execMask(lane)) {
2626 sdst.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
2627 }
2628 }
2629
2630 wf->execMask() = sdst.rawData();
2631 sdst.write();
2632 } // execute
2633 // --- Inst_VOP3__V_CMPX_NEQ_F32 class methods ---
2634
2635 Inst_VOP3__V_CMPX_NEQ_F32::Inst_VOP3__V_CMPX_NEQ_F32(
2636 InFmt_VOP3A *iFmt)
2637 : Inst_VOP3A(iFmt, "v_cmpx_neq_f32", true)
2638 {
2639 setFlag(ALU);
2640 setFlag(F32);
2641 setFlag(WritesEXEC);
2642 } // Inst_VOP3__V_CMPX_NEQ_F32
2643
2644 Inst_VOP3__V_CMPX_NEQ_F32::~Inst_VOP3__V_CMPX_NEQ_F32()
2645 {
2646 } // ~Inst_VOP3__V_CMPX_NEQ_F32
2647
2648 // --- description from .arch file ---
2649 // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
2650 void
2651 Inst_VOP3__V_CMPX_NEQ_F32::execute(GPUDynInstPtr gpuDynInst)
2652 {
2653 Wavefront *wf = gpuDynInst->wavefront();
2654 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2655 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2656 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2657
2658 src0.readSrc();
2659 src1.readSrc();
2660
2661 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2662 if (wf->execMask(lane)) {
2663 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
2664 }
2665 }
2666
2667 wf->execMask() = sdst.rawData();
2668 sdst.write();
2669 } // execute
2670 // --- Inst_VOP3__V_CMPX_NLT_F32 class methods ---
2671
2672 Inst_VOP3__V_CMPX_NLT_F32::Inst_VOP3__V_CMPX_NLT_F32(
2673 InFmt_VOP3A *iFmt)
2674 : Inst_VOP3A(iFmt, "v_cmpx_nlt_f32", true)
2675 {
2676 setFlag(ALU);
2677 setFlag(F32);
2678 setFlag(WritesEXEC);
2679 } // Inst_VOP3__V_CMPX_NLT_F32
2680
2681 Inst_VOP3__V_CMPX_NLT_F32::~Inst_VOP3__V_CMPX_NLT_F32()
2682 {
2683 } // ~Inst_VOP3__V_CMPX_NLT_F32
2684
2685 // --- description from .arch file ---
2686 // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
2687 void
2688 Inst_VOP3__V_CMPX_NLT_F32::execute(GPUDynInstPtr gpuDynInst)
2689 {
2690 Wavefront *wf = gpuDynInst->wavefront();
2691 ConstVecOperandF32 src0(gpuDynInst, extData.SRC0);
2692 ConstVecOperandF32 src1(gpuDynInst, extData.SRC1);
2693 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2694
2695 src0.readSrc();
2696 src1.readSrc();
2697
2698 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2699 if (wf->execMask(lane)) {
2700 sdst.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
2701 }
2702 }
2703
2704 wf->execMask() = sdst.rawData();
2705 sdst.write();
2706 } // execute
2707 // --- Inst_VOP3__V_CMPX_TRU_F32 class methods ---
2708
2709 Inst_VOP3__V_CMPX_TRU_F32::Inst_VOP3__V_CMPX_TRU_F32(
2710 InFmt_VOP3A *iFmt)
2711 : Inst_VOP3A(iFmt, "v_cmpx_tru_f32", true)
2712 {
2713 setFlag(ALU);
2714 setFlag(F32);
2715 setFlag(WritesEXEC);
2716 } // Inst_VOP3__V_CMPX_TRU_F32
2717
2718 Inst_VOP3__V_CMPX_TRU_F32::~Inst_VOP3__V_CMPX_TRU_F32()
2719 {
2720 } // ~Inst_VOP3__V_CMPX_TRU_F32
2721
2722 // --- description from .arch file ---
2723 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
2724 void
2725 Inst_VOP3__V_CMPX_TRU_F32::execute(GPUDynInstPtr gpuDynInst)
2726 {
2727 Wavefront *wf = gpuDynInst->wavefront();
2728 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2729
2730 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2731 if (wf->execMask(lane)) {
2732 sdst.setBit(lane, 1);
2733 }
2734 }
2735
2736 wf->execMask() = sdst.rawData();
2737 sdst.write();
2738 } // execute
2739 // --- Inst_VOP3__V_CMP_F_F64 class methods ---
2740
2741 Inst_VOP3__V_CMP_F_F64::Inst_VOP3__V_CMP_F_F64(InFmt_VOP3A *iFmt)
2742 : Inst_VOP3A(iFmt, "v_cmp_f_f64", true)
2743 {
2744 setFlag(ALU);
2745 setFlag(F64);
2746 } // Inst_VOP3__V_CMP_F_F64
2747
2748 Inst_VOP3__V_CMP_F_F64::~Inst_VOP3__V_CMP_F_F64()
2749 {
2750 } // ~Inst_VOP3__V_CMP_F_F64
2751
2752 // --- description from .arch file ---
2753 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
2754 void
2755 Inst_VOP3__V_CMP_F_F64::execute(GPUDynInstPtr gpuDynInst)
2756 {
2757 Wavefront *wf = gpuDynInst->wavefront();
2758 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2759
2760 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2761 if (wf->execMask(lane)) {
2762 sdst.setBit(lane, 0);
2763 }
2764 }
2765
2766 sdst.write();
2767 } // execute
2768 // --- Inst_VOP3__V_CMP_LT_F64 class methods ---
2769
2770 Inst_VOP3__V_CMP_LT_F64::Inst_VOP3__V_CMP_LT_F64(
2771 InFmt_VOP3A *iFmt)
2772 : Inst_VOP3A(iFmt, "v_cmp_lt_f64", true)
2773 {
2774 setFlag(ALU);
2775 setFlag(F64);
2776 } // Inst_VOP3__V_CMP_LT_F64
2777
2778 Inst_VOP3__V_CMP_LT_F64::~Inst_VOP3__V_CMP_LT_F64()
2779 {
2780 } // ~Inst_VOP3__V_CMP_LT_F64
2781
2782 // --- description from .arch file ---
2783 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
2784 void
2785 Inst_VOP3__V_CMP_LT_F64::execute(GPUDynInstPtr gpuDynInst)
2786 {
2787 Wavefront *wf = gpuDynInst->wavefront();
2788 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
2789 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
2790 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2791
2792 src0.readSrc();
2793 src1.readSrc();
2794
2795 if (instData.ABS & 0x1) {
2796 src0.absModifier();
2797 }
2798
2799 if (instData.ABS & 0x2) {
2800 src1.absModifier();
2801 }
2802
2803 if (extData.NEG & 0x1) {
2804 src0.negModifier();
2805 }
2806
2807 if (extData.NEG & 0x2) {
2808 src1.negModifier();
2809 }
2810
2814 assert(!(instData.ABS & 0x4));
2815 assert(!(extData.NEG & 0x4));
2816
2817 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2818 if (wf->execMask(lane)) {
2819 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
2820 }
2821 }
2822
2823 sdst.write();
2824 } // execute
2825 // --- Inst_VOP3__V_CMP_EQ_F64 class methods ---
2826
2827 Inst_VOP3__V_CMP_EQ_F64::Inst_VOP3__V_CMP_EQ_F64(
2828 InFmt_VOP3A *iFmt)
2829 : Inst_VOP3A(iFmt, "v_cmp_eq_f64", true)
2830 {
2831 setFlag(ALU);
2832 setFlag(F64);
2833 } // Inst_VOP3__V_CMP_EQ_F64
2834
2835 Inst_VOP3__V_CMP_EQ_F64::~Inst_VOP3__V_CMP_EQ_F64()
2836 {
2837 } // ~Inst_VOP3__V_CMP_EQ_F64
2838
2839 // --- description from .arch file ---
2840 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
2841 void
2842 Inst_VOP3__V_CMP_EQ_F64::execute(GPUDynInstPtr gpuDynInst)
2843 {
2844 Wavefront *wf = gpuDynInst->wavefront();
2845 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
2846 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
2847 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2848
2849 src0.readSrc();
2850 src1.readSrc();
2851
2852 if (instData.ABS & 0x1) {
2853 src0.absModifier();
2854 }
2855
2856 if (instData.ABS & 0x2) {
2857 src1.absModifier();
2858 }
2859
2860 if (extData.NEG & 0x1) {
2861 src0.negModifier();
2862 }
2863
2864 if (extData.NEG & 0x2) {
2865 src1.negModifier();
2866 }
2867
2871 assert(!(instData.ABS & 0x4));
2872 assert(!(extData.NEG & 0x4));
2873
2874 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2875 if (wf->execMask(lane)) {
2876 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
2877 }
2878 }
2879
2880 sdst.write();
2881 } // execute
2882 // --- Inst_VOP3__V_CMP_LE_F64 class methods ---
2883
2884 Inst_VOP3__V_CMP_LE_F64::Inst_VOP3__V_CMP_LE_F64(
2885 InFmt_VOP3A *iFmt)
2886 : Inst_VOP3A(iFmt, "v_cmp_le_f64", true)
2887 {
2888 setFlag(ALU);
2889 setFlag(F64);
2890 } // Inst_VOP3__V_CMP_LE_F64
2891
2892 Inst_VOP3__V_CMP_LE_F64::~Inst_VOP3__V_CMP_LE_F64()
2893 {
2894 } // ~Inst_VOP3__V_CMP_LE_F64
2895
2896 // --- description from .arch file ---
2897 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
2898 void
2899 Inst_VOP3__V_CMP_LE_F64::execute(GPUDynInstPtr gpuDynInst)
2900 {
2901 Wavefront *wf = gpuDynInst->wavefront();
2902 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
2903 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
2904 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2905
2906 src0.readSrc();
2907 src1.readSrc();
2908
2909 if (instData.ABS & 0x1) {
2910 src0.absModifier();
2911 }
2912
2913 if (instData.ABS & 0x2) {
2914 src1.absModifier();
2915 }
2916
2917 if (extData.NEG & 0x1) {
2918 src0.negModifier();
2919 }
2920
2921 if (extData.NEG & 0x2) {
2922 src1.negModifier();
2923 }
2924
2928 assert(!(instData.ABS & 0x4));
2929 assert(!(extData.NEG & 0x4));
2930
2931 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2932 if (wf->execMask(lane)) {
2933 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
2934 }
2935 }
2936
2937 sdst.write();
2938 } // execute
2939 // --- Inst_VOP3__V_CMP_GT_F64 class methods ---
2940
2941 Inst_VOP3__V_CMP_GT_F64::Inst_VOP3__V_CMP_GT_F64(
2942 InFmt_VOP3A *iFmt)
2943 : Inst_VOP3A(iFmt, "v_cmp_gt_f64", true)
2944 {
2945 setFlag(ALU);
2946 setFlag(F64);
2947 } // Inst_VOP3__V_CMP_GT_F64
2948
2949 Inst_VOP3__V_CMP_GT_F64::~Inst_VOP3__V_CMP_GT_F64()
2950 {
2951 } // ~Inst_VOP3__V_CMP_GT_F64
2952
2953 // --- description from .arch file ---
2954 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
2955 void
2956 Inst_VOP3__V_CMP_GT_F64::execute(GPUDynInstPtr gpuDynInst)
2957 {
2958 Wavefront *wf = gpuDynInst->wavefront();
2959 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
2960 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
2961 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
2962
2963 src0.readSrc();
2964 src1.readSrc();
2965
2966 if (instData.ABS & 0x1) {
2967 src0.absModifier();
2968 }
2969
2970 if (instData.ABS & 0x2) {
2971 src1.absModifier();
2972 }
2973
2974 if (extData.NEG & 0x1) {
2975 src0.negModifier();
2976 }
2977
2978 if (extData.NEG & 0x2) {
2979 src1.negModifier();
2980 }
2981
2985 assert(!(instData.ABS & 0x4));
2986 assert(!(extData.NEG & 0x4));
2987
2988 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
2989 if (wf->execMask(lane)) {
2990 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
2991 }
2992 }
2993
2994 sdst.write();
2995 } // execute
2996 // --- Inst_VOP3__V_CMP_LG_F64 class methods ---
2997
2998 Inst_VOP3__V_CMP_LG_F64::Inst_VOP3__V_CMP_LG_F64(
2999 InFmt_VOP3A *iFmt)
3000 : Inst_VOP3A(iFmt, "v_cmp_lg_f64", true)
3001 {
3002 setFlag(ALU);
3003 setFlag(F64);
3004 } // Inst_VOP3__V_CMP_LG_F64
3005
3006 Inst_VOP3__V_CMP_LG_F64::~Inst_VOP3__V_CMP_LG_F64()
3007 {
3008 } // ~Inst_VOP3__V_CMP_LG_F64
3009
3010 // --- description from .arch file ---
3011 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
3012 void
3013 Inst_VOP3__V_CMP_LG_F64::execute(GPUDynInstPtr gpuDynInst)
3014 {
3015 Wavefront *wf = gpuDynInst->wavefront();
3016 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3017 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3018 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3019
3020 src0.readSrc();
3021 src1.readSrc();
3022
3023 if (instData.ABS & 0x1) {
3024 src0.absModifier();
3025 }
3026
3027 if (instData.ABS & 0x2) {
3028 src1.absModifier();
3029 }
3030
3031 if (extData.NEG & 0x1) {
3032 src0.negModifier();
3033 }
3034
3035 if (extData.NEG & 0x2) {
3036 src1.negModifier();
3037 }
3038
3042 assert(!(instData.ABS & 0x4));
3043 assert(!(extData.NEG & 0x4));
3044
3045 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3046 if (wf->execMask(lane)) {
3047 sdst.setBit(lane, (src0[lane] < src1[lane]
3048 || src0[lane] > src1[lane]) ? 1 : 0);
3049 }
3050 }
3051
3052 sdst.write();
3053 } // execute
3054 // --- Inst_VOP3__V_CMP_GE_F64 class methods ---
3055
3056 Inst_VOP3__V_CMP_GE_F64::Inst_VOP3__V_CMP_GE_F64(
3057 InFmt_VOP3A *iFmt)
3058 : Inst_VOP3A(iFmt, "v_cmp_ge_f64", true)
3059 {
3060 setFlag(ALU);
3061 setFlag(F64);
3062 } // Inst_VOP3__V_CMP_GE_F64
3063
3064 Inst_VOP3__V_CMP_GE_F64::~Inst_VOP3__V_CMP_GE_F64()
3065 {
3066 } // ~Inst_VOP3__V_CMP_GE_F64
3067
3068 // --- description from .arch file ---
3069 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
3070 void
3071 Inst_VOP3__V_CMP_GE_F64::execute(GPUDynInstPtr gpuDynInst)
3072 {
3073 Wavefront *wf = gpuDynInst->wavefront();
3074 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3075 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3076 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3077
3078 src0.readSrc();
3079 src1.readSrc();
3080
3081 if (instData.ABS & 0x1) {
3082 src0.absModifier();
3083 }
3084
3085 if (instData.ABS & 0x2) {
3086 src1.absModifier();
3087 }
3088
3089 if (extData.NEG & 0x1) {
3090 src0.negModifier();
3091 }
3092
3093 if (extData.NEG & 0x2) {
3094 src1.negModifier();
3095 }
3096
3100 assert(!(instData.ABS & 0x4));
3101 assert(!(extData.NEG & 0x4));
3102
3103 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3104 if (wf->execMask(lane)) {
3105 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
3106 }
3107 }
3108
3109 sdst.write();
3110 } // execute
3111 // --- Inst_VOP3__V_CMP_O_F64 class methods ---
3112
3113 Inst_VOP3__V_CMP_O_F64::Inst_VOP3__V_CMP_O_F64(InFmt_VOP3A *iFmt)
3114 : Inst_VOP3A(iFmt, "v_cmp_o_f64", true)
3115 {
3116 setFlag(ALU);
3117 setFlag(F64);
3118 } // Inst_VOP3__V_CMP_O_F64
3119
3120 Inst_VOP3__V_CMP_O_F64::~Inst_VOP3__V_CMP_O_F64()
3121 {
3122 } // ~Inst_VOP3__V_CMP_O_F64
3123
3124 // --- description from .arch file ---
3125 // D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC encoding.
3126 void
3127 Inst_VOP3__V_CMP_O_F64::execute(GPUDynInstPtr gpuDynInst)
3128 {
3129 Wavefront *wf = gpuDynInst->wavefront();
3130 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3131 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3132 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3133
3134 src0.readSrc();
3135 src1.readSrc();
3136
3137 if (instData.ABS & 0x1) {
3138 src0.absModifier();
3139 }
3140
3141 if (instData.ABS & 0x2) {
3142 src1.absModifier();
3143 }
3144
3145 if (extData.NEG & 0x1) {
3146 src0.negModifier();
3147 }
3148
3149 if (extData.NEG & 0x2) {
3150 src1.negModifier();
3151 }
3152
3156 assert(!(instData.ABS & 0x4));
3157 assert(!(extData.NEG & 0x4));
3158
3159 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3160 if (wf->execMask(lane)) {
3161 sdst.setBit(lane, (!std::isnan(src0[lane])
3162 && !std::isnan(src1[lane])) ? 1 : 0);
3163 }
3164 }
3165
3166 sdst.write();
3167 } // execute
3168 // --- Inst_VOP3__V_CMP_U_F64 class methods ---
3169
3170 Inst_VOP3__V_CMP_U_F64::Inst_VOP3__V_CMP_U_F64(InFmt_VOP3A *iFmt)
3171 : Inst_VOP3A(iFmt, "v_cmp_u_f64", true)
3172 {
3173 setFlag(ALU);
3174 setFlag(F64);
3175 } // Inst_VOP3__V_CMP_U_F64
3176
3177 Inst_VOP3__V_CMP_U_F64::~Inst_VOP3__V_CMP_U_F64()
3178 {
3179 } // ~Inst_VOP3__V_CMP_U_F64
3180
3181 // --- description from .arch file ---
3182 // D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC encoding.
3183 void
3184 Inst_VOP3__V_CMP_U_F64::execute(GPUDynInstPtr gpuDynInst)
3185 {
3186 Wavefront *wf = gpuDynInst->wavefront();
3187 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3188 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3189 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3190
3191 src0.readSrc();
3192 src1.readSrc();
3193
3194 if (instData.ABS & 0x1) {
3195 src0.absModifier();
3196 }
3197
3198 if (instData.ABS & 0x2) {
3199 src1.absModifier();
3200 }
3201
3202 if (extData.NEG & 0x1) {
3203 src0.negModifier();
3204 }
3205
3206 if (extData.NEG & 0x2) {
3207 src1.negModifier();
3208 }
3209
3213 assert(!(instData.ABS & 0x4));
3214 assert(!(extData.NEG & 0x4));
3215
3216 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3217 if (wf->execMask(lane)) {
3218 sdst.setBit(lane, (std::isnan(src0[lane])
3219 || std::isnan(src1[lane])) ? 1 : 0);
3220 }
3221 }
3222
3223 sdst.write();
3224 } // execute
3225 // --- Inst_VOP3__V_CMP_NGE_F64 class methods ---
3226
3227 Inst_VOP3__V_CMP_NGE_F64::Inst_VOP3__V_CMP_NGE_F64(
3228 InFmt_VOP3A *iFmt)
3229 : Inst_VOP3A(iFmt, "v_cmp_nge_f64", true)
3230 {
3231 setFlag(ALU);
3232 setFlag(F64);
3233 } // Inst_VOP3__V_CMP_NGE_F64
3234
3235 Inst_VOP3__V_CMP_NGE_F64::~Inst_VOP3__V_CMP_NGE_F64()
3236 {
3237 } // ~Inst_VOP3__V_CMP_NGE_F64
3238
3239 // --- description from .arch file ---
3240 // D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
3241 void
3242 Inst_VOP3__V_CMP_NGE_F64::execute(GPUDynInstPtr gpuDynInst)
3243 {
3244 Wavefront *wf = gpuDynInst->wavefront();
3245 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3246 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3247 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3248
3249 src0.readSrc();
3250 src1.readSrc();
3251
3252 if (instData.ABS & 0x1) {
3253 src0.absModifier();
3254 }
3255
3256 if (instData.ABS & 0x2) {
3257 src1.absModifier();
3258 }
3259
3260 if (extData.NEG & 0x1) {
3261 src0.negModifier();
3262 }
3263
3264 if (extData.NEG & 0x2) {
3265 src1.negModifier();
3266 }
3267
3271 assert(!(instData.ABS & 0x4));
3272 assert(!(extData.NEG & 0x4));
3273
3274 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3275 if (wf->execMask(lane)) {
3276 sdst.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
3277 }
3278 }
3279
3280 sdst.write();
3281 } // execute
3282 // --- Inst_VOP3__V_CMP_NLG_F64 class methods ---
3283
3284 Inst_VOP3__V_CMP_NLG_F64::Inst_VOP3__V_CMP_NLG_F64(
3285 InFmt_VOP3A *iFmt)
3286 : Inst_VOP3A(iFmt, "v_cmp_nlg_f64", true)
3287 {
3288 setFlag(ALU);
3289 setFlag(F64);
3290 } // Inst_VOP3__V_CMP_NLG_F64
3291
3292 Inst_VOP3__V_CMP_NLG_F64::~Inst_VOP3__V_CMP_NLG_F64()
3293 {
3294 } // ~Inst_VOP3__V_CMP_NLG_F64
3295
3296 // --- description from .arch file ---
3297 // D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
3298 void
3299 Inst_VOP3__V_CMP_NLG_F64::execute(GPUDynInstPtr gpuDynInst)
3300 {
3301 Wavefront *wf = gpuDynInst->wavefront();
3302 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3303 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3304 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3305
3306 src0.readSrc();
3307 src1.readSrc();
3308
3309 if (instData.ABS & 0x1) {
3310 src0.absModifier();
3311 }
3312
3313 if (instData.ABS & 0x2) {
3314 src1.absModifier();
3315 }
3316
3317 if (extData.NEG & 0x1) {
3318 src0.negModifier();
3319 }
3320
3321 if (extData.NEG & 0x2) {
3322 src1.negModifier();
3323 }
3324
3328 assert(!(instData.ABS & 0x4));
3329 assert(!(extData.NEG & 0x4));
3330
3331 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3332 if (wf->execMask(lane)) {
3333 sdst.setBit(lane, !(src0[lane] < src1[lane]
3334 || src0[lane] > src1[lane]) ? 1 : 0);
3335 }
3336 }
3337
3338 sdst.write();
3339 } // execute
3340 // --- Inst_VOP3__V_CMP_NGT_F64 class methods ---
3341
3342 Inst_VOP3__V_CMP_NGT_F64::Inst_VOP3__V_CMP_NGT_F64(
3343 InFmt_VOP3A *iFmt)
3344 : Inst_VOP3A(iFmt, "v_cmp_ngt_f64", true)
3345 {
3346 setFlag(ALU);
3347 setFlag(F64);
3348 } // Inst_VOP3__V_CMP_NGT_F64
3349
3350 Inst_VOP3__V_CMP_NGT_F64::~Inst_VOP3__V_CMP_NGT_F64()
3351 {
3352 } // ~Inst_VOP3__V_CMP_NGT_F64
3353
3354 // --- description from .arch file ---
3355 // D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
3356 void
3357 Inst_VOP3__V_CMP_NGT_F64::execute(GPUDynInstPtr gpuDynInst)
3358 {
3359 Wavefront *wf = gpuDynInst->wavefront();
3360 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3361 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3362 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3363
3364 src0.readSrc();
3365 src1.readSrc();
3366
3367 if (instData.ABS & 0x1) {
3368 src0.absModifier();
3369 }
3370
3371 if (instData.ABS & 0x2) {
3372 src1.absModifier();
3373 }
3374
3375 if (extData.NEG & 0x1) {
3376 src0.negModifier();
3377 }
3378
3379 if (extData.NEG & 0x2) {
3380 src1.negModifier();
3381 }
3382
3386 assert(!(instData.ABS & 0x4));
3387 assert(!(extData.NEG & 0x4));
3388
3389 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3390 if (wf->execMask(lane)) {
3391 sdst.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
3392 }
3393 }
3394
3395 sdst.write();
3396 } // execute
3397 // --- Inst_VOP3__V_CMP_NLE_F64 class methods ---
3398
3399 Inst_VOP3__V_CMP_NLE_F64::Inst_VOP3__V_CMP_NLE_F64(
3400 InFmt_VOP3A *iFmt)
3401 : Inst_VOP3A(iFmt, "v_cmp_nle_f64", true)
3402 {
3403 setFlag(ALU);
3404 setFlag(F64);
3405 } // Inst_VOP3__V_CMP_NLE_F64
3406
3407 Inst_VOP3__V_CMP_NLE_F64::~Inst_VOP3__V_CMP_NLE_F64()
3408 {
3409 } // ~Inst_VOP3__V_CMP_NLE_F64
3410
3411 // --- description from .arch file ---
3412 // D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
3413 void
3414 Inst_VOP3__V_CMP_NLE_F64::execute(GPUDynInstPtr gpuDynInst)
3415 {
3416 Wavefront *wf = gpuDynInst->wavefront();
3417 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3418 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3419 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3420
3421 src0.readSrc();
3422 src1.readSrc();
3423
3424 if (instData.ABS & 0x1) {
3425 src0.absModifier();
3426 }
3427
3428 if (instData.ABS & 0x2) {
3429 src1.absModifier();
3430 }
3431
3432 if (extData.NEG & 0x1) {
3433 src0.negModifier();
3434 }
3435
3436 if (extData.NEG & 0x2) {
3437 src1.negModifier();
3438 }
3439
3443 assert(!(instData.ABS & 0x4));
3444 assert(!(extData.NEG & 0x4));
3445
3446 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3447 if (wf->execMask(lane)) {
3448 sdst.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
3449 }
3450 }
3451
3452 sdst.write();
3453 } // execute
3454 // --- Inst_VOP3__V_CMP_NEQ_F64 class methods ---
3455
3456 Inst_VOP3__V_CMP_NEQ_F64::Inst_VOP3__V_CMP_NEQ_F64(
3457 InFmt_VOP3A *iFmt)
3458 : Inst_VOP3A(iFmt, "v_cmp_neq_f64", true)
3459 {
3460 setFlag(ALU);
3461 setFlag(F64);
3462 } // Inst_VOP3__V_CMP_NEQ_F64
3463
3464 Inst_VOP3__V_CMP_NEQ_F64::~Inst_VOP3__V_CMP_NEQ_F64()
3465 {
3466 } // ~Inst_VOP3__V_CMP_NEQ_F64
3467
3468 // --- description from .arch file ---
3469 // D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
3470 void
3471 Inst_VOP3__V_CMP_NEQ_F64::execute(GPUDynInstPtr gpuDynInst)
3472 {
3473 Wavefront *wf = gpuDynInst->wavefront();
3474 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3475 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3476 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3477
3478 src0.readSrc();
3479 src1.readSrc();
3480
3481 if (instData.ABS & 0x1) {
3482 src0.absModifier();
3483 }
3484
3485 if (instData.ABS & 0x2) {
3486 src1.absModifier();
3487 }
3488
3489 if (extData.NEG & 0x1) {
3490 src0.negModifier();
3491 }
3492
3493 if (extData.NEG & 0x2) {
3494 src1.negModifier();
3495 }
3496
3500 assert(!(instData.ABS & 0x4));
3501 assert(!(extData.NEG & 0x4));
3502
3503 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3504 if (wf->execMask(lane)) {
3505 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
3506 }
3507 }
3508
3509 sdst.write();
3510 } // execute
3511 // --- Inst_VOP3__V_CMP_NLT_F64 class methods ---
3512
3513 Inst_VOP3__V_CMP_NLT_F64::Inst_VOP3__V_CMP_NLT_F64(
3514 InFmt_VOP3A *iFmt)
3515 : Inst_VOP3A(iFmt, "v_cmp_nlt_f64", true)
3516 {
3517 setFlag(ALU);
3518 setFlag(F64);
3519 } // Inst_VOP3__V_CMP_NLT_F64
3520
3521 Inst_VOP3__V_CMP_NLT_F64::~Inst_VOP3__V_CMP_NLT_F64()
3522 {
3523 } // ~Inst_VOP3__V_CMP_NLT_F64
3524
3525 // --- description from .arch file ---
3526 // D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
3527 void
3528 Inst_VOP3__V_CMP_NLT_F64::execute(GPUDynInstPtr gpuDynInst)
3529 {
3530 Wavefront *wf = gpuDynInst->wavefront();
3531 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3532 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3533 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3534
3535 src0.readSrc();
3536 src1.readSrc();
3537
3538 if (instData.ABS & 0x1) {
3539 src0.absModifier();
3540 }
3541
3542 if (instData.ABS & 0x2) {
3543 src1.absModifier();
3544 }
3545
3546 if (extData.NEG & 0x1) {
3547 src0.negModifier();
3548 }
3549
3550 if (extData.NEG & 0x2) {
3551 src1.negModifier();
3552 }
3553
3557 assert(!(instData.ABS & 0x4));
3558 assert(!(extData.NEG & 0x4));
3559
3560 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3561 if (wf->execMask(lane)) {
3562 sdst.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
3563 }
3564 }
3565
3566 sdst.write();
3567 } // execute
3568 // --- Inst_VOP3__V_CMP_TRU_F64 class methods ---
3569
3570 Inst_VOP3__V_CMP_TRU_F64::Inst_VOP3__V_CMP_TRU_F64(
3571 InFmt_VOP3A *iFmt)
3572 : Inst_VOP3A(iFmt, "v_cmp_tru_f64", true)
3573 {
3574 setFlag(ALU);
3575 setFlag(F64);
3576 } // Inst_VOP3__V_CMP_TRU_F64
3577
3578 Inst_VOP3__V_CMP_TRU_F64::~Inst_VOP3__V_CMP_TRU_F64()
3579 {
3580 } // ~Inst_VOP3__V_CMP_TRU_F64
3581
3582 // --- description from .arch file ---
3583 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
3584 void
3585 Inst_VOP3__V_CMP_TRU_F64::execute(GPUDynInstPtr gpuDynInst)
3586 {
3587 Wavefront *wf = gpuDynInst->wavefront();
3588 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3589
3590 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3591 if (wf->execMask(lane)) {
3592 sdst.setBit(lane, 1);
3593 }
3594 }
3595
3596 sdst.write();
3597 } // execute
3598 // --- Inst_VOP3__V_CMPX_F_F64 class methods ---
3599
3600 Inst_VOP3__V_CMPX_F_F64::Inst_VOP3__V_CMPX_F_F64(
3601 InFmt_VOP3A *iFmt)
3602 : Inst_VOP3A(iFmt, "v_cmpx_f_f64", true)
3603 {
3604 setFlag(ALU);
3605 setFlag(F64);
3606 setFlag(WritesEXEC);
3607 } // Inst_VOP3__V_CMPX_F_F64
3608
3609 Inst_VOP3__V_CMPX_F_F64::~Inst_VOP3__V_CMPX_F_F64()
3610 {
3611 } // ~Inst_VOP3__V_CMPX_F_F64
3612
3613 // --- description from .arch file ---
3614 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
3615 void
3616 Inst_VOP3__V_CMPX_F_F64::execute(GPUDynInstPtr gpuDynInst)
3617 {
3618 Wavefront *wf = gpuDynInst->wavefront();
3619 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3620
3621 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3622 if (wf->execMask(lane)) {
3623 sdst.setBit(lane, 0);
3624 }
3625 }
3626
3627 wf->execMask() = sdst.rawData();
3628 sdst.write();
3629 } // execute
3630 // --- Inst_VOP3__V_CMPX_LT_F64 class methods ---
3631
3632 Inst_VOP3__V_CMPX_LT_F64::Inst_VOP3__V_CMPX_LT_F64(
3633 InFmt_VOP3A *iFmt)
3634 : Inst_VOP3A(iFmt, "v_cmpx_lt_f64", true)
3635 {
3636 setFlag(ALU);
3637 setFlag(F64);
3638 setFlag(WritesEXEC);
3639 } // Inst_VOP3__V_CMPX_LT_F64
3640
3641 Inst_VOP3__V_CMPX_LT_F64::~Inst_VOP3__V_CMPX_LT_F64()
3642 {
3643 } // ~Inst_VOP3__V_CMPX_LT_F64
3644
3645 // --- description from .arch file ---
3646 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
3647 void
3648 Inst_VOP3__V_CMPX_LT_F64::execute(GPUDynInstPtr gpuDynInst)
3649 {
3650 Wavefront *wf = gpuDynInst->wavefront();
3651 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3652 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3653 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3654
3655 src0.readSrc();
3656 src1.readSrc();
3657
3658 if (instData.ABS & 0x1) {
3659 src0.absModifier();
3660 }
3661
3662 if (instData.ABS & 0x2) {
3663 src1.absModifier();
3664 }
3665
3666 if (extData.NEG & 0x1) {
3667 src0.negModifier();
3668 }
3669
3670 if (extData.NEG & 0x2) {
3671 src1.negModifier();
3672 }
3673
3677 assert(!(instData.ABS & 0x4));
3678 assert(!(extData.NEG & 0x4));
3679
3680 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3681 if (wf->execMask(lane)) {
3682 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
3683 }
3684 }
3685
3686 wf->execMask() = sdst.rawData();
3687 sdst.write();
3688 } // execute
3689 // --- Inst_VOP3__V_CMPX_EQ_F64 class methods ---
3690
3691 Inst_VOP3__V_CMPX_EQ_F64::Inst_VOP3__V_CMPX_EQ_F64(
3692 InFmt_VOP3A *iFmt)
3693 : Inst_VOP3A(iFmt, "v_cmpx_eq_f64", true)
3694 {
3695 setFlag(ALU);
3696 setFlag(F64);
3697 setFlag(WritesEXEC);
3698 } // Inst_VOP3__V_CMPX_EQ_F64
3699
3700 Inst_VOP3__V_CMPX_EQ_F64::~Inst_VOP3__V_CMPX_EQ_F64()
3701 {
3702 } // ~Inst_VOP3__V_CMPX_EQ_F64
3703
3704 // --- description from .arch file ---
3705 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
3706 void
3707 Inst_VOP3__V_CMPX_EQ_F64::execute(GPUDynInstPtr gpuDynInst)
3708 {
3709 Wavefront *wf = gpuDynInst->wavefront();
3710 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3711 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3712 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3713
3714 src0.readSrc();
3715 src1.readSrc();
3716
3717 if (instData.ABS & 0x1) {
3718 src0.absModifier();
3719 }
3720
3721 if (instData.ABS & 0x2) {
3722 src1.absModifier();
3723 }
3724
3725 if (extData.NEG & 0x1) {
3726 src0.negModifier();
3727 }
3728
3729 if (extData.NEG & 0x2) {
3730 src1.negModifier();
3731 }
3732
3736 assert(!(instData.ABS & 0x4));
3737 assert(!(extData.NEG & 0x4));
3738
3739 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3740 if (wf->execMask(lane)) {
3741 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
3742 }
3743 }
3744
3745 wf->execMask() = sdst.rawData();
3746 sdst.write();
3747 } // execute
3748 // --- Inst_VOP3__V_CMPX_LE_F64 class methods ---
3749
3750 Inst_VOP3__V_CMPX_LE_F64::Inst_VOP3__V_CMPX_LE_F64(
3751 InFmt_VOP3A *iFmt)
3752 : Inst_VOP3A(iFmt, "v_cmpx_le_f64", true)
3753 {
3754 setFlag(ALU);
3755 setFlag(F64);
3756 setFlag(WritesEXEC);
3757 } // Inst_VOP3__V_CMPX_LE_F64
3758
3759 Inst_VOP3__V_CMPX_LE_F64::~Inst_VOP3__V_CMPX_LE_F64()
3760 {
3761 } // ~Inst_VOP3__V_CMPX_LE_F64
3762
3763 // --- description from .arch file ---
3764 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
3765 void
3766 Inst_VOP3__V_CMPX_LE_F64::execute(GPUDynInstPtr gpuDynInst)
3767 {
3768 Wavefront *wf = gpuDynInst->wavefront();
3769 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3770 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3771 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3772
3773 src0.readSrc();
3774 src1.readSrc();
3775
3776 if (instData.ABS & 0x1) {
3777 src0.absModifier();
3778 }
3779
3780 if (instData.ABS & 0x2) {
3781 src1.absModifier();
3782 }
3783
3784 if (extData.NEG & 0x1) {
3785 src0.negModifier();
3786 }
3787
3788 if (extData.NEG & 0x2) {
3789 src1.negModifier();
3790 }
3791
3795 assert(!(instData.ABS & 0x4));
3796 assert(!(extData.NEG & 0x4));
3797
3798 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3799 if (wf->execMask(lane)) {
3800 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
3801 }
3802 }
3803
3804 wf->execMask() = sdst.rawData();
3805 sdst.write();
3806 } // execute
3807 // --- Inst_VOP3__V_CMPX_GT_F64 class methods ---
3808
3809 Inst_VOP3__V_CMPX_GT_F64::Inst_VOP3__V_CMPX_GT_F64(
3810 InFmt_VOP3A *iFmt)
3811 : Inst_VOP3A(iFmt, "v_cmpx_gt_f64", true)
3812 {
3813 setFlag(ALU);
3814 setFlag(F64);
3815 setFlag(WritesEXEC);
3816 } // Inst_VOP3__V_CMPX_GT_F64
3817
3818 Inst_VOP3__V_CMPX_GT_F64::~Inst_VOP3__V_CMPX_GT_F64()
3819 {
3820 } // ~Inst_VOP3__V_CMPX_GT_F64
3821
3822 // --- description from .arch file ---
3823 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
3824 void
3825 Inst_VOP3__V_CMPX_GT_F64::execute(GPUDynInstPtr gpuDynInst)
3826 {
3827 Wavefront *wf = gpuDynInst->wavefront();
3828 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3829 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3830 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3831
3832 src0.readSrc();
3833 src1.readSrc();
3834
3835 if (instData.ABS & 0x1) {
3836 src0.absModifier();
3837 }
3838
3839 if (instData.ABS & 0x2) {
3840 src1.absModifier();
3841 }
3842
3843 if (extData.NEG & 0x1) {
3844 src0.negModifier();
3845 }
3846
3847 if (extData.NEG & 0x2) {
3848 src1.negModifier();
3849 }
3850
3854 assert(!(instData.ABS & 0x4));
3855 assert(!(extData.NEG & 0x4));
3856
3857 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3858 if (wf->execMask(lane)) {
3859 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
3860 }
3861 }
3862
3863 wf->execMask() = sdst.rawData();
3864 sdst.write();
3865 } // execute
3866 // --- Inst_VOP3__V_CMPX_LG_F64 class methods ---
3867
3868 Inst_VOP3__V_CMPX_LG_F64::Inst_VOP3__V_CMPX_LG_F64(
3869 InFmt_VOP3A *iFmt)
3870 : Inst_VOP3A(iFmt, "v_cmpx_lg_f64", true)
3871 {
3872 setFlag(ALU);
3873 setFlag(F64);
3874 setFlag(WritesEXEC);
3875 } // Inst_VOP3__V_CMPX_LG_F64
3876
3877 Inst_VOP3__V_CMPX_LG_F64::~Inst_VOP3__V_CMPX_LG_F64()
3878 {
3879 } // ~Inst_VOP3__V_CMPX_LG_F64
3880
3881 // --- description from .arch file ---
3882 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
3883 void
3884 Inst_VOP3__V_CMPX_LG_F64::execute(GPUDynInstPtr gpuDynInst)
3885 {
3886 Wavefront *wf = gpuDynInst->wavefront();
3887 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3888 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3889 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3890
3891 src0.readSrc();
3892 src1.readSrc();
3893
3894 if (instData.ABS & 0x1) {
3895 src0.absModifier();
3896 }
3897
3898 if (instData.ABS & 0x2) {
3899 src1.absModifier();
3900 }
3901
3902 if (extData.NEG & 0x1) {
3903 src0.negModifier();
3904 }
3905
3906 if (extData.NEG & 0x2) {
3907 src1.negModifier();
3908 }
3909
3913 assert(!(instData.ABS & 0x4));
3914 assert(!(extData.NEG & 0x4));
3915
3916 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3917 if (wf->execMask(lane)) {
3918 sdst.setBit(lane, (src0[lane] < src1[lane]
3919 || src0[lane] > src1[lane]) ? 1 : 0);
3920 }
3921 }
3922
3923 wf->execMask() = sdst.rawData();
3924 sdst.write();
3925 } // execute
3926 // --- Inst_VOP3__V_CMPX_GE_F64 class methods ---
3927
3928 Inst_VOP3__V_CMPX_GE_F64::Inst_VOP3__V_CMPX_GE_F64(
3929 InFmt_VOP3A *iFmt)
3930 : Inst_VOP3A(iFmt, "v_cmpx_ge_f64", true)
3931 {
3932 setFlag(ALU);
3933 setFlag(F64);
3934 setFlag(WritesEXEC);
3935 } // Inst_VOP3__V_CMPX_GE_F64
3936
3937 Inst_VOP3__V_CMPX_GE_F64::~Inst_VOP3__V_CMPX_GE_F64()
3938 {
3939 } // ~Inst_VOP3__V_CMPX_GE_F64
3940
3941 // --- description from .arch file ---
3942 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
3943 void
3944 Inst_VOP3__V_CMPX_GE_F64::execute(GPUDynInstPtr gpuDynInst)
3945 {
3946 Wavefront *wf = gpuDynInst->wavefront();
3947 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
3948 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
3949 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
3950
3951 src0.readSrc();
3952 src1.readSrc();
3953
3954 if (instData.ABS & 0x1) {
3955 src0.absModifier();
3956 }
3957
3958 if (instData.ABS & 0x2) {
3959 src1.absModifier();
3960 }
3961
3962 if (extData.NEG & 0x1) {
3963 src0.negModifier();
3964 }
3965
3966 if (extData.NEG & 0x2) {
3967 src1.negModifier();
3968 }
3969
3973 assert(!(instData.ABS & 0x4));
3974 assert(!(extData.NEG & 0x4));
3975
3976 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
3977 if (wf->execMask(lane)) {
3978 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
3979 }
3980 }
3981
3982 wf->execMask() = sdst.rawData();
3983 sdst.write();
3984 } // execute
3985 // --- Inst_VOP3__V_CMPX_O_F64 class methods ---
3986
3987 Inst_VOP3__V_CMPX_O_F64::Inst_VOP3__V_CMPX_O_F64(
3988 InFmt_VOP3A *iFmt)
3989 : Inst_VOP3A(iFmt, "v_cmpx_o_f64", true)
3990 {
3991 setFlag(ALU);
3992 setFlag(F64);
3993 setFlag(WritesEXEC);
3994 } // Inst_VOP3__V_CMPX_O_F64
3995
3996 Inst_VOP3__V_CMPX_O_F64::~Inst_VOP3__V_CMPX_O_F64()
3997 {
3998 } // ~Inst_VOP3__V_CMPX_O_F64
3999
4000 // --- description from .arch file ---
4001 // EXEC,D.u64[threadID] = (!isNan(S0) && !isNan(S1)); D = VCC in VOPC
4002 // encoding.
4003 void
4004 Inst_VOP3__V_CMPX_O_F64::execute(GPUDynInstPtr gpuDynInst)
4005 {
4006 Wavefront *wf = gpuDynInst->wavefront();
4007 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
4008 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
4009 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4010
4011 src0.readSrc();
4012 src1.readSrc();
4013
4014 if (instData.ABS & 0x1) {
4015 src0.absModifier();
4016 }
4017
4018 if (instData.ABS & 0x2) {
4019 src1.absModifier();
4020 }
4021
4022 if (extData.NEG & 0x1) {
4023 src0.negModifier();
4024 }
4025
4026 if (extData.NEG & 0x2) {
4027 src1.negModifier();
4028 }
4029
4033 assert(!(instData.ABS & 0x4));
4034 assert(!(extData.NEG & 0x4));
4035
4036 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4037 if (wf->execMask(lane)) {
4038 sdst.setBit(lane, (!std::isnan(src0[lane])
4039 && !std::isnan(src1[lane])) ? 1 : 0);
4040 }
4041 }
4042
4043 wf->execMask() = sdst.rawData();
4044 sdst.write();
4045 } // execute
4046 // --- Inst_VOP3__V_CMPX_U_F64 class methods ---
4047
4048 Inst_VOP3__V_CMPX_U_F64::Inst_VOP3__V_CMPX_U_F64(
4049 InFmt_VOP3A *iFmt)
4050 : Inst_VOP3A(iFmt, "v_cmpx_u_f64", true)
4051 {
4052 setFlag(ALU);
4053 setFlag(F64);
4054 setFlag(WritesEXEC);
4055 } // Inst_VOP3__V_CMPX_U_F64
4056
4057 Inst_VOP3__V_CMPX_U_F64::~Inst_VOP3__V_CMPX_U_F64()
4058 {
4059 } // ~Inst_VOP3__V_CMPX_U_F64
4060
4061 // --- description from .arch file ---
4062 // EXEC,D.u64[threadID] = (isNan(S0) || isNan(S1)); D = VCC in VOPC
4063 // encoding.
4064 void
4065 Inst_VOP3__V_CMPX_U_F64::execute(GPUDynInstPtr gpuDynInst)
4066 {
4067 Wavefront *wf = gpuDynInst->wavefront();
4068 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
4069 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
4070 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4071
4072 src0.readSrc();
4073 src1.readSrc();
4074
4075 if (instData.ABS & 0x1) {
4076 src0.absModifier();
4077 }
4078
4079 if (instData.ABS & 0x2) {
4080 src1.absModifier();
4081 }
4082
4083 if (extData.NEG & 0x1) {
4084 src0.negModifier();
4085 }
4086
4087 if (extData.NEG & 0x2) {
4088 src1.negModifier();
4089 }
4090
4094 assert(!(instData.ABS & 0x4));
4095 assert(!(extData.NEG & 0x4));
4096
4097 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4098 if (wf->execMask(lane)) {
4099 sdst.setBit(lane, (std::isnan(src0[lane])
4100 || std::isnan(src1[lane])) ? 1 : 0);
4101 }
4102 }
4103
4104 wf->execMask() = sdst.rawData();
4105 sdst.write();
4106 } // execute
4107 // --- Inst_VOP3__V_CMPX_NGE_F64 class methods ---
4108
4109 Inst_VOP3__V_CMPX_NGE_F64::Inst_VOP3__V_CMPX_NGE_F64(
4110 InFmt_VOP3A *iFmt)
4111 : Inst_VOP3A(iFmt, "v_cmpx_nge_f64", true)
4112 {
4113 setFlag(ALU);
4114 setFlag(F64);
4115 setFlag(WritesEXEC);
4116 } // Inst_VOP3__V_CMPX_NGE_F64
4117
4118 Inst_VOP3__V_CMPX_NGE_F64::~Inst_VOP3__V_CMPX_NGE_F64()
4119 {
4120 } // ~Inst_VOP3__V_CMPX_NGE_F64
4121
4122 // --- description from .arch file ---
4123 // EXEC,D.u64[threadID] = !(S0 >= S1); D = VCC in VOPC encoding.
4124 void
4125 Inst_VOP3__V_CMPX_NGE_F64::execute(GPUDynInstPtr gpuDynInst)
4126 {
4127 Wavefront *wf = gpuDynInst->wavefront();
4128 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
4129 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
4130 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4131
4132 src0.readSrc();
4133 src1.readSrc();
4134
4135 if (instData.ABS & 0x1) {
4136 src0.absModifier();
4137 }
4138
4139 if (instData.ABS & 0x2) {
4140 src1.absModifier();
4141 }
4142
4143 if (extData.NEG & 0x1) {
4144 src0.negModifier();
4145 }
4146
4147 if (extData.NEG & 0x2) {
4148 src1.negModifier();
4149 }
4150
4154 assert(!(instData.ABS & 0x4));
4155 assert(!(extData.NEG & 0x4));
4156
4157 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4158 if (wf->execMask(lane)) {
4159 sdst.setBit(lane, !(src0[lane] >= src1[lane]) ? 1 : 0);
4160 }
4161 }
4162
4163 wf->execMask() = sdst.rawData();
4164 sdst.write();
4165 } // execute
4166 // --- Inst_VOP3__V_CMPX_NLG_F64 class methods ---
4167
4168 Inst_VOP3__V_CMPX_NLG_F64::Inst_VOP3__V_CMPX_NLG_F64(
4169 InFmt_VOP3A *iFmt)
4170 : Inst_VOP3A(iFmt, "v_cmpx_nlg_f64", true)
4171 {
4172 setFlag(ALU);
4173 setFlag(F64);
4174 setFlag(WritesEXEC);
4175 } // Inst_VOP3__V_CMPX_NLG_F64
4176
4177 Inst_VOP3__V_CMPX_NLG_F64::~Inst_VOP3__V_CMPX_NLG_F64()
4178 {
4179 } // ~Inst_VOP3__V_CMPX_NLG_F64
4180
4181 // --- description from .arch file ---
4182 // EXEC,D.u64[threadID] = !(S0 <> S1); D = VCC in VOPC encoding.
4183 void
4184 Inst_VOP3__V_CMPX_NLG_F64::execute(GPUDynInstPtr gpuDynInst)
4185 {
4186 Wavefront *wf = gpuDynInst->wavefront();
4187 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
4188 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
4189 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4190
4191 src0.readSrc();
4192 src1.readSrc();
4193
4194 if (instData.ABS & 0x1) {
4195 src0.absModifier();
4196 }
4197
4198 if (instData.ABS & 0x2) {
4199 src1.absModifier();
4200 }
4201
4202 if (extData.NEG & 0x1) {
4203 src0.negModifier();
4204 }
4205
4206 if (extData.NEG & 0x2) {
4207 src1.negModifier();
4208 }
4209
4213 assert(!(instData.ABS & 0x4));
4214 assert(!(extData.NEG & 0x4));
4215
4216 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4217 if (wf->execMask(lane)) {
4218 sdst.setBit(lane, !(src0[lane] < src1[lane]
4219 || src0[lane] > src1[lane]) ? 1 : 0);
4220 }
4221 }
4222
4223 wf->execMask() = sdst.rawData();
4224 sdst.write();
4225 } // execute
4226 // --- Inst_VOP3__V_CMPX_NGT_F64 class methods ---
4227
4228 Inst_VOP3__V_CMPX_NGT_F64::Inst_VOP3__V_CMPX_NGT_F64(
4229 InFmt_VOP3A *iFmt)
4230 : Inst_VOP3A(iFmt, "v_cmpx_ngt_f64", true)
4231 {
4232 setFlag(ALU);
4233 setFlag(F64);
4234 setFlag(WritesEXEC);
4235 } // Inst_VOP3__V_CMPX_NGT_F64
4236
4237 Inst_VOP3__V_CMPX_NGT_F64::~Inst_VOP3__V_CMPX_NGT_F64()
4238 {
4239 } // ~Inst_VOP3__V_CMPX_NGT_F64
4240
4241 // --- description from .arch file ---
4242 // EXEC,D.u64[threadID] = !(S0 > S1); D = VCC in VOPC encoding.
4243 void
4244 Inst_VOP3__V_CMPX_NGT_F64::execute(GPUDynInstPtr gpuDynInst)
4245 {
4246 Wavefront *wf = gpuDynInst->wavefront();
4247 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
4248 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
4249 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4250
4251 src0.readSrc();
4252 src1.readSrc();
4253
4254 if (instData.ABS & 0x1) {
4255 src0.absModifier();
4256 }
4257
4258 if (instData.ABS & 0x2) {
4259 src1.absModifier();
4260 }
4261
4262 if (extData.NEG & 0x1) {
4263 src0.negModifier();
4264 }
4265
4266 if (extData.NEG & 0x2) {
4267 src1.negModifier();
4268 }
4269
4273 assert(!(instData.ABS & 0x4));
4274 assert(!(extData.NEG & 0x4));
4275
4276 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4277 if (wf->execMask(lane)) {
4278 sdst.setBit(lane, !(src0[lane] > src1[lane]) ? 1 : 0);
4279 }
4280 }
4281
4282 wf->execMask() = sdst.rawData();
4283 sdst.write();
4284 } // execute
4285 // --- Inst_VOP3__V_CMPX_NLE_F64 class methods ---
4286
4287 Inst_VOP3__V_CMPX_NLE_F64::Inst_VOP3__V_CMPX_NLE_F64(
4288 InFmt_VOP3A *iFmt)
4289 : Inst_VOP3A(iFmt, "v_cmpx_nle_f64", true)
4290 {
4291 setFlag(ALU);
4292 setFlag(F64);
4293 setFlag(WritesEXEC);
4294 } // Inst_VOP3__V_CMPX_NLE_F64
4295
4296 Inst_VOP3__V_CMPX_NLE_F64::~Inst_VOP3__V_CMPX_NLE_F64()
4297 {
4298 } // ~Inst_VOP3__V_CMPX_NLE_F64
4299
4300 // --- description from .arch file ---
4301 // EXEC,D.u64[threadID] = !(S0 <= S1); D = VCC in VOPC encoding.
4302 void
4303 Inst_VOP3__V_CMPX_NLE_F64::execute(GPUDynInstPtr gpuDynInst)
4304 {
4305 Wavefront *wf = gpuDynInst->wavefront();
4306 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
4307 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
4308 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4309
4310 src0.readSrc();
4311 src1.readSrc();
4312
4313 if (instData.ABS & 0x1) {
4314 src0.absModifier();
4315 }
4316
4317 if (instData.ABS & 0x2) {
4318 src1.absModifier();
4319 }
4320
4321 if (extData.NEG & 0x1) {
4322 src0.negModifier();
4323 }
4324
4325 if (extData.NEG & 0x2) {
4326 src1.negModifier();
4327 }
4328
4332 assert(!(instData.ABS & 0x4));
4333 assert(!(extData.NEG & 0x4));
4334
4335 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4336 if (wf->execMask(lane)) {
4337 sdst.setBit(lane, !(src0[lane] <= src1[lane]) ? 1 : 0);
4338 }
4339 }
4340
4341 wf->execMask() = sdst.rawData();
4342 sdst.write();
4343 } // execute
4344 // --- Inst_VOP3__V_CMPX_NEQ_F64 class methods ---
4345
4346 Inst_VOP3__V_CMPX_NEQ_F64::Inst_VOP3__V_CMPX_NEQ_F64(
4347 InFmt_VOP3A *iFmt)
4348 : Inst_VOP3A(iFmt, "v_cmpx_neq_f64", true)
4349 {
4350 setFlag(ALU);
4351 setFlag(F64);
4352 setFlag(WritesEXEC);
4353 } // Inst_VOP3__V_CMPX_NEQ_F64
4354
4355 Inst_VOP3__V_CMPX_NEQ_F64::~Inst_VOP3__V_CMPX_NEQ_F64()
4356 {
4357 } // ~Inst_VOP3__V_CMPX_NEQ_F64
4358
4359 // --- description from .arch file ---
4360 // EXEC,D.u64[threadID] = !(S0 == S1); D = VCC in VOPC encoding.
4361 void
4362 Inst_VOP3__V_CMPX_NEQ_F64::execute(GPUDynInstPtr gpuDynInst)
4363 {
4364 Wavefront *wf = gpuDynInst->wavefront();
4365 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
4366 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
4367 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4368
4369 src0.readSrc();
4370 src1.readSrc();
4371
4372 if (instData.ABS & 0x1) {
4373 src0.absModifier();
4374 }
4375
4376 if (instData.ABS & 0x2) {
4377 src1.absModifier();
4378 }
4379
4380 if (extData.NEG & 0x1) {
4381 src0.negModifier();
4382 }
4383
4384 if (extData.NEG & 0x2) {
4385 src1.negModifier();
4386 }
4387
4391 assert(!(instData.ABS & 0x4));
4392 assert(!(extData.NEG & 0x4));
4393
4394 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4395 if (wf->execMask(lane)) {
4396 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
4397 }
4398 }
4399
4400 wf->execMask() = sdst.rawData();
4401 sdst.write();
4402 } // execute
4403 // --- Inst_VOP3__V_CMPX_NLT_F64 class methods ---
4404
4405 Inst_VOP3__V_CMPX_NLT_F64::Inst_VOP3__V_CMPX_NLT_F64(
4406 InFmt_VOP3A *iFmt)
4407 : Inst_VOP3A(iFmt, "v_cmpx_nlt_f64", true)
4408 {
4409 setFlag(ALU);
4410 setFlag(F64);
4411 setFlag(WritesEXEC);
4412 } // Inst_VOP3__V_CMPX_NLT_F64
4413
4414 Inst_VOP3__V_CMPX_NLT_F64::~Inst_VOP3__V_CMPX_NLT_F64()
4415 {
4416 } // ~Inst_VOP3__V_CMPX_NLT_F64
4417
4418 // --- description from .arch file ---
4419 // EXEC,D.u64[threadID] = !(S0 < S1); D = VCC in VOPC encoding.
4420 void
4421 Inst_VOP3__V_CMPX_NLT_F64::execute(GPUDynInstPtr gpuDynInst)
4422 {
4423 Wavefront *wf = gpuDynInst->wavefront();
4424 ConstVecOperandF64 src0(gpuDynInst, extData.SRC0);
4425 ConstVecOperandF64 src1(gpuDynInst, extData.SRC1);
4426 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4427
4428 src0.readSrc();
4429 src1.readSrc();
4430
4431 if (instData.ABS & 0x1) {
4432 src0.absModifier();
4433 }
4434
4435 if (instData.ABS & 0x2) {
4436 src1.absModifier();
4437 }
4438
4439 if (extData.NEG & 0x1) {
4440 src0.negModifier();
4441 }
4442
4443 if (extData.NEG & 0x2) {
4444 src1.negModifier();
4445 }
4446
4450 assert(!(instData.ABS & 0x4));
4451 assert(!(extData.NEG & 0x4));
4452
4453 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4454 if (wf->execMask(lane)) {
4455 sdst.setBit(lane, !(src0[lane] < src1[lane]) ? 1 : 0);
4456 }
4457 }
4458
4459 wf->execMask() = sdst.rawData();
4460 sdst.write();
4461 } // execute
4462 // --- Inst_VOP3__V_CMPX_TRU_F64 class methods ---
4463
4464 Inst_VOP3__V_CMPX_TRU_F64::Inst_VOP3__V_CMPX_TRU_F64(
4465 InFmt_VOP3A *iFmt)
4466 : Inst_VOP3A(iFmt, "v_cmpx_tru_f64", true)
4467 {
4468 setFlag(ALU);
4469 setFlag(F64);
4470 setFlag(WritesEXEC);
4471 } // Inst_VOP3__V_CMPX_TRU_F64
4472
4473 Inst_VOP3__V_CMPX_TRU_F64::~Inst_VOP3__V_CMPX_TRU_F64()
4474 {
4475 } // ~Inst_VOP3__V_CMPX_TRU_F64
4476
4477 // --- description from .arch file ---
4478 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
4479 void
4480 Inst_VOP3__V_CMPX_TRU_F64::execute(GPUDynInstPtr gpuDynInst)
4481 {
4482 Wavefront *wf = gpuDynInst->wavefront();
4483 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4484
4485 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4486 if (wf->execMask(lane)) {
4487 sdst.setBit(lane, 1);
4488 }
4489 }
4490
4491 wf->execMask() = sdst.rawData();
4492 sdst.write();
4493 } // execute
4494 // --- Inst_VOP3__V_CMP_F_I16 class methods ---
4495
4496 Inst_VOP3__V_CMP_F_I16::Inst_VOP3__V_CMP_F_I16(InFmt_VOP3A *iFmt)
4497 : Inst_VOP3A(iFmt, "v_cmp_f_i16", true)
4498 {
4499 setFlag(ALU);
4500 } // Inst_VOP3__V_CMP_F_I16
4501
4502 Inst_VOP3__V_CMP_F_I16::~Inst_VOP3__V_CMP_F_I16()
4503 {
4504 } // ~Inst_VOP3__V_CMP_F_I16
4505
4506 // --- description from .arch file ---
4507 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
4508 void
4509 Inst_VOP3__V_CMP_F_I16::execute(GPUDynInstPtr gpuDynInst)
4510 {
4511 Wavefront *wf = gpuDynInst->wavefront();
4512 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4513
4514 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4515 if (wf->execMask(lane)) {
4516 sdst.setBit(lane, 0);
4517 }
4518 }
4519
4520 sdst.write();
4521 } // execute
4522 // --- Inst_VOP3__V_CMP_LT_I16 class methods ---
4523
4524 Inst_VOP3__V_CMP_LT_I16::Inst_VOP3__V_CMP_LT_I16(
4525 InFmt_VOP3A *iFmt)
4526 : Inst_VOP3A(iFmt, "v_cmp_lt_i16", true)
4527 {
4528 setFlag(ALU);
4529 } // Inst_VOP3__V_CMP_LT_I16
4530
4531 Inst_VOP3__V_CMP_LT_I16::~Inst_VOP3__V_CMP_LT_I16()
4532 {
4533 } // ~Inst_VOP3__V_CMP_LT_I16
4534
4535 // --- description from .arch file ---
4536 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
4537 void
4538 Inst_VOP3__V_CMP_LT_I16::execute(GPUDynInstPtr gpuDynInst)
4539 {
4540 Wavefront *wf = gpuDynInst->wavefront();
4541 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
4542 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
4543 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4544
4545 src0.readSrc();
4546 src1.readSrc();
4547
4551 assert(!(instData.ABS & 0x1));
4552 assert(!(instData.ABS & 0x2));
4553 assert(!(instData.ABS & 0x4));
4554 assert(!(extData.NEG & 0x1));
4555 assert(!(extData.NEG & 0x2));
4556 assert(!(extData.NEG & 0x4));
4557
4558 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4559 if (wf->execMask(lane)) {
4560 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
4561 }
4562 }
4563
4564 sdst.write();
4565 } // execute
4566 // --- Inst_VOP3__V_CMP_EQ_I16 class methods ---
4567
4568 Inst_VOP3__V_CMP_EQ_I16::Inst_VOP3__V_CMP_EQ_I16(
4569 InFmt_VOP3A *iFmt)
4570 : Inst_VOP3A(iFmt, "v_cmp_eq_i16", true)
4571 {
4572 setFlag(ALU);
4573 } // Inst_VOP3__V_CMP_EQ_I16
4574
4575 Inst_VOP3__V_CMP_EQ_I16::~Inst_VOP3__V_CMP_EQ_I16()
4576 {
4577 } // ~Inst_VOP3__V_CMP_EQ_I16
4578
4579 // --- description from .arch file ---
4580 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
4581 void
4582 Inst_VOP3__V_CMP_EQ_I16::execute(GPUDynInstPtr gpuDynInst)
4583 {
4584 Wavefront *wf = gpuDynInst->wavefront();
4585 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
4586 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
4587 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4588
4589 src0.readSrc();
4590 src1.readSrc();
4591
4595 assert(!(instData.ABS & 0x1));
4596 assert(!(instData.ABS & 0x2));
4597 assert(!(instData.ABS & 0x4));
4598 assert(!(extData.NEG & 0x1));
4599 assert(!(extData.NEG & 0x2));
4600 assert(!(extData.NEG & 0x4));
4601
4602 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4603 if (wf->execMask(lane)) {
4604 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
4605 }
4606 }
4607
4608 sdst.write();
4609 } // execute
4610 // --- Inst_VOP3__V_CMP_LE_I16 class methods ---
4611
4612 Inst_VOP3__V_CMP_LE_I16::Inst_VOP3__V_CMP_LE_I16(
4613 InFmt_VOP3A *iFmt)
4614 : Inst_VOP3A(iFmt, "v_cmp_le_i16", true)
4615 {
4616 setFlag(ALU);
4617 } // Inst_VOP3__V_CMP_LE_I16
4618
4619 Inst_VOP3__V_CMP_LE_I16::~Inst_VOP3__V_CMP_LE_I16()
4620 {
4621 } // ~Inst_VOP3__V_CMP_LE_I16
4622
4623 // --- description from .arch file ---
4624 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
4625 void
4626 Inst_VOP3__V_CMP_LE_I16::execute(GPUDynInstPtr gpuDynInst)
4627 {
4628 Wavefront *wf = gpuDynInst->wavefront();
4629 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
4630 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
4631 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4632
4633 src0.readSrc();
4634 src1.readSrc();
4635
4639 assert(!(instData.ABS & 0x1));
4640 assert(!(instData.ABS & 0x2));
4641 assert(!(instData.ABS & 0x4));
4642 assert(!(extData.NEG & 0x1));
4643 assert(!(extData.NEG & 0x2));
4644 assert(!(extData.NEG & 0x4));
4645
4646 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4647 if (wf->execMask(lane)) {
4648 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
4649 }
4650 }
4651
4652 sdst.write();
4653 } // execute
4654 // --- Inst_VOP3__V_CMP_GT_I16 class methods ---
4655
4656 Inst_VOP3__V_CMP_GT_I16::Inst_VOP3__V_CMP_GT_I16(
4657 InFmt_VOP3A *iFmt)
4658 : Inst_VOP3A(iFmt, "v_cmp_gt_i16", true)
4659 {
4660 setFlag(ALU);
4661 } // Inst_VOP3__V_CMP_GT_I16
4662
4663 Inst_VOP3__V_CMP_GT_I16::~Inst_VOP3__V_CMP_GT_I16()
4664 {
4665 } // ~Inst_VOP3__V_CMP_GT_I16
4666
4667 // --- description from .arch file ---
4668 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
4669 void
4670 Inst_VOP3__V_CMP_GT_I16::execute(GPUDynInstPtr gpuDynInst)
4671 {
4672 Wavefront *wf = gpuDynInst->wavefront();
4673 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
4674 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
4675 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4676
4677 src0.readSrc();
4678 src1.readSrc();
4679
4683 assert(!(instData.ABS & 0x1));
4684 assert(!(instData.ABS & 0x2));
4685 assert(!(instData.ABS & 0x4));
4686 assert(!(extData.NEG & 0x1));
4687 assert(!(extData.NEG & 0x2));
4688 assert(!(extData.NEG & 0x4));
4689
4690 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4691 if (wf->execMask(lane)) {
4692 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
4693 }
4694 }
4695
4696 sdst.write();
4697 } // execute
4698 // --- Inst_VOP3__V_CMP_NE_I16 class methods ---
4699
4700 Inst_VOP3__V_CMP_NE_I16::Inst_VOP3__V_CMP_NE_I16(
4701 InFmt_VOP3A *iFmt)
4702 : Inst_VOP3A(iFmt, "v_cmp_ne_i16", true)
4703 {
4704 setFlag(ALU);
4705 } // Inst_VOP3__V_CMP_NE_I16
4706
4707 Inst_VOP3__V_CMP_NE_I16::~Inst_VOP3__V_CMP_NE_I16()
4708 {
4709 } // ~Inst_VOP3__V_CMP_NE_I16
4710
4711 // --- description from .arch file ---
4712 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
4713 void
4714 Inst_VOP3__V_CMP_NE_I16::execute(GPUDynInstPtr gpuDynInst)
4715 {
4716 Wavefront *wf = gpuDynInst->wavefront();
4717 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
4718 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
4719 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4720
4721 src0.readSrc();
4722 src1.readSrc();
4723
4727 assert(!(instData.ABS & 0x1));
4728 assert(!(instData.ABS & 0x2));
4729 assert(!(instData.ABS & 0x4));
4730 assert(!(extData.NEG & 0x1));
4731 assert(!(extData.NEG & 0x2));
4732 assert(!(extData.NEG & 0x4));
4733
4734 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4735 if (wf->execMask(lane)) {
4736 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
4737 }
4738 }
4739
4740 sdst.write();
4741 } // execute
4742 // --- Inst_VOP3__V_CMP_GE_I16 class methods ---
4743
4744 Inst_VOP3__V_CMP_GE_I16::Inst_VOP3__V_CMP_GE_I16(
4745 InFmt_VOP3A *iFmt)
4746 : Inst_VOP3A(iFmt, "v_cmp_ge_i16", true)
4747 {
4748 setFlag(ALU);
4749 } // Inst_VOP3__V_CMP_GE_I16
4750
4751 Inst_VOP3__V_CMP_GE_I16::~Inst_VOP3__V_CMP_GE_I16()
4752 {
4753 } // ~Inst_VOP3__V_CMP_GE_I16
4754
4755 // --- description from .arch file ---
4756 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
4757 void
4758 Inst_VOP3__V_CMP_GE_I16::execute(GPUDynInstPtr gpuDynInst)
4759 {
4760 Wavefront *wf = gpuDynInst->wavefront();
4761 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
4762 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
4763 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4764
4765 src0.readSrc();
4766 src1.readSrc();
4767
4771 assert(!(instData.ABS & 0x1));
4772 assert(!(instData.ABS & 0x2));
4773 assert(!(instData.ABS & 0x4));
4774 assert(!(extData.NEG & 0x1));
4775 assert(!(extData.NEG & 0x2));
4776 assert(!(extData.NEG & 0x4));
4777
4778 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4779 if (wf->execMask(lane)) {
4780 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
4781 }
4782 }
4783
4784 sdst.write();
4785 } // execute
4786 // --- Inst_VOP3__V_CMP_T_I16 class methods ---
4787
4788 Inst_VOP3__V_CMP_T_I16::Inst_VOP3__V_CMP_T_I16(InFmt_VOP3A *iFmt)
4789 : Inst_VOP3A(iFmt, "v_cmp_t_i16", true)
4790 {
4791 setFlag(ALU);
4792 } // Inst_VOP3__V_CMP_T_I16
4793
4794 Inst_VOP3__V_CMP_T_I16::~Inst_VOP3__V_CMP_T_I16()
4795 {
4796 } // ~Inst_VOP3__V_CMP_T_I16
4797
4798 // --- description from .arch file ---
4799 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
4800 void
4801 Inst_VOP3__V_CMP_T_I16::execute(GPUDynInstPtr gpuDynInst)
4802 {
4803 Wavefront *wf = gpuDynInst->wavefront();
4804 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4805
4806 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4807 if (wf->execMask(lane)) {
4808 sdst.setBit(lane, 1);
4809 }
4810 }
4811
4812 sdst.write();
4813 } // execute
4814 // --- Inst_VOP3__V_CMP_F_U16 class methods ---
4815
4816 Inst_VOP3__V_CMP_F_U16::Inst_VOP3__V_CMP_F_U16(InFmt_VOP3A *iFmt)
4817 : Inst_VOP3A(iFmt, "v_cmp_f_u16", true)
4818 {
4819 setFlag(ALU);
4820 } // Inst_VOP3__V_CMP_F_U16
4821
4822 Inst_VOP3__V_CMP_F_U16::~Inst_VOP3__V_CMP_F_U16()
4823 {
4824 } // ~Inst_VOP3__V_CMP_F_U16
4825
4826 // --- description from .arch file ---
4827 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
4828 void
4829 Inst_VOP3__V_CMP_F_U16::execute(GPUDynInstPtr gpuDynInst)
4830 {
4831 Wavefront *wf = gpuDynInst->wavefront();
4832 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4833
4834 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4835 if (wf->execMask(lane)) {
4836 sdst.setBit(lane, 0);
4837 }
4838 }
4839
4840 sdst.write();
4841 } // execute
4842 // --- Inst_VOP3__V_CMP_LT_U16 class methods ---
4843
4844 Inst_VOP3__V_CMP_LT_U16::Inst_VOP3__V_CMP_LT_U16(
4845 InFmt_VOP3A *iFmt)
4846 : Inst_VOP3A(iFmt, "v_cmp_lt_u16", true)
4847 {
4848 setFlag(ALU);
4849 } // Inst_VOP3__V_CMP_LT_U16
4850
4851 Inst_VOP3__V_CMP_LT_U16::~Inst_VOP3__V_CMP_LT_U16()
4852 {
4853 } // ~Inst_VOP3__V_CMP_LT_U16
4854
4855 // --- description from .arch file ---
4856 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
4857 void
4858 Inst_VOP3__V_CMP_LT_U16::execute(GPUDynInstPtr gpuDynInst)
4859 {
4860 Wavefront *wf = gpuDynInst->wavefront();
4861 ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
4862 ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
4863 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4864
4865 src0.readSrc();
4866 src1.readSrc();
4867
4871 assert(!(instData.ABS & 0x1));
4872 assert(!(instData.ABS & 0x2));
4873 assert(!(instData.ABS & 0x4));
4874 assert(!(extData.NEG & 0x1));
4875 assert(!(extData.NEG & 0x2));
4876 assert(!(extData.NEG & 0x4));
4877
4878 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4879 if (wf->execMask(lane)) {
4880 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
4881 }
4882 }
4883
4884 sdst.write();
4885 } // execute
4886 // --- Inst_VOP3__V_CMP_EQ_U16 class methods ---
4887
4888 Inst_VOP3__V_CMP_EQ_U16::Inst_VOP3__V_CMP_EQ_U16(
4889 InFmt_VOP3A *iFmt)
4890 : Inst_VOP3A(iFmt, "v_cmp_eq_u16", true)
4891 {
4892 setFlag(ALU);
4893 } // Inst_VOP3__V_CMP_EQ_U16
4894
4895 Inst_VOP3__V_CMP_EQ_U16::~Inst_VOP3__V_CMP_EQ_U16()
4896 {
4897 } // ~Inst_VOP3__V_CMP_EQ_U16
4898
4899 // --- description from .arch file ---
4900 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
4901 void
4902 Inst_VOP3__V_CMP_EQ_U16::execute(GPUDynInstPtr gpuDynInst)
4903 {
4904 Wavefront *wf = gpuDynInst->wavefront();
4905 ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
4906 ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
4907 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4908
4909 src0.readSrc();
4910 src1.readSrc();
4911
4915 assert(!(instData.ABS & 0x1));
4916 assert(!(instData.ABS & 0x2));
4917 assert(!(instData.ABS & 0x4));
4918 assert(!(extData.NEG & 0x1));
4919 assert(!(extData.NEG & 0x2));
4920 assert(!(extData.NEG & 0x4));
4921
4922 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4923 if (wf->execMask(lane)) {
4924 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
4925 }
4926 }
4927
4928 sdst.write();
4929 } // execute
4930 // --- Inst_VOP3__V_CMP_LE_U16 class methods ---
4931
4932 Inst_VOP3__V_CMP_LE_U16::Inst_VOP3__V_CMP_LE_U16(
4933 InFmt_VOP3A *iFmt)
4934 : Inst_VOP3A(iFmt, "v_cmp_le_u16", true)
4935 {
4936 setFlag(ALU);
4937 } // Inst_VOP3__V_CMP_LE_U16
4938
4939 Inst_VOP3__V_CMP_LE_U16::~Inst_VOP3__V_CMP_LE_U16()
4940 {
4941 } // ~Inst_VOP3__V_CMP_LE_U16
4942
4943 // --- description from .arch file ---
4944 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
4945 void
4946 Inst_VOP3__V_CMP_LE_U16::execute(GPUDynInstPtr gpuDynInst)
4947 {
4948 Wavefront *wf = gpuDynInst->wavefront();
4949 ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
4950 ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
4951 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4952
4953 src0.readSrc();
4954 src1.readSrc();
4955
4959 assert(!(instData.ABS & 0x1));
4960 assert(!(instData.ABS & 0x2));
4961 assert(!(instData.ABS & 0x4));
4962 assert(!(extData.NEG & 0x1));
4963 assert(!(extData.NEG & 0x2));
4964 assert(!(extData.NEG & 0x4));
4965
4966 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
4967 if (wf->execMask(lane)) {
4968 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
4969 }
4970 }
4971
4972 sdst.write();
4973 } // execute
4974 // --- Inst_VOP3__V_CMP_GT_U16 class methods ---
4975
4976 Inst_VOP3__V_CMP_GT_U16::Inst_VOP3__V_CMP_GT_U16(
4977 InFmt_VOP3A *iFmt)
4978 : Inst_VOP3A(iFmt, "v_cmp_gt_u16", true)
4979 {
4980 setFlag(ALU);
4981 } // Inst_VOP3__V_CMP_GT_U16
4982
4983 Inst_VOP3__V_CMP_GT_U16::~Inst_VOP3__V_CMP_GT_U16()
4984 {
4985 } // ~Inst_VOP3__V_CMP_GT_U16
4986
4987 // --- description from .arch file ---
4988 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
4989 void
4990 Inst_VOP3__V_CMP_GT_U16::execute(GPUDynInstPtr gpuDynInst)
4991 {
4992 Wavefront *wf = gpuDynInst->wavefront();
4993 ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
4994 ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
4995 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
4996
4997 src0.readSrc();
4998 src1.readSrc();
4999
5003 assert(!(instData.ABS & 0x1));
5004 assert(!(instData.ABS & 0x2));
5005 assert(!(instData.ABS & 0x4));
5006 assert(!(extData.NEG & 0x1));
5007 assert(!(extData.NEG & 0x2));
5008 assert(!(extData.NEG & 0x4));
5009
5010 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5011 if (wf->execMask(lane)) {
5012 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
5013 }
5014 }
5015
5016 sdst.write();
5017 } // execute
5018 // --- Inst_VOP3__V_CMP_NE_U16 class methods ---
5019
5020 Inst_VOP3__V_CMP_NE_U16::Inst_VOP3__V_CMP_NE_U16(
5021 InFmt_VOP3A *iFmt)
5022 : Inst_VOP3A(iFmt, "v_cmp_ne_u16", true)
5023 {
5024 setFlag(ALU);
5025 } // Inst_VOP3__V_CMP_NE_U16
5026
5027 Inst_VOP3__V_CMP_NE_U16::~Inst_VOP3__V_CMP_NE_U16()
5028 {
5029 } // ~Inst_VOP3__V_CMP_NE_U16
5030
5031 // --- description from .arch file ---
5032 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
5033 void
5034 Inst_VOP3__V_CMP_NE_U16::execute(GPUDynInstPtr gpuDynInst)
5035 {
5036 Wavefront *wf = gpuDynInst->wavefront();
5037 ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
5038 ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
5039 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5040
5041 src0.readSrc();
5042 src1.readSrc();
5043
5047 assert(!(instData.ABS & 0x1));
5048 assert(!(instData.ABS & 0x2));
5049 assert(!(instData.ABS & 0x4));
5050 assert(!(extData.NEG & 0x1));
5051 assert(!(extData.NEG & 0x2));
5052 assert(!(extData.NEG & 0x4));
5053
5054 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5055 if (wf->execMask(lane)) {
5056 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
5057 }
5058 }
5059
5060 sdst.write();
5061 } // execute
5062 // --- Inst_VOP3__V_CMP_GE_U16 class methods ---
5063
5064 Inst_VOP3__V_CMP_GE_U16::Inst_VOP3__V_CMP_GE_U16(
5065 InFmt_VOP3A *iFmt)
5066 : Inst_VOP3A(iFmt, "v_cmp_ge_u16", true)
5067 {
5068 setFlag(ALU);
5069 } // Inst_VOP3__V_CMP_GE_U16
5070
5071 Inst_VOP3__V_CMP_GE_U16::~Inst_VOP3__V_CMP_GE_U16()
5072 {
5073 } // ~Inst_VOP3__V_CMP_GE_U16
5074
5075 // --- description from .arch file ---
5076 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
5077 void
5078 Inst_VOP3__V_CMP_GE_U16::execute(GPUDynInstPtr gpuDynInst)
5079 {
5080 Wavefront *wf = gpuDynInst->wavefront();
5081 ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
5082 ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
5083 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5084
5085 src0.readSrc();
5086 src1.readSrc();
5087
5091 assert(!(instData.ABS & 0x1));
5092 assert(!(instData.ABS & 0x2));
5093 assert(!(instData.ABS & 0x4));
5094 assert(!(extData.NEG & 0x1));
5095 assert(!(extData.NEG & 0x2));
5096 assert(!(extData.NEG & 0x4));
5097
5098 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5099 if (wf->execMask(lane)) {
5100 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
5101 }
5102 }
5103
5104 sdst.write();
5105 } // execute
5106 // --- Inst_VOP3__V_CMP_T_U16 class methods ---
5107
5108 Inst_VOP3__V_CMP_T_U16::Inst_VOP3__V_CMP_T_U16(InFmt_VOP3A *iFmt)
5109 : Inst_VOP3A(iFmt, "v_cmp_t_u16", true)
5110 {
5111 setFlag(ALU);
5112 } // Inst_VOP3__V_CMP_T_U16
5113
5114 Inst_VOP3__V_CMP_T_U16::~Inst_VOP3__V_CMP_T_U16()
5115 {
5116 } // ~Inst_VOP3__V_CMP_T_U16
5117
5118 // --- description from .arch file ---
5119 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
5120 void
5121 Inst_VOP3__V_CMP_T_U16::execute(GPUDynInstPtr gpuDynInst)
5122 {
5123 Wavefront *wf = gpuDynInst->wavefront();
5124 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5125
5126 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5127 if (wf->execMask(lane)) {
5128 sdst.setBit(lane, 1);
5129 }
5130 }
5131
5132 sdst.write();
5133 } // execute
5134 // --- Inst_VOP3__V_CMPX_F_I16 class methods ---
5135
5136 Inst_VOP3__V_CMPX_F_I16::Inst_VOP3__V_CMPX_F_I16(
5137 InFmt_VOP3A *iFmt)
5138 : Inst_VOP3A(iFmt, "v_cmpx_f_i16", true)
5139 {
5140 setFlag(ALU);
5141 setFlag(WritesEXEC);
5142 } // Inst_VOP3__V_CMPX_F_I16
5143
5144 Inst_VOP3__V_CMPX_F_I16::~Inst_VOP3__V_CMPX_F_I16()
5145 {
5146 } // ~Inst_VOP3__V_CMPX_F_I16
5147
5148 // --- description from .arch file ---
5149 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
5150 void
5151 Inst_VOP3__V_CMPX_F_I16::execute(GPUDynInstPtr gpuDynInst)
5152 {
5153 Wavefront *wf = gpuDynInst->wavefront();
5154 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5155
5156 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5157 if (wf->execMask(lane)) {
5158 sdst.setBit(lane, 0);
5159 }
5160 }
5161
5162 wf->execMask() = sdst.rawData();
5163 sdst.write();
5164 } // execute
5165 // --- Inst_VOP3__V_CMPX_LT_I16 class methods ---
5166
5167 Inst_VOP3__V_CMPX_LT_I16::Inst_VOP3__V_CMPX_LT_I16(
5168 InFmt_VOP3A *iFmt)
5169 : Inst_VOP3A(iFmt, "v_cmpx_lt_i16", true)
5170 {
5171 setFlag(ALU);
5172 setFlag(WritesEXEC);
5173 } // Inst_VOP3__V_CMPX_LT_I16
5174
5175 Inst_VOP3__V_CMPX_LT_I16::~Inst_VOP3__V_CMPX_LT_I16()
5176 {
5177 } // ~Inst_VOP3__V_CMPX_LT_I16
5178
5179 // --- description from .arch file ---
5180 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
5181 void
5182 Inst_VOP3__V_CMPX_LT_I16::execute(GPUDynInstPtr gpuDynInst)
5183 {
5184 Wavefront *wf = gpuDynInst->wavefront();
5185 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
5186 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
5187 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5188
5189 src0.readSrc();
5190 src1.readSrc();
5191
5195 assert(!(instData.ABS & 0x1));
5196 assert(!(instData.ABS & 0x2));
5197 assert(!(instData.ABS & 0x4));
5198 assert(!(extData.NEG & 0x1));
5199 assert(!(extData.NEG & 0x2));
5200 assert(!(extData.NEG & 0x4));
5201
5202 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5203 if (wf->execMask(lane)) {
5204 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
5205 }
5206 }
5207
5208 wf->execMask() = sdst.rawData();
5209 sdst.write();
5210 } // execute
5211 // --- Inst_VOP3__V_CMPX_EQ_I16 class methods ---
5212
5213 Inst_VOP3__V_CMPX_EQ_I16::Inst_VOP3__V_CMPX_EQ_I16(
5214 InFmt_VOP3A *iFmt)
5215 : Inst_VOP3A(iFmt, "v_cmpx_eq_i16", true)
5216 {
5217 setFlag(ALU);
5218 setFlag(WritesEXEC);
5219 } // Inst_VOP3__V_CMPX_EQ_I16
5220
5221 Inst_VOP3__V_CMPX_EQ_I16::~Inst_VOP3__V_CMPX_EQ_I16()
5222 {
5223 } // ~Inst_VOP3__V_CMPX_EQ_I16
5224
5225 // --- description from .arch file ---
5226 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
5227 void
5228 Inst_VOP3__V_CMPX_EQ_I16::execute(GPUDynInstPtr gpuDynInst)
5229 {
5230 Wavefront *wf = gpuDynInst->wavefront();
5231 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
5232 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
5233 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5234
5235 src0.readSrc();
5236 src1.readSrc();
5237
5241 assert(!(instData.ABS & 0x1));
5242 assert(!(instData.ABS & 0x2));
5243 assert(!(instData.ABS & 0x4));
5244 assert(!(extData.NEG & 0x1));
5245 assert(!(extData.NEG & 0x2));
5246 assert(!(extData.NEG & 0x4));
5247
5248 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5249 if (wf->execMask(lane)) {
5250 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
5251 }
5252 }
5253
5254 wf->execMask() = sdst.rawData();
5255 sdst.write();
5256 } // execute
5257 // --- Inst_VOP3__V_CMPX_LE_I16 class methods ---
5258
5259 Inst_VOP3__V_CMPX_LE_I16::Inst_VOP3__V_CMPX_LE_I16(
5260 InFmt_VOP3A *iFmt)
5261 : Inst_VOP3A(iFmt, "v_cmpx_le_i16", true)
5262 {
5263 setFlag(ALU);
5264 setFlag(WritesEXEC);
5265 } // Inst_VOP3__V_CMPX_LE_I16
5266
5267 Inst_VOP3__V_CMPX_LE_I16::~Inst_VOP3__V_CMPX_LE_I16()
5268 {
5269 } // ~Inst_VOP3__V_CMPX_LE_I16
5270
5271 // --- description from .arch file ---
5272 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
5273 void
5274 Inst_VOP3__V_CMPX_LE_I16::execute(GPUDynInstPtr gpuDynInst)
5275 {
5276 Wavefront *wf = gpuDynInst->wavefront();
5277 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
5278 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
5279 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5280
5281 src0.readSrc();
5282 src1.readSrc();
5283
5287 assert(!(instData.ABS & 0x1));
5288 assert(!(instData.ABS & 0x2));
5289 assert(!(instData.ABS & 0x4));
5290 assert(!(extData.NEG & 0x1));
5291 assert(!(extData.NEG & 0x2));
5292 assert(!(extData.NEG & 0x4));
5293
5294 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5295 if (wf->execMask(lane)) {
5296 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
5297 }
5298 }
5299
5300 wf->execMask() = sdst.rawData();
5301 sdst.write();
5302 } // execute
5303 // --- Inst_VOP3__V_CMPX_GT_I16 class methods ---
5304
5305 Inst_VOP3__V_CMPX_GT_I16::Inst_VOP3__V_CMPX_GT_I16(
5306 InFmt_VOP3A *iFmt)
5307 : Inst_VOP3A(iFmt, "v_cmpx_gt_i16", true)
5308 {
5309 setFlag(ALU);
5310 setFlag(WritesEXEC);
5311 } // Inst_VOP3__V_CMPX_GT_I16
5312
5313 Inst_VOP3__V_CMPX_GT_I16::~Inst_VOP3__V_CMPX_GT_I16()
5314 {
5315 } // ~Inst_VOP3__V_CMPX_GT_I16
5316
5317 // --- description from .arch file ---
5318 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
5319 void
5320 Inst_VOP3__V_CMPX_GT_I16::execute(GPUDynInstPtr gpuDynInst)
5321 {
5322 Wavefront *wf = gpuDynInst->wavefront();
5323 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
5324 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
5325 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5326
5327 src0.readSrc();
5328 src1.readSrc();
5329
5333 assert(!(instData.ABS & 0x1));
5334 assert(!(instData.ABS & 0x2));
5335 assert(!(instData.ABS & 0x4));
5336 assert(!(extData.NEG & 0x1));
5337 assert(!(extData.NEG & 0x2));
5338 assert(!(extData.NEG & 0x4));
5339
5340 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5341 if (wf->execMask(lane)) {
5342 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
5343 }
5344 }
5345
5346 wf->execMask() = sdst.rawData();
5347 sdst.write();
5348 } // execute
5349 // --- Inst_VOP3__V_CMPX_NE_I16 class methods ---
5350
5351 Inst_VOP3__V_CMPX_NE_I16::Inst_VOP3__V_CMPX_NE_I16(
5352 InFmt_VOP3A *iFmt)
5353 : Inst_VOP3A(iFmt, "v_cmpx_ne_i16", true)
5354 {
5355 setFlag(ALU);
5356 setFlag(WritesEXEC);
5357 } // Inst_VOP3__V_CMPX_NE_I16
5358
5359 Inst_VOP3__V_CMPX_NE_I16::~Inst_VOP3__V_CMPX_NE_I16()
5360 {
5361 } // ~Inst_VOP3__V_CMPX_NE_I16
5362
5363 // --- description from .arch file ---
5364 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
5365 void
5366 Inst_VOP3__V_CMPX_NE_I16::execute(GPUDynInstPtr gpuDynInst)
5367 {
5368 Wavefront *wf = gpuDynInst->wavefront();
5369 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
5370 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
5371 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5372
5373 src0.readSrc();
5374 src1.readSrc();
5375
5379 assert(!(instData.ABS & 0x1));
5380 assert(!(instData.ABS & 0x2));
5381 assert(!(instData.ABS & 0x4));
5382 assert(!(extData.NEG & 0x1));
5383 assert(!(extData.NEG & 0x2));
5384 assert(!(extData.NEG & 0x4));
5385
5386 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5387 if (wf->execMask(lane)) {
5388 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
5389 }
5390 }
5391
5392 wf->execMask() = sdst.rawData();
5393 sdst.write();
5394 } // execute
5395 // --- Inst_VOP3__V_CMPX_GE_I16 class methods ---
5396
5397 Inst_VOP3__V_CMPX_GE_I16::Inst_VOP3__V_CMPX_GE_I16(
5398 InFmt_VOP3A *iFmt)
5399 : Inst_VOP3A(iFmt, "v_cmpx_ge_i16", true)
5400 {
5401 setFlag(ALU);
5402 setFlag(WritesEXEC);
5403 } // Inst_VOP3__V_CMPX_GE_I16
5404
5405 Inst_VOP3__V_CMPX_GE_I16::~Inst_VOP3__V_CMPX_GE_I16()
5406 {
5407 } // ~Inst_VOP3__V_CMPX_GE_I16
5408
5409 // --- description from .arch file ---
5410 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
5411 void
5412 Inst_VOP3__V_CMPX_GE_I16::execute(GPUDynInstPtr gpuDynInst)
5413 {
5414 Wavefront *wf = gpuDynInst->wavefront();
5415 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
5416 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
5417 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5418
5419 src0.readSrc();
5420 src1.readSrc();
5421
5425 assert(!(instData.ABS & 0x1));
5426 assert(!(instData.ABS & 0x2));
5427 assert(!(instData.ABS & 0x4));
5428 assert(!(extData.NEG & 0x1));
5429 assert(!(extData.NEG & 0x2));
5430 assert(!(extData.NEG & 0x4));
5431
5432 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5433 if (wf->execMask(lane)) {
5434 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
5435 }
5436 }
5437
5438 wf->execMask() = sdst.rawData();
5439 sdst.write();
5440 } // execute
5441 // --- Inst_VOP3__V_CMPX_T_I16 class methods ---
5442
5443 Inst_VOP3__V_CMPX_T_I16::Inst_VOP3__V_CMPX_T_I16(
5444 InFmt_VOP3A *iFmt)
5445 : Inst_VOP3A(iFmt, "v_cmpx_t_i16", true)
5446 {
5447 setFlag(ALU);
5448 setFlag(WritesEXEC);
5449 } // Inst_VOP3__V_CMPX_T_I16
5450
5451 Inst_VOP3__V_CMPX_T_I16::~Inst_VOP3__V_CMPX_T_I16()
5452 {
5453 } // ~Inst_VOP3__V_CMPX_T_I16
5454
5455 // --- description from .arch file ---
5456 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
5457 void
5458 Inst_VOP3__V_CMPX_T_I16::execute(GPUDynInstPtr gpuDynInst)
5459 {
5460 Wavefront *wf = gpuDynInst->wavefront();
5461 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5462
5463 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5464 if (wf->execMask(lane)) {
5465 sdst.setBit(lane, 1);
5466 }
5467 }
5468
5469 wf->execMask() = sdst.rawData();
5470 sdst.write();
5471 } // execute
5472 // --- Inst_VOP3__V_CMPX_F_U16 class methods ---
5473
5474 Inst_VOP3__V_CMPX_F_U16::Inst_VOP3__V_CMPX_F_U16(
5475 InFmt_VOP3A *iFmt)
5476 : Inst_VOP3A(iFmt, "v_cmpx_f_u16", true)
5477 {
5478 setFlag(ALU);
5479 setFlag(WritesEXEC);
5480 } // Inst_VOP3__V_CMPX_F_U16
5481
5482 Inst_VOP3__V_CMPX_F_U16::~Inst_VOP3__V_CMPX_F_U16()
5483 {
5484 } // ~Inst_VOP3__V_CMPX_F_U16
5485
5486 // --- description from .arch file ---
5487 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
5488 void
5489 Inst_VOP3__V_CMPX_F_U16::execute(GPUDynInstPtr gpuDynInst)
5490 {
5491 Wavefront *wf = gpuDynInst->wavefront();
5492 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5493
5494 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5495 if (wf->execMask(lane)) {
5496 sdst.setBit(lane, 0);
5497 }
5498 }
5499
5500 wf->execMask() = sdst.rawData();
5501 sdst.write();
5502 } // execute
5503 // --- Inst_VOP3__V_CMPX_LT_U16 class methods ---
5504
5505 Inst_VOP3__V_CMPX_LT_U16::Inst_VOP3__V_CMPX_LT_U16(
5506 InFmt_VOP3A *iFmt)
5507 : Inst_VOP3A(iFmt, "v_cmpx_lt_u16", true)
5508 {
5509 setFlag(ALU);
5510 setFlag(WritesEXEC);
5511 } // Inst_VOP3__V_CMPX_LT_U16
5512
5513 Inst_VOP3__V_CMPX_LT_U16::~Inst_VOP3__V_CMPX_LT_U16()
5514 {
5515 } // ~Inst_VOP3__V_CMPX_LT_U16
5516
5517 // --- description from .arch file ---
5518 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
5519 void
5520 Inst_VOP3__V_CMPX_LT_U16::execute(GPUDynInstPtr gpuDynInst)
5521 {
5522 Wavefront *wf = gpuDynInst->wavefront();
5523 ConstVecOperandU16 src0(gpuDynInst, extData.SRC0);
5524 ConstVecOperandU16 src1(gpuDynInst, extData.SRC1);
5525 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5526
5527 src0.readSrc();
5528 src1.readSrc();
5529
5533 assert(!(instData.ABS & 0x1));
5534 assert(!(instData.ABS & 0x2));
5535 assert(!(instData.ABS & 0x4));
5536 assert(!(extData.NEG & 0x1));
5537 assert(!(extData.NEG & 0x2));
5538 assert(!(extData.NEG & 0x4));
5539
5540 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5541 if (wf->execMask(lane)) {
5542 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
5543 }
5544 }
5545
5546 wf->execMask() = sdst.rawData();
5547 sdst.write();
5548 } // execute
5549 // --- Inst_VOP3__V_CMPX_EQ_U16 class methods ---
5550
5551 Inst_VOP3__V_CMPX_EQ_U16::Inst_VOP3__V_CMPX_EQ_U16(
5552 InFmt_VOP3A *iFmt)
5553 : Inst_VOP3A(iFmt, "v_cmpx_eq_u16", true)
5554 {
5555 setFlag(ALU);
5556 setFlag(WritesEXEC);
5557 } // Inst_VOP3__V_CMPX_EQ_U16
5558
5559 Inst_VOP3__V_CMPX_EQ_U16::~Inst_VOP3__V_CMPX_EQ_U16()
5560 {
5561 } // ~Inst_VOP3__V_CMPX_EQ_U16
5562
5563 // --- description from .arch file ---
5564 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
5565 void
5566 Inst_VOP3__V_CMPX_EQ_U16::execute(GPUDynInstPtr gpuDynInst)
5567 {
5568 Wavefront *wf = gpuDynInst->wavefront();
5569 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
5570 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
5571 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5572
5573 src0.readSrc();
5574 src1.readSrc();
5575
5579 assert(!(instData.ABS & 0x1));
5580 assert(!(instData.ABS & 0x2));
5581 assert(!(instData.ABS & 0x4));
5582 assert(!(extData.NEG & 0x1));
5583 assert(!(extData.NEG & 0x2));
5584 assert(!(extData.NEG & 0x4));
5585
5586 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5587 if (wf->execMask(lane)) {
5588 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
5589 }
5590 }
5591
5592 wf->execMask() = sdst.rawData();
5593 sdst.write();
5594 } // execute
5595 // --- Inst_VOP3__V_CMPX_LE_U16 class methods ---
5596
5597 Inst_VOP3__V_CMPX_LE_U16::Inst_VOP3__V_CMPX_LE_U16(
5598 InFmt_VOP3A *iFmt)
5599 : Inst_VOP3A(iFmt, "v_cmpx_le_u16", true)
5600 {
5601 setFlag(ALU);
5602 setFlag(WritesEXEC);
5603 } // Inst_VOP3__V_CMPX_LE_U16
5604
5605 Inst_VOP3__V_CMPX_LE_U16::~Inst_VOP3__V_CMPX_LE_U16()
5606 {
5607 } // ~Inst_VOP3__V_CMPX_LE_U16
5608
5609 // --- description from .arch file ---
5610 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
5611 void
5612 Inst_VOP3__V_CMPX_LE_U16::execute(GPUDynInstPtr gpuDynInst)
5613 {
5614 Wavefront *wf = gpuDynInst->wavefront();
5615 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
5616 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
5617 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5618
5619 src0.readSrc();
5620 src1.readSrc();
5621
5625 assert(!(instData.ABS & 0x1));
5626 assert(!(instData.ABS & 0x2));
5627 assert(!(instData.ABS & 0x4));
5628 assert(!(extData.NEG & 0x1));
5629 assert(!(extData.NEG & 0x2));
5630 assert(!(extData.NEG & 0x4));
5631
5632 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5633 if (wf->execMask(lane)) {
5634 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
5635 }
5636 }
5637
5638 wf->execMask() = sdst.rawData();
5639 sdst.write();
5640 } // execute
5641 // --- Inst_VOP3__V_CMPX_GT_U16 class methods ---
5642
5643 Inst_VOP3__V_CMPX_GT_U16::Inst_VOP3__V_CMPX_GT_U16(
5644 InFmt_VOP3A *iFmt)
5645 : Inst_VOP3A(iFmt, "v_cmpx_gt_u16", true)
5646 {
5647 setFlag(ALU);
5648 setFlag(WritesEXEC);
5649 } // Inst_VOP3__V_CMPX_GT_U16
5650
5651 Inst_VOP3__V_CMPX_GT_U16::~Inst_VOP3__V_CMPX_GT_U16()
5652 {
5653 } // ~Inst_VOP3__V_CMPX_GT_U16
5654
5655 // --- description from .arch file ---
5656 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
5657 void
5658 Inst_VOP3__V_CMPX_GT_U16::execute(GPUDynInstPtr gpuDynInst)
5659 {
5660 Wavefront *wf = gpuDynInst->wavefront();
5661 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
5662 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
5663 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5664
5665 src0.readSrc();
5666 src1.readSrc();
5667
5671 assert(!(instData.ABS & 0x1));
5672 assert(!(instData.ABS & 0x2));
5673 assert(!(instData.ABS & 0x4));
5674 assert(!(extData.NEG & 0x1));
5675 assert(!(extData.NEG & 0x2));
5676 assert(!(extData.NEG & 0x4));
5677
5678 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5679 if (wf->execMask(lane)) {
5680 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
5681 }
5682 }
5683
5684 wf->execMask() = sdst.rawData();
5685 sdst.write();
5686 } // execute
5687 // --- Inst_VOP3__V_CMPX_NE_U16 class methods ---
5688
5689 Inst_VOP3__V_CMPX_NE_U16::Inst_VOP3__V_CMPX_NE_U16(
5690 InFmt_VOP3A *iFmt)
5691 : Inst_VOP3A(iFmt, "v_cmpx_ne_u16", true)
5692 {
5693 setFlag(ALU);
5694 setFlag(WritesEXEC);
5695 } // Inst_VOP3__V_CMPX_NE_U16
5696
5697 Inst_VOP3__V_CMPX_NE_U16::~Inst_VOP3__V_CMPX_NE_U16()
5698 {
5699 } // ~Inst_VOP3__V_CMPX_NE_U16
5700
5701 // --- description from .arch file ---
5702 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
5703 void
5704 Inst_VOP3__V_CMPX_NE_U16::execute(GPUDynInstPtr gpuDynInst)
5705 {
5706 Wavefront *wf = gpuDynInst->wavefront();
5707 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
5708 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
5709 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5710
5711 src0.readSrc();
5712 src1.readSrc();
5713
5717 assert(!(instData.ABS & 0x1));
5718 assert(!(instData.ABS & 0x2));
5719 assert(!(instData.ABS & 0x4));
5720 assert(!(extData.NEG & 0x1));
5721 assert(!(extData.NEG & 0x2));
5722 assert(!(extData.NEG & 0x4));
5723
5724 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5725 if (wf->execMask(lane)) {
5726 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
5727 }
5728 }
5729
5730 wf->execMask() = sdst.rawData();
5731 sdst.write();
5732 } // execute
5733 // --- Inst_VOP3__V_CMPX_GE_U16 class methods ---
5734
5735 Inst_VOP3__V_CMPX_GE_U16::Inst_VOP3__V_CMPX_GE_U16(
5736 InFmt_VOP3A *iFmt)
5737 : Inst_VOP3A(iFmt, "v_cmpx_ge_u16", true)
5738 {
5739 setFlag(ALU);
5740 setFlag(WritesEXEC);
5741 } // Inst_VOP3__V_CMPX_GE_U16
5742
5743 Inst_VOP3__V_CMPX_GE_U16::~Inst_VOP3__V_CMPX_GE_U16()
5744 {
5745 } // ~Inst_VOP3__V_CMPX_GE_U16
5746
5747 // --- description from .arch file ---
5748 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
5749 void
5750 Inst_VOP3__V_CMPX_GE_U16::execute(GPUDynInstPtr gpuDynInst)
5751 {
5752 Wavefront *wf = gpuDynInst->wavefront();
5753 ConstVecOperandI16 src0(gpuDynInst, extData.SRC0);
5754 ConstVecOperandI16 src1(gpuDynInst, extData.SRC1);
5755 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5756
5757 src0.readSrc();
5758 src1.readSrc();
5759
5763 assert(!(instData.ABS & 0x1));
5764 assert(!(instData.ABS & 0x2));
5765 assert(!(instData.ABS & 0x4));
5766 assert(!(extData.NEG & 0x1));
5767 assert(!(extData.NEG & 0x2));
5768 assert(!(extData.NEG & 0x4));
5769
5770 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5771 if (wf->execMask(lane)) {
5772 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
5773 }
5774 }
5775
5776 wf->execMask() = sdst.rawData();
5777 sdst.write();
5778 } // execute
5779 // --- Inst_VOP3__V_CMPX_T_U16 class methods ---
5780
5781 Inst_VOP3__V_CMPX_T_U16::Inst_VOP3__V_CMPX_T_U16(
5782 InFmt_VOP3A *iFmt)
5783 : Inst_VOP3A(iFmt, "v_cmpx_t_u16", true)
5784 {
5785 setFlag(ALU);
5786 setFlag(WritesEXEC);
5787 } // Inst_VOP3__V_CMPX_T_U16
5788
5789 Inst_VOP3__V_CMPX_T_U16::~Inst_VOP3__V_CMPX_T_U16()
5790 {
5791 } // ~Inst_VOP3__V_CMPX_T_U16
5792
5793 // --- description from .arch file ---
5794 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
5795 void
5796 Inst_VOP3__V_CMPX_T_U16::execute(GPUDynInstPtr gpuDynInst)
5797 {
5798 Wavefront *wf = gpuDynInst->wavefront();
5799 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5800
5801 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5802 if (wf->execMask(lane)) {
5803 sdst.setBit(lane, 1);
5804 }
5805 }
5806
5807 wf->execMask() = sdst.rawData();
5808 sdst.write();
5809 } // execute
5810 // --- Inst_VOP3__V_CMP_F_I32 class methods ---
5811
5812 Inst_VOP3__V_CMP_F_I32::Inst_VOP3__V_CMP_F_I32(InFmt_VOP3A *iFmt)
5813 : Inst_VOP3A(iFmt, "v_cmp_f_i32", true)
5814 {
5815 setFlag(ALU);
5816 } // Inst_VOP3__V_CMP_F_I32
5817
5818 Inst_VOP3__V_CMP_F_I32::~Inst_VOP3__V_CMP_F_I32()
5819 {
5820 } // ~Inst_VOP3__V_CMP_F_I32
5821
5822 // --- description from .arch file ---
5823 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
5824 void
5825 Inst_VOP3__V_CMP_F_I32::execute(GPUDynInstPtr gpuDynInst)
5826 {
5827 Wavefront *wf = gpuDynInst->wavefront();
5828 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5829
5830 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5831 if (wf->execMask(lane)) {
5832 sdst.setBit(lane, 0);
5833 }
5834 }
5835
5836 sdst.write();
5837 } // execute
5838 // --- Inst_VOP3__V_CMP_LT_I32 class methods ---
5839
5840 Inst_VOP3__V_CMP_LT_I32::Inst_VOP3__V_CMP_LT_I32(
5841 InFmt_VOP3A *iFmt)
5842 : Inst_VOP3A(iFmt, "v_cmp_lt_i32", true)
5843 {
5844 setFlag(ALU);
5845 } // Inst_VOP3__V_CMP_LT_I32
5846
5847 Inst_VOP3__V_CMP_LT_I32::~Inst_VOP3__V_CMP_LT_I32()
5848 {
5849 } // ~Inst_VOP3__V_CMP_LT_I32
5850
5851 // --- description from .arch file ---
5852 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
5853 void
5854 Inst_VOP3__V_CMP_LT_I32::execute(GPUDynInstPtr gpuDynInst)
5855 {
5856 Wavefront *wf = gpuDynInst->wavefront();
5857 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
5858 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
5859 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5860
5861 src0.readSrc();
5862 src1.readSrc();
5863
5867 assert(!(instData.ABS & 0x1));
5868 assert(!(instData.ABS & 0x2));
5869 assert(!(instData.ABS & 0x4));
5870 assert(!(extData.NEG & 0x1));
5871 assert(!(extData.NEG & 0x2));
5872 assert(!(extData.NEG & 0x4));
5873
5874 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5875 if (wf->execMask(lane)) {
5876 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
5877 }
5878 }
5879
5880 sdst.write();
5881 } // execute
5882 // --- Inst_VOP3__V_CMP_EQ_I32 class methods ---
5883
5884 Inst_VOP3__V_CMP_EQ_I32::Inst_VOP3__V_CMP_EQ_I32(
5885 InFmt_VOP3A *iFmt)
5886 : Inst_VOP3A(iFmt, "v_cmp_eq_i32", true)
5887 {
5888 setFlag(ALU);
5889 } // Inst_VOP3__V_CMP_EQ_I32
5890
5891 Inst_VOP3__V_CMP_EQ_I32::~Inst_VOP3__V_CMP_EQ_I32()
5892 {
5893 } // ~Inst_VOP3__V_CMP_EQ_I32
5894
5895 // --- description from .arch file ---
5896 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
5897 void
5898 Inst_VOP3__V_CMP_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
5899 {
5900 Wavefront *wf = gpuDynInst->wavefront();
5901 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
5902 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
5903 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5904
5905 src0.readSrc();
5906 src1.readSrc();
5907
5911 assert(!(instData.ABS & 0x1));
5912 assert(!(instData.ABS & 0x2));
5913 assert(!(instData.ABS & 0x4));
5914 assert(!(extData.NEG & 0x1));
5915 assert(!(extData.NEG & 0x2));
5916 assert(!(extData.NEG & 0x4));
5917
5918 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5919 if (wf->execMask(lane)) {
5920 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
5921 }
5922 }
5923
5924 sdst.write();
5925 } // execute
5926 // --- Inst_VOP3__V_CMP_LE_I32 class methods ---
5927
5928 Inst_VOP3__V_CMP_LE_I32::Inst_VOP3__V_CMP_LE_I32(
5929 InFmt_VOP3A *iFmt)
5930 : Inst_VOP3A(iFmt, "v_cmp_le_i32", true)
5931 {
5932 setFlag(ALU);
5933 } // Inst_VOP3__V_CMP_LE_I32
5934
5935 Inst_VOP3__V_CMP_LE_I32::~Inst_VOP3__V_CMP_LE_I32()
5936 {
5937 } // ~Inst_VOP3__V_CMP_LE_I32
5938
5939 // --- description from .arch file ---
5940 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
5941 void
5942 Inst_VOP3__V_CMP_LE_I32::execute(GPUDynInstPtr gpuDynInst)
5943 {
5944 Wavefront *wf = gpuDynInst->wavefront();
5945 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
5946 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
5947 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5948
5949 src0.readSrc();
5950 src1.readSrc();
5951
5955 assert(!(instData.ABS & 0x1));
5956 assert(!(instData.ABS & 0x2));
5957 assert(!(instData.ABS & 0x4));
5958 assert(!(extData.NEG & 0x1));
5959 assert(!(extData.NEG & 0x2));
5960 assert(!(extData.NEG & 0x4));
5961
5962 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
5963 if (wf->execMask(lane)) {
5964 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
5965 }
5966 }
5967
5968 sdst.write();
5969 } // execute
5970 // --- Inst_VOP3__V_CMP_GT_I32 class methods ---
5971
5972 Inst_VOP3__V_CMP_GT_I32::Inst_VOP3__V_CMP_GT_I32(
5973 InFmt_VOP3A *iFmt)
5974 : Inst_VOP3A(iFmt, "v_cmp_gt_i32", true)
5975 {
5976 setFlag(ALU);
5977 } // Inst_VOP3__V_CMP_GT_I32
5978
5979 Inst_VOP3__V_CMP_GT_I32::~Inst_VOP3__V_CMP_GT_I32()
5980 {
5981 } // ~Inst_VOP3__V_CMP_GT_I32
5982
5983 // --- description from .arch file ---
5984 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
5985 void
5986 Inst_VOP3__V_CMP_GT_I32::execute(GPUDynInstPtr gpuDynInst)
5987 {
5988 Wavefront *wf = gpuDynInst->wavefront();
5989 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
5990 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
5991 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
5992
5993 src0.readSrc();
5994 src1.readSrc();
5995
5999 assert(!(instData.ABS & 0x1));
6000 assert(!(instData.ABS & 0x2));
6001 assert(!(instData.ABS & 0x4));
6002 assert(!(extData.NEG & 0x1));
6003 assert(!(extData.NEG & 0x2));
6004 assert(!(extData.NEG & 0x4));
6005
6006 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6007 if (wf->execMask(lane)) {
6008 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
6009 }
6010 }
6011
6012 sdst.write();
6013 } // execute
6014 // --- Inst_VOP3__V_CMP_NE_I32 class methods ---
6015
6016 Inst_VOP3__V_CMP_NE_I32::Inst_VOP3__V_CMP_NE_I32(
6017 InFmt_VOP3A *iFmt)
6018 : Inst_VOP3A(iFmt, "v_cmp_ne_i32", true)
6019 {
6020 setFlag(ALU);
6021 } // Inst_VOP3__V_CMP_NE_I32
6022
6023 Inst_VOP3__V_CMP_NE_I32::~Inst_VOP3__V_CMP_NE_I32()
6024 {
6025 } // ~Inst_VOP3__V_CMP_NE_I32
6026
6027 // --- description from .arch file ---
6028 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
6029 void
6030 Inst_VOP3__V_CMP_NE_I32::execute(GPUDynInstPtr gpuDynInst)
6031 {
6032 Wavefront *wf = gpuDynInst->wavefront();
6033 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
6034 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
6035 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6036
6037 src0.readSrc();
6038 src1.readSrc();
6039
6043 assert(!(instData.ABS & 0x1));
6044 assert(!(instData.ABS & 0x2));
6045 assert(!(instData.ABS & 0x4));
6046 assert(!(extData.NEG & 0x1));
6047 assert(!(extData.NEG & 0x2));
6048 assert(!(extData.NEG & 0x4));
6049
6050 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6051 if (wf->execMask(lane)) {
6052 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
6053 }
6054 }
6055
6056 sdst.write();
6057 } // execute
6058 // --- Inst_VOP3__V_CMP_GE_I32 class methods ---
6059
6060 Inst_VOP3__V_CMP_GE_I32::Inst_VOP3__V_CMP_GE_I32(
6061 InFmt_VOP3A *iFmt)
6062 : Inst_VOP3A(iFmt, "v_cmp_ge_i32", true)
6063 {
6064 setFlag(ALU);
6065 } // Inst_VOP3__V_CMP_GE_I32
6066
6067 Inst_VOP3__V_CMP_GE_I32::~Inst_VOP3__V_CMP_GE_I32()
6068 {
6069 } // ~Inst_VOP3__V_CMP_GE_I32
6070
6071 // --- description from .arch file ---
6072 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
6073 void
6074 Inst_VOP3__V_CMP_GE_I32::execute(GPUDynInstPtr gpuDynInst)
6075 {
6076 Wavefront *wf = gpuDynInst->wavefront();
6077 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
6078 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
6079 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6080
6081 src0.readSrc();
6082 src1.readSrc();
6083
6087 assert(!(instData.ABS & 0x1));
6088 assert(!(instData.ABS & 0x2));
6089 assert(!(instData.ABS & 0x4));
6090 assert(!(extData.NEG & 0x1));
6091 assert(!(extData.NEG & 0x2));
6092 assert(!(extData.NEG & 0x4));
6093
6094 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6095 if (wf->execMask(lane)) {
6096 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
6097 }
6098 }
6099
6100 sdst.write();
6101 } // execute
6102 // --- Inst_VOP3__V_CMP_T_I32 class methods ---
6103
6104 Inst_VOP3__V_CMP_T_I32::Inst_VOP3__V_CMP_T_I32(InFmt_VOP3A *iFmt)
6105 : Inst_VOP3A(iFmt, "v_cmp_t_i32", true)
6106 {
6107 setFlag(ALU);
6108 } // Inst_VOP3__V_CMP_T_I32
6109
6110 Inst_VOP3__V_CMP_T_I32::~Inst_VOP3__V_CMP_T_I32()
6111 {
6112 } // ~Inst_VOP3__V_CMP_T_I32
6113
6114 // --- description from .arch file ---
6115 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
6116 void
6117 Inst_VOP3__V_CMP_T_I32::execute(GPUDynInstPtr gpuDynInst)
6118 {
6119 Wavefront *wf = gpuDynInst->wavefront();
6120 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6121
6122 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6123 if (wf->execMask(lane)) {
6124 sdst.setBit(lane, 1);
6125 }
6126 }
6127
6128 sdst.write();
6129 } // execute
6130 // --- Inst_VOP3__V_CMP_F_U32 class methods ---
6131
6132 Inst_VOP3__V_CMP_F_U32::Inst_VOP3__V_CMP_F_U32(InFmt_VOP3A *iFmt)
6133 : Inst_VOP3A(iFmt, "v_cmp_f_u32", true)
6134 {
6135 setFlag(ALU);
6136 } // Inst_VOP3__V_CMP_F_U32
6137
6138 Inst_VOP3__V_CMP_F_U32::~Inst_VOP3__V_CMP_F_U32()
6139 {
6140 } // ~Inst_VOP3__V_CMP_F_U32
6141
6142 // --- description from .arch file ---
6143 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
6144 void
6145 Inst_VOP3__V_CMP_F_U32::execute(GPUDynInstPtr gpuDynInst)
6146 {
6147 Wavefront *wf = gpuDynInst->wavefront();
6148 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6149
6150 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6151 if (wf->execMask(lane)) {
6152 sdst.setBit(lane, 0);
6153 }
6154 }
6155
6156 sdst.write();
6157 } // execute
6158 // --- Inst_VOP3__V_CMP_LT_U32 class methods ---
6159
6160 Inst_VOP3__V_CMP_LT_U32::Inst_VOP3__V_CMP_LT_U32(
6161 InFmt_VOP3A *iFmt)
6162 : Inst_VOP3A(iFmt, "v_cmp_lt_u32", true)
6163 {
6164 setFlag(ALU);
6165 } // Inst_VOP3__V_CMP_LT_U32
6166
6167 Inst_VOP3__V_CMP_LT_U32::~Inst_VOP3__V_CMP_LT_U32()
6168 {
6169 } // ~Inst_VOP3__V_CMP_LT_U32
6170
6171 // --- description from .arch file ---
6172 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
6173 void
6174 Inst_VOP3__V_CMP_LT_U32::execute(GPUDynInstPtr gpuDynInst)
6175 {
6176 Wavefront *wf = gpuDynInst->wavefront();
6177 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
6178 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
6179 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6180
6181 src0.readSrc();
6182 src1.readSrc();
6183
6187 assert(!(instData.ABS & 0x1));
6188 assert(!(instData.ABS & 0x2));
6189 assert(!(instData.ABS & 0x4));
6190 assert(!(extData.NEG & 0x1));
6191 assert(!(extData.NEG & 0x2));
6192 assert(!(extData.NEG & 0x4));
6193
6194 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6195 if (wf->execMask(lane)) {
6196 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
6197 }
6198 }
6199
6200 sdst.write();
6201 } // execute
6202 // --- Inst_VOP3__V_CMP_EQ_U32 class methods ---
6203
6204 Inst_VOP3__V_CMP_EQ_U32::Inst_VOP3__V_CMP_EQ_U32(
6205 InFmt_VOP3A *iFmt)
6206 : Inst_VOP3A(iFmt, "v_cmp_eq_u32", true)
6207 {
6208 setFlag(ALU);
6209 } // Inst_VOP3__V_CMP_EQ_U32
6210
6211 Inst_VOP3__V_CMP_EQ_U32::~Inst_VOP3__V_CMP_EQ_U32()
6212 {
6213 } // ~Inst_VOP3__V_CMP_EQ_U32
6214
6215 // --- description from .arch file ---
6216 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
6217 void
6218 Inst_VOP3__V_CMP_EQ_U32::execute(GPUDynInstPtr gpuDynInst)
6219 {
6220 Wavefront *wf = gpuDynInst->wavefront();
6221 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
6222 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
6223 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6224
6225 src0.readSrc();
6226 src1.readSrc();
6227
6231 assert(!(instData.ABS & 0x1));
6232 assert(!(instData.ABS & 0x2));
6233 assert(!(instData.ABS & 0x4));
6234 assert(!(extData.NEG & 0x1));
6235 assert(!(extData.NEG & 0x2));
6236 assert(!(extData.NEG & 0x4));
6237
6238 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6239 if (wf->execMask(lane)) {
6240 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
6241 }
6242 }
6243
6244 sdst.write();
6245 } // execute
6246 // --- Inst_VOP3__V_CMP_LE_U32 class methods ---
6247
6248 Inst_VOP3__V_CMP_LE_U32::Inst_VOP3__V_CMP_LE_U32(
6249 InFmt_VOP3A *iFmt)
6250 : Inst_VOP3A(iFmt, "v_cmp_le_u32", true)
6251 {
6252 setFlag(ALU);
6253 } // Inst_VOP3__V_CMP_LE_U32
6254
6255 Inst_VOP3__V_CMP_LE_U32::~Inst_VOP3__V_CMP_LE_U32()
6256 {
6257 } // ~Inst_VOP3__V_CMP_LE_U32
6258
6259 // --- description from .arch file ---
6260 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
6261 void
6262 Inst_VOP3__V_CMP_LE_U32::execute(GPUDynInstPtr gpuDynInst)
6263 {
6264 Wavefront *wf = gpuDynInst->wavefront();
6265 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
6266 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
6267 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6268
6269 src0.readSrc();
6270 src1.readSrc();
6271
6275 assert(!(instData.ABS & 0x1));
6276 assert(!(instData.ABS & 0x2));
6277 assert(!(instData.ABS & 0x4));
6278 assert(!(extData.NEG & 0x1));
6279 assert(!(extData.NEG & 0x2));
6280 assert(!(extData.NEG & 0x4));
6281
6282 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6283 if (wf->execMask(lane)) {
6284 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
6285 }
6286 }
6287
6288 sdst.write();
6289 } // execute
6290 // --- Inst_VOP3__V_CMP_GT_U32 class methods ---
6291
6292 Inst_VOP3__V_CMP_GT_U32::Inst_VOP3__V_CMP_GT_U32(
6293 InFmt_VOP3A *iFmt)
6294 : Inst_VOP3A(iFmt, "v_cmp_gt_u32", true)
6295 {
6296 setFlag(ALU);
6297 } // Inst_VOP3__V_CMP_GT_U32
6298
6299 Inst_VOP3__V_CMP_GT_U32::~Inst_VOP3__V_CMP_GT_U32()
6300 {
6301 } // ~Inst_VOP3__V_CMP_GT_U32
6302
6303 // --- description from .arch file ---
6304 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
6305 void
6306 Inst_VOP3__V_CMP_GT_U32::execute(GPUDynInstPtr gpuDynInst)
6307 {
6308 Wavefront *wf = gpuDynInst->wavefront();
6309 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
6310 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
6311 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6312
6313 src0.readSrc();
6314 src1.readSrc();
6315
6319 assert(!(instData.ABS & 0x1));
6320 assert(!(instData.ABS & 0x2));
6321 assert(!(instData.ABS & 0x4));
6322 assert(!(extData.NEG & 0x1));
6323 assert(!(extData.NEG & 0x2));
6324 assert(!(extData.NEG & 0x4));
6325
6326 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6327 if (wf->execMask(lane)) {
6328 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
6329 }
6330 }
6331
6332 sdst.write();
6333 } // execute
6334 // --- Inst_VOP3__V_CMP_NE_U32 class methods ---
6335
6336 Inst_VOP3__V_CMP_NE_U32::Inst_VOP3__V_CMP_NE_U32(
6337 InFmt_VOP3A *iFmt)
6338 : Inst_VOP3A(iFmt, "v_cmp_ne_u32", true)
6339 {
6340 setFlag(ALU);
6341 } // Inst_VOP3__V_CMP_NE_U32
6342
6343 Inst_VOP3__V_CMP_NE_U32::~Inst_VOP3__V_CMP_NE_U32()
6344 {
6345 } // ~Inst_VOP3__V_CMP_NE_U32
6346
6347 // --- description from .arch file ---
6348 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
6349 void
6350 Inst_VOP3__V_CMP_NE_U32::execute(GPUDynInstPtr gpuDynInst)
6351 {
6352 Wavefront *wf = gpuDynInst->wavefront();
6353 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
6354 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
6355 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6356
6357 src0.readSrc();
6358 src1.readSrc();
6359
6363 assert(!(instData.ABS & 0x1));
6364 assert(!(instData.ABS & 0x2));
6365 assert(!(instData.ABS & 0x4));
6366 assert(!(extData.NEG & 0x1));
6367 assert(!(extData.NEG & 0x2));
6368 assert(!(extData.NEG & 0x4));
6369
6370 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6371 if (wf->execMask(lane)) {
6372 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
6373 }
6374 }
6375
6376 sdst.write();
6377 } // execute
6378 // --- Inst_VOP3__V_CMP_GE_U32 class methods ---
6379
6380 Inst_VOP3__V_CMP_GE_U32::Inst_VOP3__V_CMP_GE_U32(
6381 InFmt_VOP3A *iFmt)
6382 : Inst_VOP3A(iFmt, "v_cmp_ge_u32", true)
6383 {
6384 setFlag(ALU);
6385 } // Inst_VOP3__V_CMP_GE_U32
6386
6387 Inst_VOP3__V_CMP_GE_U32::~Inst_VOP3__V_CMP_GE_U32()
6388 {
6389 } // ~Inst_VOP3__V_CMP_GE_U32
6390
6391 // --- description from .arch file ---
6392 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
6393 void
6394 Inst_VOP3__V_CMP_GE_U32::execute(GPUDynInstPtr gpuDynInst)
6395 {
6396 Wavefront *wf = gpuDynInst->wavefront();
6397 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
6398 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
6399 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6400
6401 src0.readSrc();
6402 src1.readSrc();
6403
6407 assert(!(instData.ABS & 0x1));
6408 assert(!(instData.ABS & 0x2));
6409 assert(!(instData.ABS & 0x4));
6410 assert(!(extData.NEG & 0x1));
6411 assert(!(extData.NEG & 0x2));
6412 assert(!(extData.NEG & 0x4));
6413
6414 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6415 if (wf->execMask(lane)) {
6416 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
6417 }
6418 }
6419
6420 sdst.write();
6421 } // execute
6422 // --- Inst_VOP3__V_CMP_T_U32 class methods ---
6423
6424 Inst_VOP3__V_CMP_T_U32::Inst_VOP3__V_CMP_T_U32(InFmt_VOP3A *iFmt)
6425 : Inst_VOP3A(iFmt, "v_cmp_t_u32", true)
6426 {
6427 setFlag(ALU);
6428 } // Inst_VOP3__V_CMP_T_U32
6429
6430 Inst_VOP3__V_CMP_T_U32::~Inst_VOP3__V_CMP_T_U32()
6431 {
6432 } // ~Inst_VOP3__V_CMP_T_U32
6433
6434 // --- description from .arch file ---
6435 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
6436 void
6437 Inst_VOP3__V_CMP_T_U32::execute(GPUDynInstPtr gpuDynInst)
6438 {
6439 Wavefront *wf = gpuDynInst->wavefront();
6440 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6441
6442 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6443 if (wf->execMask(lane)) {
6444 sdst.setBit(lane, 1);
6445 }
6446 }
6447
6448 sdst.write();
6449 } // execute
6450 // --- Inst_VOP3__V_CMPX_F_I32 class methods ---
6451
6452 Inst_VOP3__V_CMPX_F_I32::Inst_VOP3__V_CMPX_F_I32(
6453 InFmt_VOP3A *iFmt)
6454 : Inst_VOP3A(iFmt, "v_cmpx_f_i32", true)
6455 {
6456 setFlag(ALU);
6457 setFlag(WritesEXEC);
6458 } // Inst_VOP3__V_CMPX_F_I32
6459
6460 Inst_VOP3__V_CMPX_F_I32::~Inst_VOP3__V_CMPX_F_I32()
6461 {
6462 } // ~Inst_VOP3__V_CMPX_F_I32
6463
6464 // --- description from .arch file ---
6465 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
6466 void
6467 Inst_VOP3__V_CMPX_F_I32::execute(GPUDynInstPtr gpuDynInst)
6468 {
6469 Wavefront *wf = gpuDynInst->wavefront();
6470 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6471
6472 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6473 if (wf->execMask(lane)) {
6474 sdst.setBit(lane, 0);
6475 }
6476 }
6477
6478 wf->execMask() = sdst.rawData();
6479 sdst.write();
6480 } // execute
6481 // --- Inst_VOP3__V_CMPX_LT_I32 class methods ---
6482
6483 Inst_VOP3__V_CMPX_LT_I32::Inst_VOP3__V_CMPX_LT_I32(
6484 InFmt_VOP3A *iFmt)
6485 : Inst_VOP3A(iFmt, "v_cmpx_lt_i32", true)
6486 {
6487 setFlag(ALU);
6488 setFlag(WritesEXEC);
6489 } // Inst_VOP3__V_CMPX_LT_I32
6490
6491 Inst_VOP3__V_CMPX_LT_I32::~Inst_VOP3__V_CMPX_LT_I32()
6492 {
6493 } // ~Inst_VOP3__V_CMPX_LT_I32
6494
6495 // --- description from .arch file ---
6496 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
6497 void
6498 Inst_VOP3__V_CMPX_LT_I32::execute(GPUDynInstPtr gpuDynInst)
6499 {
6500 Wavefront *wf = gpuDynInst->wavefront();
6501 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
6502 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
6503 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6504
6505 src0.readSrc();
6506 src1.readSrc();
6507
6511 assert(!(instData.ABS & 0x1));
6512 assert(!(instData.ABS & 0x2));
6513 assert(!(instData.ABS & 0x4));
6514 assert(!(extData.NEG & 0x1));
6515 assert(!(extData.NEG & 0x2));
6516 assert(!(extData.NEG & 0x4));
6517
6518 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6519 if (wf->execMask(lane)) {
6520 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
6521 }
6522 }
6523
6524 wf->execMask() = sdst.rawData();
6525 sdst.write();
6526 } // execute
6527 // --- Inst_VOP3__V_CMPX_EQ_I32 class methods ---
6528
6529 Inst_VOP3__V_CMPX_EQ_I32::Inst_VOP3__V_CMPX_EQ_I32(
6530 InFmt_VOP3A *iFmt)
6531 : Inst_VOP3A(iFmt, "v_cmpx_eq_i32", true)
6532 {
6533 setFlag(ALU);
6534 setFlag(WritesEXEC);
6535 } // Inst_VOP3__V_CMPX_EQ_I32
6536
6537 Inst_VOP3__V_CMPX_EQ_I32::~Inst_VOP3__V_CMPX_EQ_I32()
6538 {
6539 } // ~Inst_VOP3__V_CMPX_EQ_I32
6540
6541 // --- description from .arch file ---
6542 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
6543 void
6544 Inst_VOP3__V_CMPX_EQ_I32::execute(GPUDynInstPtr gpuDynInst)
6545 {
6546 Wavefront *wf = gpuDynInst->wavefront();
6547 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
6548 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
6549 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6550
6551 src0.readSrc();
6552 src1.readSrc();
6553
6557 assert(!(instData.ABS & 0x1));
6558 assert(!(instData.ABS & 0x2));
6559 assert(!(instData.ABS & 0x4));
6560 assert(!(extData.NEG & 0x1));
6561 assert(!(extData.NEG & 0x2));
6562 assert(!(extData.NEG & 0x4));
6563
6564 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6565 if (wf->execMask(lane)) {
6566 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
6567 }
6568 }
6569
6570 wf->execMask() = sdst.rawData();
6571 sdst.write();
6572 } // execute
6573 // --- Inst_VOP3__V_CMPX_LE_I32 class methods ---
6574
6575 Inst_VOP3__V_CMPX_LE_I32::Inst_VOP3__V_CMPX_LE_I32(
6576 InFmt_VOP3A *iFmt)
6577 : Inst_VOP3A(iFmt, "v_cmpx_le_i32", true)
6578 {
6579 setFlag(ALU);
6580 setFlag(WritesEXEC);
6581 } // Inst_VOP3__V_CMPX_LE_I32
6582
6583 Inst_VOP3__V_CMPX_LE_I32::~Inst_VOP3__V_CMPX_LE_I32()
6584 {
6585 } // ~Inst_VOP3__V_CMPX_LE_I32
6586
6587 // --- description from .arch file ---
6588 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
6589 void
6590 Inst_VOP3__V_CMPX_LE_I32::execute(GPUDynInstPtr gpuDynInst)
6591 {
6592 Wavefront *wf = gpuDynInst->wavefront();
6593 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
6594 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
6595 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6596
6597 src0.readSrc();
6598 src1.readSrc();
6599
6603 assert(!(instData.ABS & 0x1));
6604 assert(!(instData.ABS & 0x2));
6605 assert(!(instData.ABS & 0x4));
6606 assert(!(extData.NEG & 0x1));
6607 assert(!(extData.NEG & 0x2));
6608 assert(!(extData.NEG & 0x4));
6609
6610 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6611 if (wf->execMask(lane)) {
6612 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
6613 }
6614 }
6615
6616 wf->execMask() = sdst.rawData();
6617 sdst.write();
6618 } // execute
6619 // --- Inst_VOP3__V_CMPX_GT_I32 class methods ---
6620
6621 Inst_VOP3__V_CMPX_GT_I32::Inst_VOP3__V_CMPX_GT_I32(
6622 InFmt_VOP3A *iFmt)
6623 : Inst_VOP3A(iFmt, "v_cmpx_gt_i32", true)
6624 {
6625 setFlag(ALU);
6626 setFlag(WritesEXEC);
6627 } // Inst_VOP3__V_CMPX_GT_I32
6628
6629 Inst_VOP3__V_CMPX_GT_I32::~Inst_VOP3__V_CMPX_GT_I32()
6630 {
6631 } // ~Inst_VOP3__V_CMPX_GT_I32
6632
6633 // --- description from .arch file ---
6634 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
6635 void
6636 Inst_VOP3__V_CMPX_GT_I32::execute(GPUDynInstPtr gpuDynInst)
6637 {
6638 Wavefront *wf = gpuDynInst->wavefront();
6639 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
6640 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
6641 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6642
6643 src0.readSrc();
6644 src1.readSrc();
6645
6649 assert(!(instData.ABS & 0x1));
6650 assert(!(instData.ABS & 0x2));
6651 assert(!(instData.ABS & 0x4));
6652 assert(!(extData.NEG & 0x1));
6653 assert(!(extData.NEG & 0x2));
6654 assert(!(extData.NEG & 0x4));
6655
6656 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6657 if (wf->execMask(lane)) {
6658 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
6659 }
6660 }
6661
6662 wf->execMask() = sdst.rawData();
6663 sdst.write();
6664 } // execute
6665 // --- Inst_VOP3__V_CMPX_NE_I32 class methods ---
6666
6667 Inst_VOP3__V_CMPX_NE_I32::Inst_VOP3__V_CMPX_NE_I32(
6668 InFmt_VOP3A *iFmt)
6669 : Inst_VOP3A(iFmt, "v_cmpx_ne_i32", true)
6670 {
6671 setFlag(ALU);
6672 setFlag(WritesEXEC);
6673 } // Inst_VOP3__V_CMPX_NE_I32
6674
6675 Inst_VOP3__V_CMPX_NE_I32::~Inst_VOP3__V_CMPX_NE_I32()
6676 {
6677 } // ~Inst_VOP3__V_CMPX_NE_I32
6678
6679 // --- description from .arch file ---
6680 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
6681 void
6682 Inst_VOP3__V_CMPX_NE_I32::execute(GPUDynInstPtr gpuDynInst)
6683 {
6684 Wavefront *wf = gpuDynInst->wavefront();
6685 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
6686 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
6687 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6688
6689 src0.readSrc();
6690 src1.readSrc();
6691
6695 assert(!(instData.ABS & 0x1));
6696 assert(!(instData.ABS & 0x2));
6697 assert(!(instData.ABS & 0x4));
6698 assert(!(extData.NEG & 0x1));
6699 assert(!(extData.NEG & 0x2));
6700 assert(!(extData.NEG & 0x4));
6701
6702 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6703 if (wf->execMask(lane)) {
6704 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
6705 }
6706 }
6707
6708 wf->execMask() = sdst.rawData();
6709 sdst.write();
6710 } // execute
6711 // --- Inst_VOP3__V_CMPX_GE_I32 class methods ---
6712
6713 Inst_VOP3__V_CMPX_GE_I32::Inst_VOP3__V_CMPX_GE_I32(
6714 InFmt_VOP3A *iFmt)
6715 : Inst_VOP3A(iFmt, "v_cmpx_ge_i32", true)
6716 {
6717 setFlag(ALU);
6718 setFlag(WritesEXEC);
6719 } // Inst_VOP3__V_CMPX_GE_I32
6720
6721 Inst_VOP3__V_CMPX_GE_I32::~Inst_VOP3__V_CMPX_GE_I32()
6722 {
6723 } // ~Inst_VOP3__V_CMPX_GE_I32
6724
6725 // --- description from .arch file ---
6726 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
6727 void
6728 Inst_VOP3__V_CMPX_GE_I32::execute(GPUDynInstPtr gpuDynInst)
6729 {
6730 Wavefront *wf = gpuDynInst->wavefront();
6731 ConstVecOperandI32 src0(gpuDynInst, extData.SRC0);
6732 ConstVecOperandI32 src1(gpuDynInst, extData.SRC1);
6733 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6734
6735 src0.readSrc();
6736 src1.readSrc();
6737
6741 assert(!(instData.ABS & 0x1));
6742 assert(!(instData.ABS & 0x2));
6743 assert(!(instData.ABS & 0x4));
6744 assert(!(extData.NEG & 0x1));
6745 assert(!(extData.NEG & 0x2));
6746 assert(!(extData.NEG & 0x4));
6747
6748 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6749 if (wf->execMask(lane)) {
6750 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
6751 }
6752 }
6753
6754 wf->execMask() = sdst.rawData();
6755 sdst.write();
6756 } // execute
6757 // --- Inst_VOP3__V_CMPX_T_I32 class methods ---
6758
6759 Inst_VOP3__V_CMPX_T_I32::Inst_VOP3__V_CMPX_T_I32(
6760 InFmt_VOP3A *iFmt)
6761 : Inst_VOP3A(iFmt, "v_cmpx_t_i32", true)
6762 {
6763 setFlag(ALU);
6764 setFlag(WritesEXEC);
6765 } // Inst_VOP3__V_CMPX_T_I32
6766
6767 Inst_VOP3__V_CMPX_T_I32::~Inst_VOP3__V_CMPX_T_I32()
6768 {
6769 } // ~Inst_VOP3__V_CMPX_T_I32
6770
6771 // --- description from .arch file ---
6772 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
6773 void
6774 Inst_VOP3__V_CMPX_T_I32::execute(GPUDynInstPtr gpuDynInst)
6775 {
6776 Wavefront *wf = gpuDynInst->wavefront();
6777 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6778
6779 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6780 if (wf->execMask(lane)) {
6781 sdst.setBit(lane, 1);
6782 }
6783 }
6784
6785 wf->execMask() = sdst.rawData();
6786 sdst.write();
6787 } // execute
6788 // --- Inst_VOP3__V_CMPX_F_U32 class methods ---
6789
6790 Inst_VOP3__V_CMPX_F_U32::Inst_VOP3__V_CMPX_F_U32(
6791 InFmt_VOP3A *iFmt)
6792 : Inst_VOP3A(iFmt, "v_cmpx_f_u32", true)
6793 {
6794 setFlag(ALU);
6795 setFlag(WritesEXEC);
6796 } // Inst_VOP3__V_CMPX_F_U32
6797
6798 Inst_VOP3__V_CMPX_F_U32::~Inst_VOP3__V_CMPX_F_U32()
6799 {
6800 } // ~Inst_VOP3__V_CMPX_F_U32
6801
6802 // --- description from .arch file ---
6803 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
6804 void
6805 Inst_VOP3__V_CMPX_F_U32::execute(GPUDynInstPtr gpuDynInst)
6806 {
6807 Wavefront *wf = gpuDynInst->wavefront();
6808 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6809
6810 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6811 if (wf->execMask(lane)) {
6812 sdst.setBit(lane, 0);
6813 }
6814 }
6815
6816 wf->execMask() = sdst.rawData();
6817 sdst.write();
6818 } // execute
6819 // --- Inst_VOP3__V_CMPX_LT_U32 class methods ---
6820
6821 Inst_VOP3__V_CMPX_LT_U32::Inst_VOP3__V_CMPX_LT_U32(
6822 InFmt_VOP3A *iFmt)
6823 : Inst_VOP3A(iFmt, "v_cmpx_lt_u32", true)
6824 {
6825 setFlag(ALU);
6826 setFlag(WritesEXEC);
6827 } // Inst_VOP3__V_CMPX_LT_U32
6828
6829 Inst_VOP3__V_CMPX_LT_U32::~Inst_VOP3__V_CMPX_LT_U32()
6830 {
6831 } // ~Inst_VOP3__V_CMPX_LT_U32
6832
6833 // --- description from .arch file ---
6834 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
6835 void
6836 Inst_VOP3__V_CMPX_LT_U32::execute(GPUDynInstPtr gpuDynInst)
6837 {
6838 Wavefront *wf = gpuDynInst->wavefront();
6839 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
6840 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
6841 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6842
6843 src0.readSrc();
6844 src1.readSrc();
6845
6849 assert(!(instData.ABS & 0x1));
6850 assert(!(instData.ABS & 0x2));
6851 assert(!(instData.ABS & 0x4));
6852 assert(!(extData.NEG & 0x1));
6853 assert(!(extData.NEG & 0x2));
6854 assert(!(extData.NEG & 0x4));
6855
6856 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6857 if (wf->execMask(lane)) {
6858 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
6859 }
6860 }
6861
6862 wf->execMask() = sdst.rawData();
6863 sdst.write();
6864 } // execute
6865 // --- Inst_VOP3__V_CMPX_EQ_U32 class methods ---
6866
6867 Inst_VOP3__V_CMPX_EQ_U32::Inst_VOP3__V_CMPX_EQ_U32(
6868 InFmt_VOP3A *iFmt)
6869 : Inst_VOP3A(iFmt, "v_cmpx_eq_u32", true)
6870 {
6871 setFlag(ALU);
6872 setFlag(WritesEXEC);
6873 } // Inst_VOP3__V_CMPX_EQ_U32
6874
6875 Inst_VOP3__V_CMPX_EQ_U32::~Inst_VOP3__V_CMPX_EQ_U32()
6876 {
6877 } // ~Inst_VOP3__V_CMPX_EQ_U32
6878
6879 // --- description from .arch file ---
6880 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
6881 void
6882 Inst_VOP3__V_CMPX_EQ_U32::execute(GPUDynInstPtr gpuDynInst)
6883 {
6884 Wavefront *wf = gpuDynInst->wavefront();
6885 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
6886 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
6887 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6888
6889 src0.readSrc();
6890 src1.readSrc();
6891
6895 assert(!(instData.ABS & 0x1));
6896 assert(!(instData.ABS & 0x2));
6897 assert(!(instData.ABS & 0x4));
6898 assert(!(extData.NEG & 0x1));
6899 assert(!(extData.NEG & 0x2));
6900 assert(!(extData.NEG & 0x4));
6901
6902 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6903 if (wf->execMask(lane)) {
6904 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
6905 }
6906 }
6907
6908 wf->execMask() = sdst.rawData();
6909 sdst.write();
6910 } // execute
6911 // --- Inst_VOP3__V_CMPX_LE_U32 class methods ---
6912
6913 Inst_VOP3__V_CMPX_LE_U32::Inst_VOP3__V_CMPX_LE_U32(
6914 InFmt_VOP3A *iFmt)
6915 : Inst_VOP3A(iFmt, "v_cmpx_le_u32", true)
6916 {
6917 setFlag(ALU);
6918 setFlag(WritesEXEC);
6919 } // Inst_VOP3__V_CMPX_LE_U32
6920
6921 Inst_VOP3__V_CMPX_LE_U32::~Inst_VOP3__V_CMPX_LE_U32()
6922 {
6923 } // ~Inst_VOP3__V_CMPX_LE_U32
6924
6925 // --- description from .arch file ---
6926 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
6927 void
6928 Inst_VOP3__V_CMPX_LE_U32::execute(GPUDynInstPtr gpuDynInst)
6929 {
6930 Wavefront *wf = gpuDynInst->wavefront();
6931 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
6932 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
6933 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6934
6935 src0.readSrc();
6936 src1.readSrc();
6937
6941 assert(!(instData.ABS & 0x1));
6942 assert(!(instData.ABS & 0x2));
6943 assert(!(instData.ABS & 0x4));
6944 assert(!(extData.NEG & 0x1));
6945 assert(!(extData.NEG & 0x2));
6946 assert(!(extData.NEG & 0x4));
6947
6948 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6949 if (wf->execMask(lane)) {
6950 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
6951 }
6952 }
6953
6954 wf->execMask() = sdst.rawData();
6955 sdst.write();
6956 } // execute
6957 // --- Inst_VOP3__V_CMPX_GT_U32 class methods ---
6958
6959 Inst_VOP3__V_CMPX_GT_U32::Inst_VOP3__V_CMPX_GT_U32(
6960 InFmt_VOP3A *iFmt)
6961 : Inst_VOP3A(iFmt, "v_cmpx_gt_u32", true)
6962 {
6963 setFlag(ALU);
6964 setFlag(WritesEXEC);
6965 } // Inst_VOP3__V_CMPX_GT_U32
6966
6967 Inst_VOP3__V_CMPX_GT_U32::~Inst_VOP3__V_CMPX_GT_U32()
6968 {
6969 } // ~Inst_VOP3__V_CMPX_GT_U32
6970
6971 // --- description from .arch file ---
6972 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
6973 void
6974 Inst_VOP3__V_CMPX_GT_U32::execute(GPUDynInstPtr gpuDynInst)
6975 {
6976 Wavefront *wf = gpuDynInst->wavefront();
6977 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
6978 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
6979 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
6980
6981 src0.readSrc();
6982 src1.readSrc();
6983
6987 assert(!(instData.ABS & 0x1));
6988 assert(!(instData.ABS & 0x2));
6989 assert(!(instData.ABS & 0x4));
6990 assert(!(extData.NEG & 0x1));
6991 assert(!(extData.NEG & 0x2));
6992 assert(!(extData.NEG & 0x4));
6993
6994 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
6995 if (wf->execMask(lane)) {
6996 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
6997 }
6998 }
6999
7000 wf->execMask() = sdst.rawData();
7001 sdst.write();
7002 } // execute
7003 // --- Inst_VOP3__V_CMPX_NE_U32 class methods ---
7004
7005 Inst_VOP3__V_CMPX_NE_U32::Inst_VOP3__V_CMPX_NE_U32(
7006 InFmt_VOP3A *iFmt)
7007 : Inst_VOP3A(iFmt, "v_cmpx_ne_u32", true)
7008 {
7009 setFlag(ALU);
7010 setFlag(WritesEXEC);
7011 } // Inst_VOP3__V_CMPX_NE_U32
7012
7013 Inst_VOP3__V_CMPX_NE_U32::~Inst_VOP3__V_CMPX_NE_U32()
7014 {
7015 } // ~Inst_VOP3__V_CMPX_NE_U32
7016
7017 // --- description from .arch file ---
7018 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
7019 void
7020 Inst_VOP3__V_CMPX_NE_U32::execute(GPUDynInstPtr gpuDynInst)
7021 {
7022 Wavefront *wf = gpuDynInst->wavefront();
7023 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
7024 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
7025 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7026
7027 src0.readSrc();
7028 src1.readSrc();
7029
7033 assert(!(instData.ABS & 0x1));
7034 assert(!(instData.ABS & 0x2));
7035 assert(!(instData.ABS & 0x4));
7036 assert(!(extData.NEG & 0x1));
7037 assert(!(extData.NEG & 0x2));
7038 assert(!(extData.NEG & 0x4));
7039
7040 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7041 if (wf->execMask(lane)) {
7042 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
7043 }
7044 }
7045
7046 wf->execMask() = sdst.rawData();
7047 sdst.write();
7048 } // execute
7049 // --- Inst_VOP3__V_CMPX_GE_U32 class methods ---
7050
7051 Inst_VOP3__V_CMPX_GE_U32::Inst_VOP3__V_CMPX_GE_U32(
7052 InFmt_VOP3A *iFmt)
7053 : Inst_VOP3A(iFmt, "v_cmpx_ge_u32", true)
7054 {
7055 setFlag(ALU);
7056 setFlag(WritesEXEC);
7057 } // Inst_VOP3__V_CMPX_GE_U32
7058
7059 Inst_VOP3__V_CMPX_GE_U32::~Inst_VOP3__V_CMPX_GE_U32()
7060 {
7061 } // ~Inst_VOP3__V_CMPX_GE_U32
7062
7063 // --- description from .arch file ---
7064 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
7065 void
7066 Inst_VOP3__V_CMPX_GE_U32::execute(GPUDynInstPtr gpuDynInst)
7067 {
7068 Wavefront *wf = gpuDynInst->wavefront();
7069 ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
7070 ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
7071 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7072
7073 src0.readSrc();
7074 src1.readSrc();
7075
7079 assert(!(instData.ABS & 0x1));
7080 assert(!(instData.ABS & 0x2));
7081 assert(!(instData.ABS & 0x4));
7082 assert(!(extData.NEG & 0x1));
7083 assert(!(extData.NEG & 0x2));
7084 assert(!(extData.NEG & 0x4));
7085
7086 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7087 if (wf->execMask(lane)) {
7088 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
7089 }
7090 }
7091
7092 wf->execMask() = sdst.rawData();
7093 sdst.write();
7094 } // execute
7095 // --- Inst_VOP3__V_CMPX_T_U32 class methods ---
7096
7097 Inst_VOP3__V_CMPX_T_U32::Inst_VOP3__V_CMPX_T_U32(
7098 InFmt_VOP3A *iFmt)
7099 : Inst_VOP3A(iFmt, "v_cmpx_t_u32", true)
7100 {
7101 setFlag(ALU);
7102 setFlag(WritesEXEC);
7103 } // Inst_VOP3__V_CMPX_T_U32
7104
7105 Inst_VOP3__V_CMPX_T_U32::~Inst_VOP3__V_CMPX_T_U32()
7106 {
7107 } // ~Inst_VOP3__V_CMPX_T_U32
7108
7109 // --- description from .arch file ---
7110 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
7111 void
7112 Inst_VOP3__V_CMPX_T_U32::execute(GPUDynInstPtr gpuDynInst)
7113 {
7114 Wavefront *wf = gpuDynInst->wavefront();
7115 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7116
7117 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7118 if (wf->execMask(lane)) {
7119 sdst.setBit(lane, 1);
7120 }
7121 }
7122
7123 wf->execMask() = sdst.rawData();
7124 sdst.write();
7125 } // execute
7126 // --- Inst_VOP3__V_CMP_F_I64 class methods ---
7127
7128 Inst_VOP3__V_CMP_F_I64::Inst_VOP3__V_CMP_F_I64(InFmt_VOP3A *iFmt)
7129 : Inst_VOP3A(iFmt, "v_cmp_f_i64", true)
7130 {
7131 setFlag(ALU);
7132 } // Inst_VOP3__V_CMP_F_I64
7133
7134 Inst_VOP3__V_CMP_F_I64::~Inst_VOP3__V_CMP_F_I64()
7135 {
7136 } // ~Inst_VOP3__V_CMP_F_I64
7137
7138 // --- description from .arch file ---
7139 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
7140 void
7141 Inst_VOP3__V_CMP_F_I64::execute(GPUDynInstPtr gpuDynInst)
7142 {
7143 Wavefront *wf = gpuDynInst->wavefront();
7144 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7145
7146 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7147 if (wf->execMask(lane)) {
7148 sdst.setBit(lane, 0);
7149 }
7150 }
7151
7152 sdst.write();
7153 } // execute
7154 // --- Inst_VOP3__V_CMP_LT_I64 class methods ---
7155
7156 Inst_VOP3__V_CMP_LT_I64::Inst_VOP3__V_CMP_LT_I64(
7157 InFmt_VOP3A *iFmt)
7158 : Inst_VOP3A(iFmt, "v_cmp_lt_i64", true)
7159 {
7160 setFlag(ALU);
7161 } // Inst_VOP3__V_CMP_LT_I64
7162
7163 Inst_VOP3__V_CMP_LT_I64::~Inst_VOP3__V_CMP_LT_I64()
7164 {
7165 } // ~Inst_VOP3__V_CMP_LT_I64
7166
7167 // --- description from .arch file ---
7168 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
7169 void
7170 Inst_VOP3__V_CMP_LT_I64::execute(GPUDynInstPtr gpuDynInst)
7171 {
7172 Wavefront *wf = gpuDynInst->wavefront();
7173 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
7174 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
7175 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7176
7177 src0.readSrc();
7178 src1.readSrc();
7179
7183 assert(!(instData.ABS & 0x1));
7184 assert(!(instData.ABS & 0x2));
7185 assert(!(instData.ABS & 0x4));
7186 assert(!(extData.NEG & 0x1));
7187 assert(!(extData.NEG & 0x2));
7188 assert(!(extData.NEG & 0x4));
7189
7190 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7191 if (wf->execMask(lane)) {
7192 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
7193 }
7194 }
7195
7196 sdst.write();
7197 } // execute
7198 // --- Inst_VOP3__V_CMP_EQ_I64 class methods ---
7199
7200 Inst_VOP3__V_CMP_EQ_I64::Inst_VOP3__V_CMP_EQ_I64(
7201 InFmt_VOP3A *iFmt)
7202 : Inst_VOP3A(iFmt, "v_cmp_eq_i64", true)
7203 {
7204 setFlag(ALU);
7205 } // Inst_VOP3__V_CMP_EQ_I64
7206
7207 Inst_VOP3__V_CMP_EQ_I64::~Inst_VOP3__V_CMP_EQ_I64()
7208 {
7209 } // ~Inst_VOP3__V_CMP_EQ_I64
7210
7211 // --- description from .arch file ---
7212 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
7213 void
7214 Inst_VOP3__V_CMP_EQ_I64::execute(GPUDynInstPtr gpuDynInst)
7215 {
7216 Wavefront *wf = gpuDynInst->wavefront();
7217 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
7218 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
7219 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7220
7221 src0.readSrc();
7222 src1.readSrc();
7223
7227 assert(!(instData.ABS & 0x1));
7228 assert(!(instData.ABS & 0x2));
7229 assert(!(instData.ABS & 0x4));
7230 assert(!(extData.NEG & 0x1));
7231 assert(!(extData.NEG & 0x2));
7232 assert(!(extData.NEG & 0x4));
7233
7234 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7235 if (wf->execMask(lane)) {
7236 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
7237 }
7238 }
7239
7240 sdst.write();
7241 } // execute
7242 // --- Inst_VOP3__V_CMP_LE_I64 class methods ---
7243
7244 Inst_VOP3__V_CMP_LE_I64::Inst_VOP3__V_CMP_LE_I64(
7245 InFmt_VOP3A *iFmt)
7246 : Inst_VOP3A(iFmt, "v_cmp_le_i64", true)
7247 {
7248 setFlag(ALU);
7249 } // Inst_VOP3__V_CMP_LE_I64
7250
7251 Inst_VOP3__V_CMP_LE_I64::~Inst_VOP3__V_CMP_LE_I64()
7252 {
7253 } // ~Inst_VOP3__V_CMP_LE_I64
7254
7255 // --- description from .arch file ---
7256 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
7257 void
7258 Inst_VOP3__V_CMP_LE_I64::execute(GPUDynInstPtr gpuDynInst)
7259 {
7260 Wavefront *wf = gpuDynInst->wavefront();
7261 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
7262 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
7263 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7264
7265 src0.readSrc();
7266 src1.readSrc();
7267
7271 assert(!(instData.ABS & 0x1));
7272 assert(!(instData.ABS & 0x2));
7273 assert(!(instData.ABS & 0x4));
7274 assert(!(extData.NEG & 0x1));
7275 assert(!(extData.NEG & 0x2));
7276 assert(!(extData.NEG & 0x4));
7277
7278 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7279 if (wf->execMask(lane)) {
7280 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
7281 }
7282 }
7283
7284 sdst.write();
7285 } // execute
7286 // --- Inst_VOP3__V_CMP_GT_I64 class methods ---
7287
7288 Inst_VOP3__V_CMP_GT_I64::Inst_VOP3__V_CMP_GT_I64(
7289 InFmt_VOP3A *iFmt)
7290 : Inst_VOP3A(iFmt, "v_cmp_gt_i64", true)
7291 {
7292 setFlag(ALU);
7293 } // Inst_VOP3__V_CMP_GT_I64
7294
7295 Inst_VOP3__V_CMP_GT_I64::~Inst_VOP3__V_CMP_GT_I64()
7296 {
7297 } // ~Inst_VOP3__V_CMP_GT_I64
7298
7299 // --- description from .arch file ---
7300 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
7301 void
7302 Inst_VOP3__V_CMP_GT_I64::execute(GPUDynInstPtr gpuDynInst)
7303 {
7304 Wavefront *wf = gpuDynInst->wavefront();
7305 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
7306 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
7307 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7308
7309 src0.readSrc();
7310 src1.readSrc();
7311
7315 assert(!(instData.ABS & 0x1));
7316 assert(!(instData.ABS & 0x2));
7317 assert(!(instData.ABS & 0x4));
7318 assert(!(extData.NEG & 0x1));
7319 assert(!(extData.NEG & 0x2));
7320 assert(!(extData.NEG & 0x4));
7321
7322 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7323 if (wf->execMask(lane)) {
7324 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
7325 }
7326 }
7327
7328 sdst.write();
7329 } // execute
7330 // --- Inst_VOP3__V_CMP_NE_I64 class methods ---
7331
7332 Inst_VOP3__V_CMP_NE_I64::Inst_VOP3__V_CMP_NE_I64(
7333 InFmt_VOP3A *iFmt)
7334 : Inst_VOP3A(iFmt, "v_cmp_ne_i64", true)
7335 {
7336 setFlag(ALU);
7337 } // Inst_VOP3__V_CMP_NE_I64
7338
7339 Inst_VOP3__V_CMP_NE_I64::~Inst_VOP3__V_CMP_NE_I64()
7340 {
7341 } // ~Inst_VOP3__V_CMP_NE_I64
7342
7343 // --- description from .arch file ---
7344 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
7345 void
7346 Inst_VOP3__V_CMP_NE_I64::execute(GPUDynInstPtr gpuDynInst)
7347 {
7348 Wavefront *wf = gpuDynInst->wavefront();
7349 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
7350 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
7351 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7352
7353 src0.readSrc();
7354 src1.readSrc();
7355
7359 assert(!(instData.ABS & 0x1));
7360 assert(!(instData.ABS & 0x2));
7361 assert(!(instData.ABS & 0x4));
7362 assert(!(extData.NEG & 0x1));
7363 assert(!(extData.NEG & 0x2));
7364 assert(!(extData.NEG & 0x4));
7365
7366 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7367 if (wf->execMask(lane)) {
7368 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
7369 }
7370 }
7371
7372 sdst.write();
7373 } // execute
7374 // --- Inst_VOP3__V_CMP_GE_I64 class methods ---
7375
7376 Inst_VOP3__V_CMP_GE_I64::Inst_VOP3__V_CMP_GE_I64(
7377 InFmt_VOP3A *iFmt)
7378 : Inst_VOP3A(iFmt, "v_cmp_ge_i64", true)
7379 {
7380 setFlag(ALU);
7381 } // Inst_VOP3__V_CMP_GE_I64
7382
7383 Inst_VOP3__V_CMP_GE_I64::~Inst_VOP3__V_CMP_GE_I64()
7384 {
7385 } // ~Inst_VOP3__V_CMP_GE_I64
7386
7387 // --- description from .arch file ---
7388 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
7389 void
7390 Inst_VOP3__V_CMP_GE_I64::execute(GPUDynInstPtr gpuDynInst)
7391 {
7392 Wavefront *wf = gpuDynInst->wavefront();
7393 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
7394 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
7395 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7396
7397 src0.readSrc();
7398 src1.readSrc();
7399
7403 assert(!(instData.ABS & 0x1));
7404 assert(!(instData.ABS & 0x2));
7405 assert(!(instData.ABS & 0x4));
7406 assert(!(extData.NEG & 0x1));
7407 assert(!(extData.NEG & 0x2));
7408 assert(!(extData.NEG & 0x4));
7409
7410 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7411 if (wf->execMask(lane)) {
7412 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
7413 }
7414 }
7415
7416 sdst.write();
7417 } // execute
7418 // --- Inst_VOP3__V_CMP_T_I64 class methods ---
7419
7420 Inst_VOP3__V_CMP_T_I64::Inst_VOP3__V_CMP_T_I64(InFmt_VOP3A *iFmt)
7421 : Inst_VOP3A(iFmt, "v_cmp_t_i64", true)
7422 {
7423 setFlag(ALU);
7424 } // Inst_VOP3__V_CMP_T_I64
7425
7426 Inst_VOP3__V_CMP_T_I64::~Inst_VOP3__V_CMP_T_I64()
7427 {
7428 } // ~Inst_VOP3__V_CMP_T_I64
7429
7430 // --- description from .arch file ---
7431 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
7432 void
7433 Inst_VOP3__V_CMP_T_I64::execute(GPUDynInstPtr gpuDynInst)
7434 {
7435 Wavefront *wf = gpuDynInst->wavefront();
7436 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7437
7438 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7439 if (wf->execMask(lane)) {
7440 sdst.setBit(lane, 1);
7441 }
7442 }
7443
7444 sdst.write();
7445 } // execute
7446 // --- Inst_VOP3__V_CMP_F_U64 class methods ---
7447
7448 Inst_VOP3__V_CMP_F_U64::Inst_VOP3__V_CMP_F_U64(InFmt_VOP3A *iFmt)
7449 : Inst_VOP3A(iFmt, "v_cmp_f_u64", true)
7450 {
7451 setFlag(ALU);
7452 } // Inst_VOP3__V_CMP_F_U64
7453
7454 Inst_VOP3__V_CMP_F_U64::~Inst_VOP3__V_CMP_F_U64()
7455 {
7456 } // ~Inst_VOP3__V_CMP_F_U64
7457
7458 // --- description from .arch file ---
7459 // D.u64[threadID] = 0; D = VCC in VOPC encoding.
7460 void
7461 Inst_VOP3__V_CMP_F_U64::execute(GPUDynInstPtr gpuDynInst)
7462 {
7463 Wavefront *wf = gpuDynInst->wavefront();
7464 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7465
7466 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7467 if (wf->execMask(lane)) {
7468 sdst.setBit(lane, 0);
7469 }
7470 }
7471
7472 sdst.write();
7473 } // execute
7474 // --- Inst_VOP3__V_CMP_LT_U64 class methods ---
7475
7476 Inst_VOP3__V_CMP_LT_U64::Inst_VOP3__V_CMP_LT_U64(
7477 InFmt_VOP3A *iFmt)
7478 : Inst_VOP3A(iFmt, "v_cmp_lt_u64", true)
7479 {
7480 setFlag(ALU);
7481 } // Inst_VOP3__V_CMP_LT_U64
7482
7483 Inst_VOP3__V_CMP_LT_U64::~Inst_VOP3__V_CMP_LT_U64()
7484 {
7485 } // ~Inst_VOP3__V_CMP_LT_U64
7486
7487 // --- description from .arch file ---
7488 // D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
7489 void
7490 Inst_VOP3__V_CMP_LT_U64::execute(GPUDynInstPtr gpuDynInst)
7491 {
7492 Wavefront *wf = gpuDynInst->wavefront();
7493 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
7494 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
7495 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7496
7497 src0.readSrc();
7498 src1.readSrc();
7499
7503 assert(!(instData.ABS & 0x1));
7504 assert(!(instData.ABS & 0x2));
7505 assert(!(instData.ABS & 0x4));
7506 assert(!(extData.NEG & 0x1));
7507 assert(!(extData.NEG & 0x2));
7508 assert(!(extData.NEG & 0x4));
7509
7510 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7511 if (wf->execMask(lane)) {
7512 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
7513 }
7514 }
7515
7516 sdst.write();
7517 } // execute
7518 // --- Inst_VOP3__V_CMP_EQ_U64 class methods ---
7519
7520 Inst_VOP3__V_CMP_EQ_U64::Inst_VOP3__V_CMP_EQ_U64(
7521 InFmt_VOP3A *iFmt)
7522 : Inst_VOP3A(iFmt, "v_cmp_eq_u64", true)
7523 {
7524 setFlag(ALU);
7525 } // Inst_VOP3__V_CMP_EQ_U64
7526
7527 Inst_VOP3__V_CMP_EQ_U64::~Inst_VOP3__V_CMP_EQ_U64()
7528 {
7529 } // ~Inst_VOP3__V_CMP_EQ_U64
7530
7531 // --- description from .arch file ---
7532 // D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
7533 void
7534 Inst_VOP3__V_CMP_EQ_U64::execute(GPUDynInstPtr gpuDynInst)
7535 {
7536 Wavefront *wf = gpuDynInst->wavefront();
7537 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
7538 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
7539 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7540
7541 src0.readSrc();
7542 src1.readSrc();
7543
7547 assert(!(instData.ABS & 0x1));
7548 assert(!(instData.ABS & 0x2));
7549 assert(!(instData.ABS & 0x4));
7550 assert(!(extData.NEG & 0x1));
7551 assert(!(extData.NEG & 0x2));
7552 assert(!(extData.NEG & 0x4));
7553
7554 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7555 if (wf->execMask(lane)) {
7556 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
7557 }
7558 }
7559
7560 sdst.write();
7561 } // execute
7562 // --- Inst_VOP3__V_CMP_LE_U64 class methods ---
7563
7564 Inst_VOP3__V_CMP_LE_U64::Inst_VOP3__V_CMP_LE_U64(
7565 InFmt_VOP3A *iFmt)
7566 : Inst_VOP3A(iFmt, "v_cmp_le_u64", true)
7567 {
7568 setFlag(ALU);
7569 } // Inst_VOP3__V_CMP_LE_U64
7570
7571 Inst_VOP3__V_CMP_LE_U64::~Inst_VOP3__V_CMP_LE_U64()
7572 {
7573 } // ~Inst_VOP3__V_CMP_LE_U64
7574
7575 // --- description from .arch file ---
7576 // D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
7577 void
7578 Inst_VOP3__V_CMP_LE_U64::execute(GPUDynInstPtr gpuDynInst)
7579 {
7580 Wavefront *wf = gpuDynInst->wavefront();
7581 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
7582 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
7583 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7584
7585 src0.readSrc();
7586 src1.readSrc();
7587
7591 assert(!(instData.ABS & 0x1));
7592 assert(!(instData.ABS & 0x2));
7593 assert(!(instData.ABS & 0x4));
7594 assert(!(extData.NEG & 0x1));
7595 assert(!(extData.NEG & 0x2));
7596 assert(!(extData.NEG & 0x4));
7597
7598 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7599 if (wf->execMask(lane)) {
7600 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
7601 }
7602 }
7603
7604 sdst.write();
7605 } // execute
7606 // --- Inst_VOP3__V_CMP_GT_U64 class methods ---
7607
7608 Inst_VOP3__V_CMP_GT_U64::Inst_VOP3__V_CMP_GT_U64(
7609 InFmt_VOP3A *iFmt)
7610 : Inst_VOP3A(iFmt, "v_cmp_gt_u64", true)
7611 {
7612 setFlag(ALU);
7613 } // Inst_VOP3__V_CMP_GT_U64
7614
7615 Inst_VOP3__V_CMP_GT_U64::~Inst_VOP3__V_CMP_GT_U64()
7616 {
7617 } // ~Inst_VOP3__V_CMP_GT_U64
7618
7619 // --- description from .arch file ---
7620 // D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
7621 void
7622 Inst_VOP3__V_CMP_GT_U64::execute(GPUDynInstPtr gpuDynInst)
7623 {
7624 Wavefront *wf = gpuDynInst->wavefront();
7625 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
7626 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
7627 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7628
7629 src0.readSrc();
7630 src1.readSrc();
7631
7635 assert(!(instData.ABS & 0x1));
7636 assert(!(instData.ABS & 0x2));
7637 assert(!(instData.ABS & 0x4));
7638 assert(!(extData.NEG & 0x1));
7639 assert(!(extData.NEG & 0x2));
7640 assert(!(extData.NEG & 0x4));
7641
7642 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7643 if (wf->execMask(lane)) {
7644 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
7645 }
7646 }
7647
7648 sdst.write();
7649 } // execute
7650 // --- Inst_VOP3__V_CMP_NE_U64 class methods ---
7651
7652 Inst_VOP3__V_CMP_NE_U64::Inst_VOP3__V_CMP_NE_U64(
7653 InFmt_VOP3A *iFmt)
7654 : Inst_VOP3A(iFmt, "v_cmp_ne_u64", true)
7655 {
7656 setFlag(ALU);
7657 } // Inst_VOP3__V_CMP_NE_U64
7658
7659 Inst_VOP3__V_CMP_NE_U64::~Inst_VOP3__V_CMP_NE_U64()
7660 {
7661 } // ~Inst_VOP3__V_CMP_NE_U64
7662
7663 // --- description from .arch file ---
7664 // D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
7665 void
7666 Inst_VOP3__V_CMP_NE_U64::execute(GPUDynInstPtr gpuDynInst)
7667 {
7668 Wavefront *wf = gpuDynInst->wavefront();
7669 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
7670 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
7671 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7672
7673 src0.readSrc();
7674 src1.readSrc();
7675
7679 assert(!(instData.ABS & 0x1));
7680 assert(!(instData.ABS & 0x2));
7681 assert(!(instData.ABS & 0x4));
7682 assert(!(extData.NEG & 0x1));
7683 assert(!(extData.NEG & 0x2));
7684 assert(!(extData.NEG & 0x4));
7685
7686 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7687 if (wf->execMask(lane)) {
7688 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
7689 }
7690 }
7691
7692 sdst.write();
7693 } // execute
7694 // --- Inst_VOP3__V_CMP_GE_U64 class methods ---
7695
7696 Inst_VOP3__V_CMP_GE_U64::Inst_VOP3__V_CMP_GE_U64(
7697 InFmt_VOP3A *iFmt)
7698 : Inst_VOP3A(iFmt, "v_cmp_ge_u64", true)
7699 {
7700 setFlag(ALU);
7701 } // Inst_VOP3__V_CMP_GE_U64
7702
7703 Inst_VOP3__V_CMP_GE_U64::~Inst_VOP3__V_CMP_GE_U64()
7704 {
7705 } // ~Inst_VOP3__V_CMP_GE_U64
7706
7707 // --- description from .arch file ---
7708 // D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
7709 void
7710 Inst_VOP3__V_CMP_GE_U64::execute(GPUDynInstPtr gpuDynInst)
7711 {
7712 Wavefront *wf = gpuDynInst->wavefront();
7713 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
7714 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
7715 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7716
7717 src0.readSrc();
7718 src1.readSrc();
7719
7723 assert(!(instData.ABS & 0x1));
7724 assert(!(instData.ABS & 0x2));
7725 assert(!(instData.ABS & 0x4));
7726 assert(!(extData.NEG & 0x1));
7727 assert(!(extData.NEG & 0x2));
7728 assert(!(extData.NEG & 0x4));
7729
7730 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7731 if (wf->execMask(lane)) {
7732 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
7733 }
7734 }
7735
7736 sdst.write();
7737 } // execute
7738 // --- Inst_VOP3__V_CMP_T_U64 class methods ---
7739
7740 Inst_VOP3__V_CMP_T_U64::Inst_VOP3__V_CMP_T_U64(InFmt_VOP3A *iFmt)
7741 : Inst_VOP3A(iFmt, "v_cmp_t_u64", true)
7742 {
7743 setFlag(ALU);
7744 } // Inst_VOP3__V_CMP_T_U64
7745
7746 Inst_VOP3__V_CMP_T_U64::~Inst_VOP3__V_CMP_T_U64()
7747 {
7748 } // ~Inst_VOP3__V_CMP_T_U64
7749
7750 // --- description from .arch file ---
7751 // D.u64[threadID] = 1; D = VCC in VOPC encoding.
7752 void
7753 Inst_VOP3__V_CMP_T_U64::execute(GPUDynInstPtr gpuDynInst)
7754 {
7755 Wavefront *wf = gpuDynInst->wavefront();
7756 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7757
7758 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7759 if (wf->execMask(lane)) {
7760 sdst.setBit(lane, 1);
7761 }
7762 }
7763
7764 sdst.write();
7765 } // execute
7766 // --- Inst_VOP3__V_CMPX_F_I64 class methods ---
7767
7768 Inst_VOP3__V_CMPX_F_I64::Inst_VOP3__V_CMPX_F_I64(
7769 InFmt_VOP3A *iFmt)
7770 : Inst_VOP3A(iFmt, "v_cmpx_f_i64", true)
7771 {
7772 setFlag(ALU);
7773 setFlag(WritesEXEC);
7774 } // Inst_VOP3__V_CMPX_F_I64
7775
7776 Inst_VOP3__V_CMPX_F_I64::~Inst_VOP3__V_CMPX_F_I64()
7777 {
7778 } // ~Inst_VOP3__V_CMPX_F_I64
7779
7780 // --- description from .arch file ---
7781 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
7782 void
7783 Inst_VOP3__V_CMPX_F_I64::execute(GPUDynInstPtr gpuDynInst)
7784 {
7785 Wavefront *wf = gpuDynInst->wavefront();
7786 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7787
7788 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7789 if (wf->execMask(lane)) {
7790 sdst.setBit(lane, 0);
7791 }
7792 }
7793
7794 wf->execMask() = sdst.rawData();
7795 sdst.write();
7796 } // execute
7797 // --- Inst_VOP3__V_CMPX_LT_I64 class methods ---
7798
7799 Inst_VOP3__V_CMPX_LT_I64::Inst_VOP3__V_CMPX_LT_I64(
7800 InFmt_VOP3A *iFmt)
7801 : Inst_VOP3A(iFmt, "v_cmpx_lt_i64", true)
7802 {
7803 setFlag(ALU);
7804 setFlag(WritesEXEC);
7805 } // Inst_VOP3__V_CMPX_LT_I64
7806
7807 Inst_VOP3__V_CMPX_LT_I64::~Inst_VOP3__V_CMPX_LT_I64()
7808 {
7809 } // ~Inst_VOP3__V_CMPX_LT_I64
7810
7811 // --- description from .arch file ---
7812 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
7813 void
7814 Inst_VOP3__V_CMPX_LT_I64::execute(GPUDynInstPtr gpuDynInst)
7815 {
7816 Wavefront *wf = gpuDynInst->wavefront();
7817 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
7818 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
7819 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7820
7821 src0.readSrc();
7822 src1.readSrc();
7823
7827 assert(!(instData.ABS & 0x1));
7828 assert(!(instData.ABS & 0x2));
7829 assert(!(instData.ABS & 0x4));
7830 assert(!(extData.NEG & 0x1));
7831 assert(!(extData.NEG & 0x2));
7832 assert(!(extData.NEG & 0x4));
7833
7834 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7835 if (wf->execMask(lane)) {
7836 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
7837 }
7838 }
7839
7840 wf->execMask() = sdst.rawData();
7841 sdst.write();
7842 } // execute
7843 // --- Inst_VOP3__V_CMPX_EQ_I64 class methods ---
7844
7845 Inst_VOP3__V_CMPX_EQ_I64::Inst_VOP3__V_CMPX_EQ_I64(
7846 InFmt_VOP3A *iFmt)
7847 : Inst_VOP3A(iFmt, "v_cmpx_eq_i64", true)
7848 {
7849 setFlag(ALU);
7850 setFlag(WritesEXEC);
7851 } // Inst_VOP3__V_CMPX_EQ_I64
7852
7853 Inst_VOP3__V_CMPX_EQ_I64::~Inst_VOP3__V_CMPX_EQ_I64()
7854 {
7855 } // ~Inst_VOP3__V_CMPX_EQ_I64
7856
7857 // --- description from .arch file ---
7858 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
7859 void
7860 Inst_VOP3__V_CMPX_EQ_I64::execute(GPUDynInstPtr gpuDynInst)
7861 {
7862 Wavefront *wf = gpuDynInst->wavefront();
7863 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
7864 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
7865 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7866
7867 src0.readSrc();
7868 src1.readSrc();
7869
7873 assert(!(instData.ABS & 0x1));
7874 assert(!(instData.ABS & 0x2));
7875 assert(!(instData.ABS & 0x4));
7876 assert(!(extData.NEG & 0x1));
7877 assert(!(extData.NEG & 0x2));
7878 assert(!(extData.NEG & 0x4));
7879
7880 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7881 if (wf->execMask(lane)) {
7882 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
7883 }
7884 }
7885
7886 wf->execMask() = sdst.rawData();
7887 sdst.write();
7888 } // execute
7889 // --- Inst_VOP3__V_CMPX_LE_I64 class methods ---
7890
7891 Inst_VOP3__V_CMPX_LE_I64::Inst_VOP3__V_CMPX_LE_I64(
7892 InFmt_VOP3A *iFmt)
7893 : Inst_VOP3A(iFmt, "v_cmpx_le_i64", true)
7894 {
7895 setFlag(ALU);
7896 setFlag(WritesEXEC);
7897 } // Inst_VOP3__V_CMPX_LE_I64
7898
7899 Inst_VOP3__V_CMPX_LE_I64::~Inst_VOP3__V_CMPX_LE_I64()
7900 {
7901 } // ~Inst_VOP3__V_CMPX_LE_I64
7902
7903 // --- description from .arch file ---
7904 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
7905 void
7906 Inst_VOP3__V_CMPX_LE_I64::execute(GPUDynInstPtr gpuDynInst)
7907 {
7908 Wavefront *wf = gpuDynInst->wavefront();
7909 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
7910 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
7911 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7912
7913 src0.readSrc();
7914 src1.readSrc();
7915
7919 assert(!(instData.ABS & 0x1));
7920 assert(!(instData.ABS & 0x2));
7921 assert(!(instData.ABS & 0x4));
7922 assert(!(extData.NEG & 0x1));
7923 assert(!(extData.NEG & 0x2));
7924 assert(!(extData.NEG & 0x4));
7925
7926 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7927 if (wf->execMask(lane)) {
7928 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
7929 }
7930 }
7931
7932 wf->execMask() = sdst.rawData();
7933 sdst.write();
7934 } // execute
7935 // --- Inst_VOP3__V_CMPX_GT_I64 class methods ---
7936
7937 Inst_VOP3__V_CMPX_GT_I64::Inst_VOP3__V_CMPX_GT_I64(
7938 InFmt_VOP3A *iFmt)
7939 : Inst_VOP3A(iFmt, "v_cmpx_gt_i64", true)
7940 {
7941 setFlag(ALU);
7942 setFlag(WritesEXEC);
7943 } // Inst_VOP3__V_CMPX_GT_I64
7944
7945 Inst_VOP3__V_CMPX_GT_I64::~Inst_VOP3__V_CMPX_GT_I64()
7946 {
7947 } // ~Inst_VOP3__V_CMPX_GT_I64
7948
7949 // --- description from .arch file ---
7950 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
7951 void
7952 Inst_VOP3__V_CMPX_GT_I64::execute(GPUDynInstPtr gpuDynInst)
7953 {
7954 Wavefront *wf = gpuDynInst->wavefront();
7955 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
7956 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
7957 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
7958
7959 src0.readSrc();
7960 src1.readSrc();
7961
7965 assert(!(instData.ABS & 0x1));
7966 assert(!(instData.ABS & 0x2));
7967 assert(!(instData.ABS & 0x4));
7968 assert(!(extData.NEG & 0x1));
7969 assert(!(extData.NEG & 0x2));
7970 assert(!(extData.NEG & 0x4));
7971
7972 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
7973 if (wf->execMask(lane)) {
7974 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
7975 }
7976 }
7977
7978 wf->execMask() = sdst.rawData();
7979 sdst.write();
7980 } // execute
7981 // --- Inst_VOP3__V_CMPX_NE_I64 class methods ---
7982
7983 Inst_VOP3__V_CMPX_NE_I64::Inst_VOP3__V_CMPX_NE_I64(
7984 InFmt_VOP3A *iFmt)
7985 : Inst_VOP3A(iFmt, "v_cmpx_ne_i64", true)
7986 {
7987 setFlag(ALU);
7988 setFlag(WritesEXEC);
7989 } // Inst_VOP3__V_CMPX_NE_I64
7990
7991 Inst_VOP3__V_CMPX_NE_I64::~Inst_VOP3__V_CMPX_NE_I64()
7992 {
7993 } // ~Inst_VOP3__V_CMPX_NE_I64
7994
7995 // --- description from .arch file ---
7996 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
7997 void
7998 Inst_VOP3__V_CMPX_NE_I64::execute(GPUDynInstPtr gpuDynInst)
7999 {
8000 Wavefront *wf = gpuDynInst->wavefront();
8001 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
8002 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
8003 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
8004
8005 src0.readSrc();
8006 src1.readSrc();
8007
8011 assert(!(instData.ABS & 0x1));
8012 assert(!(instData.ABS & 0x2));
8013 assert(!(instData.ABS & 0x4));
8014 assert(!(extData.NEG & 0x1));
8015 assert(!(extData.NEG & 0x2));
8016 assert(!(extData.NEG & 0x4));
8017
8018 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
8019 if (wf->execMask(lane)) {
8020 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
8021 }
8022 }
8023
8024 wf->execMask() = sdst.rawData();
8025 sdst.write();
8026 } // execute
8027 // --- Inst_VOP3__V_CMPX_GE_I64 class methods ---
8028
8029 Inst_VOP3__V_CMPX_GE_I64::Inst_VOP3__V_CMPX_GE_I64(
8030 InFmt_VOP3A *iFmt)
8031 : Inst_VOP3A(iFmt, "v_cmpx_ge_i64", true)
8032 {
8033 setFlag(ALU);
8034 setFlag(WritesEXEC);
8035 } // Inst_VOP3__V_CMPX_GE_I64
8036
8037 Inst_VOP3__V_CMPX_GE_I64::~Inst_VOP3__V_CMPX_GE_I64()
8038 {
8039 } // ~Inst_VOP3__V_CMPX_GE_I64
8040
8041 // --- description from .arch file ---
8042 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
8043 void
8044 Inst_VOP3__V_CMPX_GE_I64::execute(GPUDynInstPtr gpuDynInst)
8045 {
8046 Wavefront *wf = gpuDynInst->wavefront();
8047 ConstVecOperandI64 src0(gpuDynInst, extData.SRC0);
8048 ConstVecOperandI64 src1(gpuDynInst, extData.SRC1);
8049 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
8050
8051 src0.readSrc();
8052 src1.readSrc();
8053
8057 assert(!(instData.ABS & 0x1));
8058 assert(!(instData.ABS & 0x2));
8059 assert(!(instData.ABS & 0x4));
8060 assert(!(extData.NEG & 0x1));
8061 assert(!(extData.NEG & 0x2));
8062 assert(!(extData.NEG & 0x4));
8063
8064 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
8065 if (wf->execMask(lane)) {
8066 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
8067 }
8068 }
8069
8070 wf->execMask() = sdst.rawData();
8071 sdst.write();
8072 } // execute
8073 // --- Inst_VOP3__V_CMPX_T_I64 class methods ---
8074
8075 Inst_VOP3__V_CMPX_T_I64::Inst_VOP3__V_CMPX_T_I64(
8076 InFmt_VOP3A *iFmt)
8077 : Inst_VOP3A(iFmt, "v_cmpx_t_i64", true)
8078 {
8079 setFlag(ALU);
8080 setFlag(WritesEXEC);
8081 } // Inst_VOP3__V_CMPX_T_I64
8082
8083 Inst_VOP3__V_CMPX_T_I64::~Inst_VOP3__V_CMPX_T_I64()
8084 {
8085 } // ~Inst_VOP3__V_CMPX_T_I64
8086
8087 // --- description from .arch file ---
8088 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
8089 void
8090 Inst_VOP3__V_CMPX_T_I64::execute(GPUDynInstPtr gpuDynInst)
8091 {
8092 Wavefront *wf = gpuDynInst->wavefront();
8093 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
8094
8095 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
8096 if (wf->execMask(lane)) {
8097 sdst.setBit(lane, 1);
8098 }
8099 }
8100
8101 wf->execMask() = sdst.rawData();
8102 sdst.write();
8103 } // execute
8104 // --- Inst_VOP3__V_CMPX_F_U64 class methods ---
8105
8106 Inst_VOP3__V_CMPX_F_U64::Inst_VOP3__V_CMPX_F_U64(
8107 InFmt_VOP3A *iFmt)
8108 : Inst_VOP3A(iFmt, "v_cmpx_f_u64", true)
8109 {
8110 setFlag(ALU);
8111 setFlag(WritesEXEC);
8112 } // Inst_VOP3__V_CMPX_F_U64
8113
8114 Inst_VOP3__V_CMPX_F_U64::~Inst_VOP3__V_CMPX_F_U64()
8115 {
8116 } // ~Inst_VOP3__V_CMPX_F_U64
8117
8118 // --- description from .arch file ---
8119 // EXEC,D.u64[threadID] = 0; D = VCC in VOPC encoding.
8120 void
8121 Inst_VOP3__V_CMPX_F_U64::execute(GPUDynInstPtr gpuDynInst)
8122 {
8123 Wavefront *wf = gpuDynInst->wavefront();
8124 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
8125
8126 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
8127 if (wf->execMask(lane)) {
8128 sdst.setBit(lane, 0);
8129 }
8130 }
8131
8132 wf->execMask() = sdst.rawData();
8133 sdst.write();
8134 } // execute
8135 // --- Inst_VOP3__V_CMPX_LT_U64 class methods ---
8136
8137 Inst_VOP3__V_CMPX_LT_U64::Inst_VOP3__V_CMPX_LT_U64(
8138 InFmt_VOP3A *iFmt)
8139 : Inst_VOP3A(iFmt, "v_cmpx_lt_u64", true)
8140 {
8141 setFlag(ALU);
8142 setFlag(WritesEXEC);
8143 } // Inst_VOP3__V_CMPX_LT_U64
8144
8145 Inst_VOP3__V_CMPX_LT_U64::~Inst_VOP3__V_CMPX_LT_U64()
8146 {
8147 } // ~Inst_VOP3__V_CMPX_LT_U64
8148
8149 // --- description from .arch file ---
8150 // EXEC,D.u64[threadID] = (S0 < S1); D = VCC in VOPC encoding.
8151 void
8152 Inst_VOP3__V_CMPX_LT_U64::execute(GPUDynInstPtr gpuDynInst)
8153 {
8154 Wavefront *wf = gpuDynInst->wavefront();
8155 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
8156 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
8157 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
8158
8159 src0.readSrc();
8160 src1.readSrc();
8161
8165 assert(!(instData.ABS & 0x1));
8166 assert(!(instData.ABS & 0x2));
8167 assert(!(instData.ABS & 0x4));
8168 assert(!(extData.NEG & 0x1));
8169 assert(!(extData.NEG & 0x2));
8170 assert(!(extData.NEG & 0x4));
8171
8172 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
8173 if (wf->execMask(lane)) {
8174 sdst.setBit(lane, src0[lane] < src1[lane] ? 1 : 0);
8175 }
8176 }
8177
8178 wf->execMask() = sdst.rawData();
8179 sdst.write();
8180 } // execute
8181 // --- Inst_VOP3__V_CMPX_EQ_U64 class methods ---
8182
8183 Inst_VOP3__V_CMPX_EQ_U64::Inst_VOP3__V_CMPX_EQ_U64(
8184 InFmt_VOP3A *iFmt)
8185 : Inst_VOP3A(iFmt, "v_cmpx_eq_u64", true)
8186 {
8187 setFlag(ALU);
8188 setFlag(WritesEXEC);
8189 } // Inst_VOP3__V_CMPX_EQ_U64
8190
8191 Inst_VOP3__V_CMPX_EQ_U64::~Inst_VOP3__V_CMPX_EQ_U64()
8192 {
8193 } // ~Inst_VOP3__V_CMPX_EQ_U64
8194
8195 // --- description from .arch file ---
8196 // EXEC,D.u64[threadID] = (S0 == S1); D = VCC in VOPC encoding.
8197 void
8198 Inst_VOP3__V_CMPX_EQ_U64::execute(GPUDynInstPtr gpuDynInst)
8199 {
8200 Wavefront *wf = gpuDynInst->wavefront();
8201 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
8202 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
8203 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
8204
8205 src0.readSrc();
8206 src1.readSrc();
8207
8211 assert(!(instData.ABS & 0x1));
8212 assert(!(instData.ABS & 0x2));
8213 assert(!(instData.ABS & 0x4));
8214 assert(!(extData.NEG & 0x1));
8215 assert(!(extData.NEG & 0x2));
8216 assert(!(extData.NEG & 0x4));
8217
8218 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
8219 if (wf->execMask(lane)) {
8220 sdst.setBit(lane, src0[lane] == src1[lane] ? 1 : 0);
8221 }
8222 }
8223
8224 wf->execMask() = sdst.rawData();
8225 sdst.write();
8226 } // execute
8227 // --- Inst_VOP3__V_CMPX_LE_U64 class methods ---
8228
8229 Inst_VOP3__V_CMPX_LE_U64::Inst_VOP3__V_CMPX_LE_U64(
8230 InFmt_VOP3A *iFmt)
8231 : Inst_VOP3A(iFmt, "v_cmpx_le_u64", true)
8232 {
8233 setFlag(ALU);
8234 setFlag(WritesEXEC);
8235 } // Inst_VOP3__V_CMPX_LE_U64
8236
8237 Inst_VOP3__V_CMPX_LE_U64::~Inst_VOP3__V_CMPX_LE_U64()
8238 {
8239 } // ~Inst_VOP3__V_CMPX_LE_U64
8240
8241 // --- description from .arch file ---
8242 // EXEC,D.u64[threadID] = (S0 <= S1); D = VCC in VOPC encoding.
8243 void
8244 Inst_VOP3__V_CMPX_LE_U64::execute(GPUDynInstPtr gpuDynInst)
8245 {
8246 Wavefront *wf = gpuDynInst->wavefront();
8247 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
8248 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
8249 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
8250
8251 src0.readSrc();
8252 src1.readSrc();
8253
8257 assert(!(instData.ABS & 0x1));
8258 assert(!(instData.ABS & 0x2));
8259 assert(!(instData.ABS & 0x4));
8260 assert(!(extData.NEG & 0x1));
8261 assert(!(extData.NEG & 0x2));
8262 assert(!(extData.NEG & 0x4));
8263
8264 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
8265 if (wf->execMask(lane)) {
8266 sdst.setBit(lane, src0[lane] <= src1[lane] ? 1 : 0);
8267 }
8268 }
8269
8270 wf->execMask() = sdst.rawData();
8271 sdst.write();
8272 } // execute
8273 // --- Inst_VOP3__V_CMPX_GT_U64 class methods ---
8274
8275 Inst_VOP3__V_CMPX_GT_U64::Inst_VOP3__V_CMPX_GT_U64(
8276 InFmt_VOP3A *iFmt)
8277 : Inst_VOP3A(iFmt, "v_cmpx_gt_u64", true)
8278 {
8279 setFlag(ALU);
8280 setFlag(WritesEXEC);
8281 } // Inst_VOP3__V_CMPX_GT_U64
8282
8283 Inst_VOP3__V_CMPX_GT_U64::~Inst_VOP3__V_CMPX_GT_U64()
8284 {
8285 } // ~Inst_VOP3__V_CMPX_GT_U64
8286
8287 // --- description from .arch file ---
8288 // EXEC,D.u64[threadID] = (S0 > S1); D = VCC in VOPC encoding.
8289 void
8290 Inst_VOP3__V_CMPX_GT_U64::execute(GPUDynInstPtr gpuDynInst)
8291 {
8292 Wavefront *wf = gpuDynInst->wavefront();
8293 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
8294 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
8295 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
8296
8297 src0.readSrc();
8298 src1.readSrc();
8299
8303 assert(!(instData.ABS & 0x1));
8304 assert(!(instData.ABS & 0x2));
8305 assert(!(instData.ABS & 0x4));
8306 assert(!(extData.NEG & 0x1));
8307 assert(!(extData.NEG & 0x2));
8308 assert(!(extData.NEG & 0x4));
8309
8310 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
8311 if (wf->execMask(lane)) {
8312 sdst.setBit(lane, src0[lane] > src1[lane] ? 1 : 0);
8313 }
8314 }
8315
8316 wf->execMask() = sdst.rawData();
8317 sdst.write();
8318 } // execute
8319 // --- Inst_VOP3__V_CMPX_NE_U64 class methods ---
8320
8321 Inst_VOP3__V_CMPX_NE_U64::Inst_VOP3__V_CMPX_NE_U64(
8322 InFmt_VOP3A *iFmt)
8323 : Inst_VOP3A(iFmt, "v_cmpx_ne_u64", true)
8324 {
8325 setFlag(ALU);
8326 setFlag(WritesEXEC);
8327 } // Inst_VOP3__V_CMPX_NE_U64
8328
8329 Inst_VOP3__V_CMPX_NE_U64::~Inst_VOP3__V_CMPX_NE_U64()
8330 {
8331 } // ~Inst_VOP3__V_CMPX_NE_U64
8332
8333 // --- description from .arch file ---
8334 // EXEC,D.u64[threadID] = (S0 <> S1); D = VCC in VOPC encoding.
8335 void
8336 Inst_VOP3__V_CMPX_NE_U64::execute(GPUDynInstPtr gpuDynInst)
8337 {
8338 Wavefront *wf = gpuDynInst->wavefront();
8339 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
8340 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
8341 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
8342
8343 src0.readSrc();
8344 src1.readSrc();
8345
8349 assert(!(instData.ABS & 0x1));
8350 assert(!(instData.ABS & 0x2));
8351 assert(!(instData.ABS & 0x4));
8352 assert(!(extData.NEG & 0x1));
8353 assert(!(extData.NEG & 0x2));
8354 assert(!(extData.NEG & 0x4));
8355
8356 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
8357 if (wf->execMask(lane)) {
8358 sdst.setBit(lane, src0[lane] != src1[lane] ? 1 : 0);
8359 }
8360 }
8361
8362 wf->execMask() = sdst.rawData();
8363 sdst.write();
8364 } // execute
8365 // --- Inst_VOP3__V_CMPX_GE_U64 class methods ---
8366
8367 Inst_VOP3__V_CMPX_GE_U64::Inst_VOP3__V_CMPX_GE_U64(
8368 InFmt_VOP3A *iFmt)
8369 : Inst_VOP3A(iFmt, "v_cmpx_ge_u64", true)
8370 {
8371 setFlag(ALU);
8372 setFlag(WritesEXEC);
8373 } // Inst_VOP3__V_CMPX_GE_U64
8374
8375 Inst_VOP3__V_CMPX_GE_U64::~Inst_VOP3__V_CMPX_GE_U64()
8376 {
8377 } // ~Inst_VOP3__V_CMPX_GE_U64
8378
8379 // --- description from .arch file ---
8380 // EXEC,D.u64[threadID] = (S0 >= S1); D = VCC in VOPC encoding.
8381 void
8382 Inst_VOP3__V_CMPX_GE_U64::execute(GPUDynInstPtr gpuDynInst)
8383 {
8384 Wavefront *wf = gpuDynInst->wavefront();
8385 ConstVecOperandU64 src0(gpuDynInst, extData.SRC0);
8386 ConstVecOperandU64 src1(gpuDynInst, extData.SRC1);
8387 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
8388
8389 src0.readSrc();
8390 src1.readSrc();
8391
8395 assert(!(instData.ABS & 0x1));
8396 assert(!(instData.ABS & 0x2));
8397 assert(!(instData.ABS & 0x4));
8398 assert(!(extData.NEG & 0x1));
8399 assert(!(extData.NEG & 0x2));
8400 assert(!(extData.NEG & 0x4));
8401
8402 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
8403 if (wf->execMask(lane)) {
8404 sdst.setBit(lane, src0[lane] >= src1[lane] ? 1 : 0);
8405 }
8406 }
8407
8408 wf->execMask() = sdst.rawData();
8409 sdst.write();
8410 } // execute
8411 // --- Inst_VOP3__V_CMPX_T_U64 class methods ---
8412
8413 Inst_VOP3__V_CMPX_T_U64::Inst_VOP3__V_CMPX_T_U64(
8414 InFmt_VOP3A *iFmt)
8415 : Inst_VOP3A(iFmt, "v_cmpx_t_u64", true)
8416 {
8417 setFlag(ALU);
8418 setFlag(WritesEXEC);
8419 } // Inst_VOP3__V_CMPX_T_U64
8420
8421 Inst_VOP3__V_CMPX_T_U64::~Inst_VOP3__V_CMPX_T_U64()
8422 {
8423 } // ~Inst_VOP3__V_CMPX_T_U64
8424
8425 // --- description from .arch file ---
8426 // EXEC,D.u64[threadID] = 1; D = VCC in VOPC encoding.
8427 void
8428 Inst_VOP3__V_CMPX_T_U64::execute(GPUDynInstPtr gpuDynInst)
8429 {
8430 Wavefront *wf = gpuDynInst->wavefront();
8431 ScalarOperandU64 sdst(gpuDynInst, instData.VDST);
8432
8436 assert(!(instData.ABS & 0x1));
8437 assert(!(instData.ABS & 0x2));
8438 assert(!(instData.ABS & 0x4));
8439 assert(!(extData.NEG & 0x1));
8440 assert(!(extData.NEG & 0x2));
8441 assert(!(extData.NEG & 0x4));
8442
8443 for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
8444 if (wf->execMask(lane)) {
8445 sdst.setBit(lane, 1);
8446 }
8447 }
8448
8449 wf->execMask() = sdst.rawData();
8450 sdst.write();
8451 } // execute
8452} // namespace VegaISA
8453} // namespace gem5
gem5::GPUStaticInst::setFlag
void setFlag(Flags flag)
Definition gpu_static_inst.hh:251
gem5::VegaISA::Inst_VOP3A::Inst_VOP3A
Inst_VOP3A(InFmt_VOP3A *, const std::string &opcode, bool sgpr_dst)
Definition op_encodings.cc:956
gem5::VegaISA::Inst_VOP3A::extData
InFmt_VOP3_1 extData
Definition op_encodings.hh:610
gem5::VegaISA::Inst_VOP3A::instData
InFmt_VOP3A instData
Definition op_encodings.hh:608
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F16::~Inst_VOP3__V_CMPX_CLASS_F16
~Inst_VOP3__V_CMPX_CLASS_F16()
Definition vop3_cmp.cc:554
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:574
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F16::Inst_VOP3__V_CMPX_CLASS_F16
Inst_VOP3__V_CMPX_CLASS_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:545
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F32::Inst_VOP3__V_CMPX_CLASS_F32
Inst_VOP3__V_CMPX_CLASS_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:158
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F32::~Inst_VOP3__V_CMPX_CLASS_F32
~Inst_VOP3__V_CMPX_CLASS_F32()
Definition vop3_cmp.cc:167
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:187
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F64::Inst_VOP3__V_CMPX_CLASS_F64
Inst_VOP3__V_CMPX_CLASS_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:393
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:422
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F64::~Inst_VOP3__V_CMPX_CLASS_F64
~Inst_VOP3__V_CMPX_CLASS_F64()
Definition vop3_cmp.cc:402
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:991
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F16::Inst_VOP3__V_CMPX_EQ_F16
Inst_VOP3__V_CMPX_EQ_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:975
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F16::~Inst_VOP3__V_CMPX_EQ_F16
~Inst_VOP3__V_CMPX_EQ_F16()
Definition vop3_cmp.cc:984
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F32::~Inst_VOP3__V_CMPX_EQ_F32
~Inst_VOP3__V_CMPX_EQ_F32()
Definition vop3_cmp.cc:2231
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2238
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F32::Inst_VOP3__V_CMPX_EQ_F32
Inst_VOP3__V_CMPX_EQ_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2222
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F64::Inst_VOP3__V_CMPX_EQ_F64
Inst_VOP3__V_CMPX_EQ_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3691
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3707
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F64::~Inst_VOP3__V_CMPX_EQ_F64
~Inst_VOP3__V_CMPX_EQ_F64()
Definition vop3_cmp.cc:3700
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5228
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I16::Inst_VOP3__V_CMPX_EQ_I16
Inst_VOP3__V_CMPX_EQ_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5213
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I16::~Inst_VOP3__V_CMPX_EQ_I16
~Inst_VOP3__V_CMPX_EQ_I16()
Definition vop3_cmp.cc:5221
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I32::Inst_VOP3__V_CMPX_EQ_I32
Inst_VOP3__V_CMPX_EQ_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6529
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I32::~Inst_VOP3__V_CMPX_EQ_I32
~Inst_VOP3__V_CMPX_EQ_I32()
Definition vop3_cmp.cc:6537
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6544
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I64::~Inst_VOP3__V_CMPX_EQ_I64
~Inst_VOP3__V_CMPX_EQ_I64()
Definition vop3_cmp.cc:7853
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7860
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I64::Inst_VOP3__V_CMPX_EQ_I64
Inst_VOP3__V_CMPX_EQ_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7845
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5566
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U16::~Inst_VOP3__V_CMPX_EQ_U16
~Inst_VOP3__V_CMPX_EQ_U16()
Definition vop3_cmp.cc:5559
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U16::Inst_VOP3__V_CMPX_EQ_U16
Inst_VOP3__V_CMPX_EQ_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5551
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U32::~Inst_VOP3__V_CMPX_EQ_U32
~Inst_VOP3__V_CMPX_EQ_U32()
Definition vop3_cmp.cc:6875
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6882
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U32::Inst_VOP3__V_CMPX_EQ_U32
Inst_VOP3__V_CMPX_EQ_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6867
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:8198
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U64::~Inst_VOP3__V_CMPX_EQ_U64
~Inst_VOP3__V_CMPX_EQ_U64()
Definition vop3_cmp.cc:8191
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U64::Inst_VOP3__V_CMPX_EQ_U64
Inst_VOP3__V_CMPX_EQ_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:8183
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F16::Inst_VOP3__V_CMPX_F_F16
Inst_VOP3__V_CMPX_F_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:922
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F16::~Inst_VOP3__V_CMPX_F_F16
~Inst_VOP3__V_CMPX_F_F16()
Definition vop3_cmp.cc:930
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:937
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F32::Inst_VOP3__V_CMPX_F_F32
Inst_VOP3__V_CMPX_F_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2153
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2169
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F32::~Inst_VOP3__V_CMPX_F_F32
~Inst_VOP3__V_CMPX_F_F32()
Definition vop3_cmp.cc:2162
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F64::Inst_VOP3__V_CMPX_F_F64
Inst_VOP3__V_CMPX_F_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3600
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F64::~Inst_VOP3__V_CMPX_F_F64
~Inst_VOP3__V_CMPX_F_F64()
Definition vop3_cmp.cc:3609
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3616
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I16::~Inst_VOP3__V_CMPX_F_I16
~Inst_VOP3__V_CMPX_F_I16()
Definition vop3_cmp.cc:5144
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I16::Inst_VOP3__V_CMPX_F_I16
Inst_VOP3__V_CMPX_F_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5136
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5151
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I32::~Inst_VOP3__V_CMPX_F_I32
~Inst_VOP3__V_CMPX_F_I32()
Definition vop3_cmp.cc:6460
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6467
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I32::Inst_VOP3__V_CMPX_F_I32
Inst_VOP3__V_CMPX_F_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6452
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7783
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I64::~Inst_VOP3__V_CMPX_F_I64
~Inst_VOP3__V_CMPX_F_I64()
Definition vop3_cmp.cc:7776
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I64::Inst_VOP3__V_CMPX_F_I64
Inst_VOP3__V_CMPX_F_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7768
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U16::Inst_VOP3__V_CMPX_F_U16
Inst_VOP3__V_CMPX_F_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5474
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5489
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U16::~Inst_VOP3__V_CMPX_F_U16
~Inst_VOP3__V_CMPX_F_U16()
Definition vop3_cmp.cc:5482
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6805
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U32::~Inst_VOP3__V_CMPX_F_U32
~Inst_VOP3__V_CMPX_F_U32()
Definition vop3_cmp.cc:6798
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U32::Inst_VOP3__V_CMPX_F_U32
Inst_VOP3__V_CMPX_F_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6790
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U64::Inst_VOP3__V_CMPX_F_U64
Inst_VOP3__V_CMPX_F_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:8106
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U64::~Inst_VOP3__V_CMPX_F_U64
~Inst_VOP3__V_CMPX_F_U64()
Definition vop3_cmp.cc:8114
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:8121
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F16::~Inst_VOP3__V_CMPX_GE_F16
~Inst_VOP3__V_CMPX_GE_F16()
Definition vop3_cmp.cc:1072
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F16::Inst_VOP3__V_CMPX_GE_F16
Inst_VOP3__V_CMPX_GE_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1063
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1079
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F32::~Inst_VOP3__V_CMPX_GE_F32
~Inst_VOP3__V_CMPX_GE_F32()
Definition vop3_cmp.cc:2380
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2387
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F32::Inst_VOP3__V_CMPX_GE_F32
Inst_VOP3__V_CMPX_GE_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2371
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F64::~Inst_VOP3__V_CMPX_GE_F64
~Inst_VOP3__V_CMPX_GE_F64()
Definition vop3_cmp.cc:3937
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3944
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F64::Inst_VOP3__V_CMPX_GE_F64
Inst_VOP3__V_CMPX_GE_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3928
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I16::~Inst_VOP3__V_CMPX_GE_I16
~Inst_VOP3__V_CMPX_GE_I16()
Definition vop3_cmp.cc:5405
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5412
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I16::Inst_VOP3__V_CMPX_GE_I16
Inst_VOP3__V_CMPX_GE_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5397
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I32::~Inst_VOP3__V_CMPX_GE_I32
~Inst_VOP3__V_CMPX_GE_I32()
Definition vop3_cmp.cc:6721
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6728
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I32::Inst_VOP3__V_CMPX_GE_I32
Inst_VOP3__V_CMPX_GE_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6713
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I64::Inst_VOP3__V_CMPX_GE_I64
Inst_VOP3__V_CMPX_GE_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:8029
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:8044
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I64::~Inst_VOP3__V_CMPX_GE_I64
~Inst_VOP3__V_CMPX_GE_I64()
Definition vop3_cmp.cc:8037
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5750
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U16::~Inst_VOP3__V_CMPX_GE_U16
~Inst_VOP3__V_CMPX_GE_U16()
Definition vop3_cmp.cc:5743
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U16::Inst_VOP3__V_CMPX_GE_U16
Inst_VOP3__V_CMPX_GE_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5735
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U32::Inst_VOP3__V_CMPX_GE_U32
Inst_VOP3__V_CMPX_GE_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:7051
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7066
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U32::~Inst_VOP3__V_CMPX_GE_U32
~Inst_VOP3__V_CMPX_GE_U32()
Definition vop3_cmp.cc:7059
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U64::Inst_VOP3__V_CMPX_GE_U64
Inst_VOP3__V_CMPX_GE_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:8367
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:8382
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U64::~Inst_VOP3__V_CMPX_GE_U64
~Inst_VOP3__V_CMPX_GE_U64()
Definition vop3_cmp.cc:8375
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1035
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F16::Inst_VOP3__V_CMPX_GT_F16
Inst_VOP3__V_CMPX_GT_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1019
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F16::~Inst_VOP3__V_CMPX_GT_F16
~Inst_VOP3__V_CMPX_GT_F16()
Definition vop3_cmp.cc:1028
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F32::Inst_VOP3__V_CMPX_GT_F32
Inst_VOP3__V_CMPX_GT_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2296
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2312
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F32::~Inst_VOP3__V_CMPX_GT_F32
~Inst_VOP3__V_CMPX_GT_F32()
Definition vop3_cmp.cc:2305
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3825
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F64::Inst_VOP3__V_CMPX_GT_F64
Inst_VOP3__V_CMPX_GT_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3809
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F64::~Inst_VOP3__V_CMPX_GT_F64
~Inst_VOP3__V_CMPX_GT_F64()
Definition vop3_cmp.cc:3818
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I16::~Inst_VOP3__V_CMPX_GT_I16
~Inst_VOP3__V_CMPX_GT_I16()
Definition vop3_cmp.cc:5313
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I16::Inst_VOP3__V_CMPX_GT_I16
Inst_VOP3__V_CMPX_GT_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5305
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5320
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I32::Inst_VOP3__V_CMPX_GT_I32
Inst_VOP3__V_CMPX_GT_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6621
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6636
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I32::~Inst_VOP3__V_CMPX_GT_I32
~Inst_VOP3__V_CMPX_GT_I32()
Definition vop3_cmp.cc:6629
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I64::Inst_VOP3__V_CMPX_GT_I64
Inst_VOP3__V_CMPX_GT_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7937
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7952
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I64::~Inst_VOP3__V_CMPX_GT_I64
~Inst_VOP3__V_CMPX_GT_I64()
Definition vop3_cmp.cc:7945
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U16::~Inst_VOP3__V_CMPX_GT_U16
~Inst_VOP3__V_CMPX_GT_U16()
Definition vop3_cmp.cc:5651
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5658
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U16::Inst_VOP3__V_CMPX_GT_U16
Inst_VOP3__V_CMPX_GT_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5643
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6974
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U32::~Inst_VOP3__V_CMPX_GT_U32
~Inst_VOP3__V_CMPX_GT_U32()
Definition vop3_cmp.cc:6967
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U32::Inst_VOP3__V_CMPX_GT_U32
Inst_VOP3__V_CMPX_GT_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6959
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:8290
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U64::Inst_VOP3__V_CMPX_GT_U64
Inst_VOP3__V_CMPX_GT_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:8275
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U64::~Inst_VOP3__V_CMPX_GT_U64
~Inst_VOP3__V_CMPX_GT_U64()
Definition vop3_cmp.cc:8283
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F16::Inst_VOP3__V_CMPX_LE_F16
Inst_VOP3__V_CMPX_LE_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:997
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F16::~Inst_VOP3__V_CMPX_LE_F16
~Inst_VOP3__V_CMPX_LE_F16()
Definition vop3_cmp.cc:1006
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1013
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F32::~Inst_VOP3__V_CMPX_LE_F32
~Inst_VOP3__V_CMPX_LE_F32()
Definition vop3_cmp.cc:2268
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2275
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F32::Inst_VOP3__V_CMPX_LE_F32
Inst_VOP3__V_CMPX_LE_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2259
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F64::Inst_VOP3__V_CMPX_LE_F64
Inst_VOP3__V_CMPX_LE_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3750
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F64::~Inst_VOP3__V_CMPX_LE_F64
~Inst_VOP3__V_CMPX_LE_F64()
Definition vop3_cmp.cc:3759
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3766
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I16::Inst_VOP3__V_CMPX_LE_I16
Inst_VOP3__V_CMPX_LE_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5259
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5274
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I16::~Inst_VOP3__V_CMPX_LE_I16
~Inst_VOP3__V_CMPX_LE_I16()
Definition vop3_cmp.cc:5267
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6590
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I32::~Inst_VOP3__V_CMPX_LE_I32
~Inst_VOP3__V_CMPX_LE_I32()
Definition vop3_cmp.cc:6583
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I32::Inst_VOP3__V_CMPX_LE_I32
Inst_VOP3__V_CMPX_LE_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6575
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7906
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I64::Inst_VOP3__V_CMPX_LE_I64
Inst_VOP3__V_CMPX_LE_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7891
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I64::~Inst_VOP3__V_CMPX_LE_I64
~Inst_VOP3__V_CMPX_LE_I64()
Definition vop3_cmp.cc:7899
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5612
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U16::Inst_VOP3__V_CMPX_LE_U16
Inst_VOP3__V_CMPX_LE_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5597
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U16::~Inst_VOP3__V_CMPX_LE_U16
~Inst_VOP3__V_CMPX_LE_U16()
Definition vop3_cmp.cc:5605
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U32::Inst_VOP3__V_CMPX_LE_U32
Inst_VOP3__V_CMPX_LE_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6913
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U32::~Inst_VOP3__V_CMPX_LE_U32
~Inst_VOP3__V_CMPX_LE_U32()
Definition vop3_cmp.cc:6921
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6928
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U64::~Inst_VOP3__V_CMPX_LE_U64
~Inst_VOP3__V_CMPX_LE_U64()
Definition vop3_cmp.cc:8237
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U64::Inst_VOP3__V_CMPX_LE_U64
Inst_VOP3__V_CMPX_LE_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:8229
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:8244
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F16::Inst_VOP3__V_CMPX_LG_F16
Inst_VOP3__V_CMPX_LG_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1041
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1057
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F16::~Inst_VOP3__V_CMPX_LG_F16
~Inst_VOP3__V_CMPX_LG_F16()
Definition vop3_cmp.cc:1050
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F32::Inst_VOP3__V_CMPX_LG_F32
Inst_VOP3__V_CMPX_LG_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2333
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F32::~Inst_VOP3__V_CMPX_LG_F32
~Inst_VOP3__V_CMPX_LG_F32()
Definition vop3_cmp.cc:2342
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2349
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3884
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F64::~Inst_VOP3__V_CMPX_LG_F64
~Inst_VOP3__V_CMPX_LG_F64()
Definition vop3_cmp.cc:3877
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F64::Inst_VOP3__V_CMPX_LG_F64
Inst_VOP3__V_CMPX_LG_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3868
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F16::Inst_VOP3__V_CMPX_LT_F16
Inst_VOP3__V_CMPX_LT_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:953
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:969
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F16::~Inst_VOP3__V_CMPX_LT_F16
~Inst_VOP3__V_CMPX_LT_F16()
Definition vop3_cmp.cc:962
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F32::~Inst_VOP3__V_CMPX_LT_F32
~Inst_VOP3__V_CMPX_LT_F32()
Definition vop3_cmp.cc:2194
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F32::Inst_VOP3__V_CMPX_LT_F32
Inst_VOP3__V_CMPX_LT_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2185
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2201
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F64::Inst_VOP3__V_CMPX_LT_F64
Inst_VOP3__V_CMPX_LT_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3632
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F64::~Inst_VOP3__V_CMPX_LT_F64
~Inst_VOP3__V_CMPX_LT_F64()
Definition vop3_cmp.cc:3641
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3648
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I16::~Inst_VOP3__V_CMPX_LT_I16
~Inst_VOP3__V_CMPX_LT_I16()
Definition vop3_cmp.cc:5175
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5182
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I16::Inst_VOP3__V_CMPX_LT_I16
Inst_VOP3__V_CMPX_LT_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5167
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I32::Inst_VOP3__V_CMPX_LT_I32
Inst_VOP3__V_CMPX_LT_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6483
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6498
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I32::~Inst_VOP3__V_CMPX_LT_I32
~Inst_VOP3__V_CMPX_LT_I32()
Definition vop3_cmp.cc:6491
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7814
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I64::~Inst_VOP3__V_CMPX_LT_I64
~Inst_VOP3__V_CMPX_LT_I64()
Definition vop3_cmp.cc:7807
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I64::Inst_VOP3__V_CMPX_LT_I64
Inst_VOP3__V_CMPX_LT_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7799
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U16::~Inst_VOP3__V_CMPX_LT_U16
~Inst_VOP3__V_CMPX_LT_U16()
Definition vop3_cmp.cc:5513
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U16::Inst_VOP3__V_CMPX_LT_U16
Inst_VOP3__V_CMPX_LT_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5505
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5520
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U32::~Inst_VOP3__V_CMPX_LT_U32
~Inst_VOP3__V_CMPX_LT_U32()
Definition vop3_cmp.cc:6829
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U32::Inst_VOP3__V_CMPX_LT_U32
Inst_VOP3__V_CMPX_LT_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6821
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6836
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:8152
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U64::~Inst_VOP3__V_CMPX_LT_U64
~Inst_VOP3__V_CMPX_LT_U64()
Definition vop3_cmp.cc:8145
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U64::Inst_VOP3__V_CMPX_LT_U64
Inst_VOP3__V_CMPX_LT_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:8137
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1235
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F16::~Inst_VOP3__V_CMPX_NEQ_F16
~Inst_VOP3__V_CMPX_NEQ_F16()
Definition vop3_cmp.cc:1228
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F16::Inst_VOP3__V_CMPX_NEQ_F16
Inst_VOP3__V_CMPX_NEQ_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1219
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F32::Inst_VOP3__V_CMPX_NEQ_F32
Inst_VOP3__V_CMPX_NEQ_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2635
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2651
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F32::~Inst_VOP3__V_CMPX_NEQ_F32
~Inst_VOP3__V_CMPX_NEQ_F32()
Definition vop3_cmp.cc:2644
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F64::Inst_VOP3__V_CMPX_NEQ_F64
Inst_VOP3__V_CMPX_NEQ_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:4346
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F64::~Inst_VOP3__V_CMPX_NEQ_F64
~Inst_VOP3__V_CMPX_NEQ_F64()
Definition vop3_cmp.cc:4355
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4362
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5366
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I16::~Inst_VOP3__V_CMPX_NE_I16
~Inst_VOP3__V_CMPX_NE_I16()
Definition vop3_cmp.cc:5359
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I16::Inst_VOP3__V_CMPX_NE_I16
Inst_VOP3__V_CMPX_NE_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5351
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6682
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I32::Inst_VOP3__V_CMPX_NE_I32
Inst_VOP3__V_CMPX_NE_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6667
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I32::~Inst_VOP3__V_CMPX_NE_I32
~Inst_VOP3__V_CMPX_NE_I32()
Definition vop3_cmp.cc:6675
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I64::~Inst_VOP3__V_CMPX_NE_I64
~Inst_VOP3__V_CMPX_NE_I64()
Definition vop3_cmp.cc:7991
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7998
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I64::Inst_VOP3__V_CMPX_NE_I64
Inst_VOP3__V_CMPX_NE_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7983
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U16::~Inst_VOP3__V_CMPX_NE_U16
~Inst_VOP3__V_CMPX_NE_U16()
Definition vop3_cmp.cc:5697
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5704
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U16::Inst_VOP3__V_CMPX_NE_U16
Inst_VOP3__V_CMPX_NE_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5689
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U32::Inst_VOP3__V_CMPX_NE_U32
Inst_VOP3__V_CMPX_NE_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:7005
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U32::~Inst_VOP3__V_CMPX_NE_U32
~Inst_VOP3__V_CMPX_NE_U32()
Definition vop3_cmp.cc:7013
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7020
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U64::~Inst_VOP3__V_CMPX_NE_U64
~Inst_VOP3__V_CMPX_NE_U64()
Definition vop3_cmp.cc:8329
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U64::Inst_VOP3__V_CMPX_NE_U64
Inst_VOP3__V_CMPX_NE_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:8321
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:8336
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F16::~Inst_VOP3__V_CMPX_NGE_F16
~Inst_VOP3__V_CMPX_NGE_F16()
Definition vop3_cmp.cc:1140
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F16::Inst_VOP3__V_CMPX_NGE_F16
Inst_VOP3__V_CMPX_NGE_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1131
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1147
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F32::Inst_VOP3__V_CMPX_NGE_F32
Inst_VOP3__V_CMPX_NGE_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2486
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2502
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F32::~Inst_VOP3__V_CMPX_NGE_F32
~Inst_VOP3__V_CMPX_NGE_F32()
Definition vop3_cmp.cc:2495
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4125
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F64::~Inst_VOP3__V_CMPX_NGE_F64
~Inst_VOP3__V_CMPX_NGE_F64()
Definition vop3_cmp.cc:4118
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F64::Inst_VOP3__V_CMPX_NGE_F64
Inst_VOP3__V_CMPX_NGE_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:4109
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F16::Inst_VOP3__V_CMPX_NGT_F16
Inst_VOP3__V_CMPX_NGT_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1175
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F16::~Inst_VOP3__V_CMPX_NGT_F16
~Inst_VOP3__V_CMPX_NGT_F16()
Definition vop3_cmp.cc:1184
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1191
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F32::~Inst_VOP3__V_CMPX_NGT_F32
~Inst_VOP3__V_CMPX_NGT_F32()
Definition vop3_cmp.cc:2570
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F32::Inst_VOP3__V_CMPX_NGT_F32
Inst_VOP3__V_CMPX_NGT_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2561
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2577
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F64::Inst_VOP3__V_CMPX_NGT_F64
Inst_VOP3__V_CMPX_NGT_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:4228
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F64::~Inst_VOP3__V_CMPX_NGT_F64
~Inst_VOP3__V_CMPX_NGT_F64()
Definition vop3_cmp.cc:4237
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4244
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F16::Inst_VOP3__V_CMPX_NLE_F16
Inst_VOP3__V_CMPX_NLE_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1197
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F16::~Inst_VOP3__V_CMPX_NLE_F16
~Inst_VOP3__V_CMPX_NLE_F16()
Definition vop3_cmp.cc:1206
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1213
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2614
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F32::~Inst_VOP3__V_CMPX_NLE_F32
~Inst_VOP3__V_CMPX_NLE_F32()
Definition vop3_cmp.cc:2607
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F32::Inst_VOP3__V_CMPX_NLE_F32
Inst_VOP3__V_CMPX_NLE_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2598
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F64::Inst_VOP3__V_CMPX_NLE_F64
Inst_VOP3__V_CMPX_NLE_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:4287
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4303
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F64::~Inst_VOP3__V_CMPX_NLE_F64
~Inst_VOP3__V_CMPX_NLE_F64()
Definition vop3_cmp.cc:4296
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F16::~Inst_VOP3__V_CMPX_NLG_F16
~Inst_VOP3__V_CMPX_NLG_F16()
Definition vop3_cmp.cc:1162
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F16::Inst_VOP3__V_CMPX_NLG_F16
Inst_VOP3__V_CMPX_NLG_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1153
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1169
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2539
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F32::Inst_VOP3__V_CMPX_NLG_F32
Inst_VOP3__V_CMPX_NLG_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2523
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F32::~Inst_VOP3__V_CMPX_NLG_F32
~Inst_VOP3__V_CMPX_NLG_F32()
Definition vop3_cmp.cc:2532
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F64::Inst_VOP3__V_CMPX_NLG_F64
Inst_VOP3__V_CMPX_NLG_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:4168
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F64::~Inst_VOP3__V_CMPX_NLG_F64
~Inst_VOP3__V_CMPX_NLG_F64()
Definition vop3_cmp.cc:4177
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4184
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F16::Inst_VOP3__V_CMPX_NLT_F16
Inst_VOP3__V_CMPX_NLT_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1241
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F16::~Inst_VOP3__V_CMPX_NLT_F16
~Inst_VOP3__V_CMPX_NLT_F16()
Definition vop3_cmp.cc:1250
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1257
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2688
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F32::Inst_VOP3__V_CMPX_NLT_F32
Inst_VOP3__V_CMPX_NLT_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2672
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F32::~Inst_VOP3__V_CMPX_NLT_F32
~Inst_VOP3__V_CMPX_NLT_F32()
Definition vop3_cmp.cc:2681
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F64::Inst_VOP3__V_CMPX_NLT_F64
Inst_VOP3__V_CMPX_NLT_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:4405
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4421
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F64::~Inst_VOP3__V_CMPX_NLT_F64
~Inst_VOP3__V_CMPX_NLT_F64()
Definition vop3_cmp.cc:4414
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F16::Inst_VOP3__V_CMPX_O_F16
Inst_VOP3__V_CMPX_O_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1085
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1102
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F16::~Inst_VOP3__V_CMPX_O_F16
~Inst_VOP3__V_CMPX_O_F16()
Definition vop3_cmp.cc:1094
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F32::~Inst_VOP3__V_CMPX_O_F32
~Inst_VOP3__V_CMPX_O_F32()
Definition vop3_cmp.cc:2417
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F32::Inst_VOP3__V_CMPX_O_F32
Inst_VOP3__V_CMPX_O_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2408
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2425
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F64::~Inst_VOP3__V_CMPX_O_F64
~Inst_VOP3__V_CMPX_O_F64()
Definition vop3_cmp.cc:3996
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4004
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F64::Inst_VOP3__V_CMPX_O_F64
Inst_VOP3__V_CMPX_O_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3987
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F16::Inst_VOP3__V_CMPX_TRU_F16
Inst_VOP3__V_CMPX_TRU_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1263
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1279
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F16::~Inst_VOP3__V_CMPX_TRU_F16
~Inst_VOP3__V_CMPX_TRU_F16()
Definition vop3_cmp.cc:1272
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F32::~Inst_VOP3__V_CMPX_TRU_F32
~Inst_VOP3__V_CMPX_TRU_F32()
Definition vop3_cmp.cc:2718
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F32::Inst_VOP3__V_CMPX_TRU_F32
Inst_VOP3__V_CMPX_TRU_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2709
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2725
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4480
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F64::Inst_VOP3__V_CMPX_TRU_F64
Inst_VOP3__V_CMPX_TRU_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:4464
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F64::~Inst_VOP3__V_CMPX_TRU_F64
~Inst_VOP3__V_CMPX_TRU_F64()
Definition vop3_cmp.cc:4473
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I16::~Inst_VOP3__V_CMPX_T_I16
~Inst_VOP3__V_CMPX_T_I16()
Definition vop3_cmp.cc:5451
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5458
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I16::Inst_VOP3__V_CMPX_T_I16
Inst_VOP3__V_CMPX_T_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5443
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I32::Inst_VOP3__V_CMPX_T_I32
Inst_VOP3__V_CMPX_T_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6759
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I32::~Inst_VOP3__V_CMPX_T_I32
~Inst_VOP3__V_CMPX_T_I32()
Definition vop3_cmp.cc:6767
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6774
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:8090
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I64::Inst_VOP3__V_CMPX_T_I64
Inst_VOP3__V_CMPX_T_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:8075
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I64::~Inst_VOP3__V_CMPX_T_I64
~Inst_VOP3__V_CMPX_T_I64()
Definition vop3_cmp.cc:8083
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5796
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U16::~Inst_VOP3__V_CMPX_T_U16
~Inst_VOP3__V_CMPX_T_U16()
Definition vop3_cmp.cc:5789
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U16::Inst_VOP3__V_CMPX_T_U16
Inst_VOP3__V_CMPX_T_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5781
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7112
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U32::~Inst_VOP3__V_CMPX_T_U32
~Inst_VOP3__V_CMPX_T_U32()
Definition vop3_cmp.cc:7105
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U32::Inst_VOP3__V_CMPX_T_U32
Inst_VOP3__V_CMPX_T_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:7097
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U64::Inst_VOP3__V_CMPX_T_U64
Inst_VOP3__V_CMPX_T_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:8413
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:8428
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U64::~Inst_VOP3__V_CMPX_T_U64
~Inst_VOP3__V_CMPX_T_U64()
Definition vop3_cmp.cc:8421
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F16::~Inst_VOP3__V_CMPX_U_F16
~Inst_VOP3__V_CMPX_U_F16()
Definition vop3_cmp.cc:1117
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1125
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F16::Inst_VOP3__V_CMPX_U_F16
Inst_VOP3__V_CMPX_U_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:1108
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F32::Inst_VOP3__V_CMPX_U_F32
Inst_VOP3__V_CMPX_U_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2447
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2464
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F32::~Inst_VOP3__V_CMPX_U_F32
~Inst_VOP3__V_CMPX_U_F32()
Definition vop3_cmp.cc:2456
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F64::Inst_VOP3__V_CMPX_U_F64
Inst_VOP3__V_CMPX_U_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:4048
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F64::~Inst_VOP3__V_CMPX_U_F64
~Inst_VOP3__V_CMPX_U_F64()
Definition vop3_cmp.cc:4057
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4065
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F16::~Inst_VOP3__V_CMP_CLASS_F16
~Inst_VOP3__V_CMP_CLASS_F16()
Definition vop3_cmp.cc:520
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F16::Inst_VOP3__V_CMP_CLASS_F16
Inst_VOP3__V_CMP_CLASS_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:512
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:539
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F32::~Inst_VOP3__V_CMP_CLASS_F32
~Inst_VOP3__V_CMP_CLASS_F32()
Definition vop3_cmp.cc:50
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F32::Inst_VOP3__V_CMP_CLASS_F32
Inst_VOP3__V_CMP_CLASS_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:42
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:69
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F64::~Inst_VOP3__V_CMP_CLASS_F64
~Inst_VOP3__V_CMP_CLASS_F64()
Definition vop3_cmp.cc:285
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:304
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F64::Inst_VOP3__V_CMP_CLASS_F64
Inst_VOP3__V_CMP_CLASS_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:277
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F16::~Inst_VOP3__V_CMP_EQ_F16
~Inst_VOP3__V_CMP_EQ_F16()
Definition vop3_cmp.cc:629
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F16::Inst_VOP3__V_CMP_EQ_F16
Inst_VOP3__V_CMP_EQ_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:621
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:636
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F32::Inst_VOP3__V_CMP_EQ_F32
Inst_VOP3__V_CMP_EQ_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1381
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F32::~Inst_VOP3__V_CMP_EQ_F32
~Inst_VOP3__V_CMP_EQ_F32()
Definition vop3_cmp.cc:1389
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1396
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2842
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F64::Inst_VOP3__V_CMP_EQ_F64
Inst_VOP3__V_CMP_EQ_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:2827
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F64::~Inst_VOP3__V_CMP_EQ_F64
~Inst_VOP3__V_CMP_EQ_F64()
Definition vop3_cmp.cc:2835
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I16::Inst_VOP3__V_CMP_EQ_I16
Inst_VOP3__V_CMP_EQ_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4568
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4582
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I16::~Inst_VOP3__V_CMP_EQ_I16
~Inst_VOP3__V_CMP_EQ_I16()
Definition vop3_cmp.cc:4575
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5898
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I32::~Inst_VOP3__V_CMP_EQ_I32
~Inst_VOP3__V_CMP_EQ_I32()
Definition vop3_cmp.cc:5891
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I32::Inst_VOP3__V_CMP_EQ_I32
Inst_VOP3__V_CMP_EQ_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:5884
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7214
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I64::~Inst_VOP3__V_CMP_EQ_I64
~Inst_VOP3__V_CMP_EQ_I64()
Definition vop3_cmp.cc:7207
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I64::Inst_VOP3__V_CMP_EQ_I64
Inst_VOP3__V_CMP_EQ_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7200
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U16::Inst_VOP3__V_CMP_EQ_U16
Inst_VOP3__V_CMP_EQ_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4888
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4902
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U16::~Inst_VOP3__V_CMP_EQ_U16
~Inst_VOP3__V_CMP_EQ_U16()
Definition vop3_cmp.cc:4895
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U32::Inst_VOP3__V_CMP_EQ_U32
Inst_VOP3__V_CMP_EQ_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6204
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U32::~Inst_VOP3__V_CMP_EQ_U32
~Inst_VOP3__V_CMP_EQ_U32()
Definition vop3_cmp.cc:6211
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6218
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U64::Inst_VOP3__V_CMP_EQ_U64
Inst_VOP3__V_CMP_EQ_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7520
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7534
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U64::~Inst_VOP3__V_CMP_EQ_U64
~Inst_VOP3__V_CMP_EQ_U64()
Definition vop3_cmp.cc:7527
gem5::VegaISA::Inst_VOP3__V_CMP_F_F16::~Inst_VOP3__V_CMP_F_F16
~Inst_VOP3__V_CMP_F_F16()
Definition vop3_cmp.cc:587
gem5::VegaISA::Inst_VOP3__V_CMP_F_F16::Inst_VOP3__V_CMP_F_F16
Inst_VOP3__V_CMP_F_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:580
gem5::VegaISA::Inst_VOP3__V_CMP_F_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:594
gem5::VegaISA::Inst_VOP3__V_CMP_F_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1309
gem5::VegaISA::Inst_VOP3__V_CMP_F_F32::Inst_VOP3__V_CMP_F_F32
Inst_VOP3__V_CMP_F_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1295
gem5::VegaISA::Inst_VOP3__V_CMP_F_F32::~Inst_VOP3__V_CMP_F_F32
~Inst_VOP3__V_CMP_F_F32()
Definition vop3_cmp.cc:1302
gem5::VegaISA::Inst_VOP3__V_CMP_F_F64::~Inst_VOP3__V_CMP_F_F64
~Inst_VOP3__V_CMP_F_F64()
Definition vop3_cmp.cc:2748
gem5::VegaISA::Inst_VOP3__V_CMP_F_F64::Inst_VOP3__V_CMP_F_F64
Inst_VOP3__V_CMP_F_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:2741
gem5::VegaISA::Inst_VOP3__V_CMP_F_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2755
gem5::VegaISA::Inst_VOP3__V_CMP_F_I16::~Inst_VOP3__V_CMP_F_I16
~Inst_VOP3__V_CMP_F_I16()
Definition vop3_cmp.cc:4502
gem5::VegaISA::Inst_VOP3__V_CMP_F_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4509
gem5::VegaISA::Inst_VOP3__V_CMP_F_I16::Inst_VOP3__V_CMP_F_I16
Inst_VOP3__V_CMP_F_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4496
gem5::VegaISA::Inst_VOP3__V_CMP_F_I32::Inst_VOP3__V_CMP_F_I32
Inst_VOP3__V_CMP_F_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:5812
gem5::VegaISA::Inst_VOP3__V_CMP_F_I32::~Inst_VOP3__V_CMP_F_I32
~Inst_VOP3__V_CMP_F_I32()
Definition vop3_cmp.cc:5818
gem5::VegaISA::Inst_VOP3__V_CMP_F_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5825
gem5::VegaISA::Inst_VOP3__V_CMP_F_I64::Inst_VOP3__V_CMP_F_I64
Inst_VOP3__V_CMP_F_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7128
gem5::VegaISA::Inst_VOP3__V_CMP_F_I64::~Inst_VOP3__V_CMP_F_I64
~Inst_VOP3__V_CMP_F_I64()
Definition vop3_cmp.cc:7134
gem5::VegaISA::Inst_VOP3__V_CMP_F_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7141
gem5::VegaISA::Inst_VOP3__V_CMP_F_U16::~Inst_VOP3__V_CMP_F_U16
~Inst_VOP3__V_CMP_F_U16()
Definition vop3_cmp.cc:4822
gem5::VegaISA::Inst_VOP3__V_CMP_F_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4829
gem5::VegaISA::Inst_VOP3__V_CMP_F_U16::Inst_VOP3__V_CMP_F_U16
Inst_VOP3__V_CMP_F_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4816
gem5::VegaISA::Inst_VOP3__V_CMP_F_U32::Inst_VOP3__V_CMP_F_U32
Inst_VOP3__V_CMP_F_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6132
gem5::VegaISA::Inst_VOP3__V_CMP_F_U32::~Inst_VOP3__V_CMP_F_U32
~Inst_VOP3__V_CMP_F_U32()
Definition vop3_cmp.cc:6138
gem5::VegaISA::Inst_VOP3__V_CMP_F_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6145
gem5::VegaISA::Inst_VOP3__V_CMP_F_U64::Inst_VOP3__V_CMP_F_U64
Inst_VOP3__V_CMP_F_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7448
gem5::VegaISA::Inst_VOP3__V_CMP_F_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7461
gem5::VegaISA::Inst_VOP3__V_CMP_F_U64::~Inst_VOP3__V_CMP_F_U64
~Inst_VOP3__V_CMP_F_U64()
Definition vop3_cmp.cc:7454
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F16::~Inst_VOP3__V_CMP_GE_F16
~Inst_VOP3__V_CMP_GE_F16()
Definition vop3_cmp.cc:713
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F16::Inst_VOP3__V_CMP_GE_F16
Inst_VOP3__V_CMP_GE_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:705
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:720
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1624
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F32::~Inst_VOP3__V_CMP_GE_F32
~Inst_VOP3__V_CMP_GE_F32()
Definition vop3_cmp.cc:1617
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F32::Inst_VOP3__V_CMP_GE_F32
Inst_VOP3__V_CMP_GE_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1609
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F64::~Inst_VOP3__V_CMP_GE_F64
~Inst_VOP3__V_CMP_GE_F64()
Definition vop3_cmp.cc:3064
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3071
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F64::Inst_VOP3__V_CMP_GE_F64
Inst_VOP3__V_CMP_GE_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3056
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I16::~Inst_VOP3__V_CMP_GE_I16
~Inst_VOP3__V_CMP_GE_I16()
Definition vop3_cmp.cc:4751
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4758
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I16::Inst_VOP3__V_CMP_GE_I16
Inst_VOP3__V_CMP_GE_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4744
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6074
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I32::Inst_VOP3__V_CMP_GE_I32
Inst_VOP3__V_CMP_GE_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6060
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I32::~Inst_VOP3__V_CMP_GE_I32
~Inst_VOP3__V_CMP_GE_I32()
Definition vop3_cmp.cc:6067
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I64::Inst_VOP3__V_CMP_GE_I64
Inst_VOP3__V_CMP_GE_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7376
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I64::~Inst_VOP3__V_CMP_GE_I64
~Inst_VOP3__V_CMP_GE_I64()
Definition vop3_cmp.cc:7383
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7390
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U16::Inst_VOP3__V_CMP_GE_U16
Inst_VOP3__V_CMP_GE_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5064
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5078
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U16::~Inst_VOP3__V_CMP_GE_U16
~Inst_VOP3__V_CMP_GE_U16()
Definition vop3_cmp.cc:5071
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U32::Inst_VOP3__V_CMP_GE_U32
Inst_VOP3__V_CMP_GE_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6380
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6394
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U32::~Inst_VOP3__V_CMP_GE_U32
~Inst_VOP3__V_CMP_GE_U32()
Definition vop3_cmp.cc:6387
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U64::Inst_VOP3__V_CMP_GE_U64
Inst_VOP3__V_CMP_GE_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7696
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U64::~Inst_VOP3__V_CMP_GE_U64
~Inst_VOP3__V_CMP_GE_U64()
Definition vop3_cmp.cc:7703
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7710
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:678
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F16::~Inst_VOP3__V_CMP_GT_F16
~Inst_VOP3__V_CMP_GT_F16()
Definition vop3_cmp.cc:671
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F16::Inst_VOP3__V_CMP_GT_F16
Inst_VOP3__V_CMP_GT_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:663
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F32::Inst_VOP3__V_CMP_GT_F32
Inst_VOP3__V_CMP_GT_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1495
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1510
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F32::~Inst_VOP3__V_CMP_GT_F32
~Inst_VOP3__V_CMP_GT_F32()
Definition vop3_cmp.cc:1503
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F64::~Inst_VOP3__V_CMP_GT_F64
~Inst_VOP3__V_CMP_GT_F64()
Definition vop3_cmp.cc:2949
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2956
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F64::Inst_VOP3__V_CMP_GT_F64
Inst_VOP3__V_CMP_GT_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:2941
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I16::~Inst_VOP3__V_CMP_GT_I16
~Inst_VOP3__V_CMP_GT_I16()
Definition vop3_cmp.cc:4663
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4670
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I16::Inst_VOP3__V_CMP_GT_I16
Inst_VOP3__V_CMP_GT_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4656
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I32::~Inst_VOP3__V_CMP_GT_I32
~Inst_VOP3__V_CMP_GT_I32()
Definition vop3_cmp.cc:5979
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5986
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I32::Inst_VOP3__V_CMP_GT_I32
Inst_VOP3__V_CMP_GT_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:5972
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7302
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I64::Inst_VOP3__V_CMP_GT_I64
Inst_VOP3__V_CMP_GT_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7288
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I64::~Inst_VOP3__V_CMP_GT_I64
~Inst_VOP3__V_CMP_GT_I64()
Definition vop3_cmp.cc:7295
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U16::~Inst_VOP3__V_CMP_GT_U16
~Inst_VOP3__V_CMP_GT_U16()
Definition vop3_cmp.cc:4983
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4990
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U16::Inst_VOP3__V_CMP_GT_U16
Inst_VOP3__V_CMP_GT_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4976
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6306
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U32::~Inst_VOP3__V_CMP_GT_U32
~Inst_VOP3__V_CMP_GT_U32()
Definition vop3_cmp.cc:6299
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U32::Inst_VOP3__V_CMP_GT_U32
Inst_VOP3__V_CMP_GT_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6292
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7622
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U64::Inst_VOP3__V_CMP_GT_U64
Inst_VOP3__V_CMP_GT_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7608
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U64::~Inst_VOP3__V_CMP_GT_U64
~Inst_VOP3__V_CMP_GT_U64()
Definition vop3_cmp.cc:7615
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F16::~Inst_VOP3__V_CMP_LE_F16
~Inst_VOP3__V_CMP_LE_F16()
Definition vop3_cmp.cc:650
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F16::Inst_VOP3__V_CMP_LE_F16
Inst_VOP3__V_CMP_LE_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:642
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:657
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F32::~Inst_VOP3__V_CMP_LE_F32
~Inst_VOP3__V_CMP_LE_F32()
Definition vop3_cmp.cc:1446
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F32::Inst_VOP3__V_CMP_LE_F32
Inst_VOP3__V_CMP_LE_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1438
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1453
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F64::~Inst_VOP3__V_CMP_LE_F64
~Inst_VOP3__V_CMP_LE_F64()
Definition vop3_cmp.cc:2892
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F64::Inst_VOP3__V_CMP_LE_F64
Inst_VOP3__V_CMP_LE_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:2884
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2899
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4626
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I16::~Inst_VOP3__V_CMP_LE_I16
~Inst_VOP3__V_CMP_LE_I16()
Definition vop3_cmp.cc:4619
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I16::Inst_VOP3__V_CMP_LE_I16
Inst_VOP3__V_CMP_LE_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4612
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5942
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I32::~Inst_VOP3__V_CMP_LE_I32
~Inst_VOP3__V_CMP_LE_I32()
Definition vop3_cmp.cc:5935
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I32::Inst_VOP3__V_CMP_LE_I32
Inst_VOP3__V_CMP_LE_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:5928
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I64::~Inst_VOP3__V_CMP_LE_I64
~Inst_VOP3__V_CMP_LE_I64()
Definition vop3_cmp.cc:7251
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I64::Inst_VOP3__V_CMP_LE_I64
Inst_VOP3__V_CMP_LE_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7244
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7258
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4946
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U16::Inst_VOP3__V_CMP_LE_U16
Inst_VOP3__V_CMP_LE_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4932
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U16::~Inst_VOP3__V_CMP_LE_U16
~Inst_VOP3__V_CMP_LE_U16()
Definition vop3_cmp.cc:4939
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U32::~Inst_VOP3__V_CMP_LE_U32
~Inst_VOP3__V_CMP_LE_U32()
Definition vop3_cmp.cc:6255
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U32::Inst_VOP3__V_CMP_LE_U32
Inst_VOP3__V_CMP_LE_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6248
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6262
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U64::~Inst_VOP3__V_CMP_LE_U64
~Inst_VOP3__V_CMP_LE_U64()
Definition vop3_cmp.cc:7571
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U64::Inst_VOP3__V_CMP_LE_U64
Inst_VOP3__V_CMP_LE_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7564
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7578
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F16::~Inst_VOP3__V_CMP_LG_F16
~Inst_VOP3__V_CMP_LG_F16()
Definition vop3_cmp.cc:692
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:699
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F16::Inst_VOP3__V_CMP_LG_F16
Inst_VOP3__V_CMP_LG_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:684
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F32::~Inst_VOP3__V_CMP_LG_F32
~Inst_VOP3__V_CMP_LG_F32()
Definition vop3_cmp.cc:1560
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1567
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F32::Inst_VOP3__V_CMP_LG_F32
Inst_VOP3__V_CMP_LG_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1552
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F64::~Inst_VOP3__V_CMP_LG_F64
~Inst_VOP3__V_CMP_LG_F64()
Definition vop3_cmp.cc:3006
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F64::Inst_VOP3__V_CMP_LG_F64
Inst_VOP3__V_CMP_LG_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:2998
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3013
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F16::~Inst_VOP3__V_CMP_LT_F16
~Inst_VOP3__V_CMP_LT_F16()
Definition vop3_cmp.cc:608
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:615
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F16::Inst_VOP3__V_CMP_LT_F16
Inst_VOP3__V_CMP_LT_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:600
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F32::~Inst_VOP3__V_CMP_LT_F32
~Inst_VOP3__V_CMP_LT_F32()
Definition vop3_cmp.cc:1332
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F32::Inst_VOP3__V_CMP_LT_F32
Inst_VOP3__V_CMP_LT_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1324
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1339
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F64::~Inst_VOP3__V_CMP_LT_F64
~Inst_VOP3__V_CMP_LT_F64()
Definition vop3_cmp.cc:2778
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2785
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F64::Inst_VOP3__V_CMP_LT_F64
Inst_VOP3__V_CMP_LT_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:2770
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4538
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I16::~Inst_VOP3__V_CMP_LT_I16
~Inst_VOP3__V_CMP_LT_I16()
Definition vop3_cmp.cc:4531
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I16::Inst_VOP3__V_CMP_LT_I16
Inst_VOP3__V_CMP_LT_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4524
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I32::~Inst_VOP3__V_CMP_LT_I32
~Inst_VOP3__V_CMP_LT_I32()
Definition vop3_cmp.cc:5847
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I32::Inst_VOP3__V_CMP_LT_I32
Inst_VOP3__V_CMP_LT_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:5840
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5854
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I64::Inst_VOP3__V_CMP_LT_I64
Inst_VOP3__V_CMP_LT_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7156
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I64::~Inst_VOP3__V_CMP_LT_I64
~Inst_VOP3__V_CMP_LT_I64()
Definition vop3_cmp.cc:7163
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7170
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U16::Inst_VOP3__V_CMP_LT_U16
Inst_VOP3__V_CMP_LT_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4844
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U16::~Inst_VOP3__V_CMP_LT_U16
~Inst_VOP3__V_CMP_LT_U16()
Definition vop3_cmp.cc:4851
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4858
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6174
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U32::~Inst_VOP3__V_CMP_LT_U32
~Inst_VOP3__V_CMP_LT_U32()
Definition vop3_cmp.cc:6167
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U32::Inst_VOP3__V_CMP_LT_U32
Inst_VOP3__V_CMP_LT_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6160
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U64::Inst_VOP3__V_CMP_LT_U64
Inst_VOP3__V_CMP_LT_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7476
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7490
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U64::~Inst_VOP3__V_CMP_LT_U64
~Inst_VOP3__V_CMP_LT_U64()
Definition vop3_cmp.cc:7483
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:865
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F16::~Inst_VOP3__V_CMP_NEQ_F16
~Inst_VOP3__V_CMP_NEQ_F16()
Definition vop3_cmp.cc:858
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F16::Inst_VOP3__V_CMP_NEQ_F16
Inst_VOP3__V_CMP_NEQ_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:850
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F32::Inst_VOP3__V_CMP_NEQ_F32
Inst_VOP3__V_CMP_NEQ_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2009
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F32::~Inst_VOP3__V_CMP_NEQ_F32
~Inst_VOP3__V_CMP_NEQ_F32()
Definition vop3_cmp.cc:2017
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2024
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F64::~Inst_VOP3__V_CMP_NEQ_F64
~Inst_VOP3__V_CMP_NEQ_F64()
Definition vop3_cmp.cc:3464
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F64::Inst_VOP3__V_CMP_NEQ_F64
Inst_VOP3__V_CMP_NEQ_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3456
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3471
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I16::Inst_VOP3__V_CMP_NE_I16
Inst_VOP3__V_CMP_NE_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4700
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4714
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I16::~Inst_VOP3__V_CMP_NE_I16
~Inst_VOP3__V_CMP_NE_I16()
Definition vop3_cmp.cc:4707
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6030
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I32::Inst_VOP3__V_CMP_NE_I32
Inst_VOP3__V_CMP_NE_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6016
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I32::~Inst_VOP3__V_CMP_NE_I32
~Inst_VOP3__V_CMP_NE_I32()
Definition vop3_cmp.cc:6023
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I64::~Inst_VOP3__V_CMP_NE_I64
~Inst_VOP3__V_CMP_NE_I64()
Definition vop3_cmp.cc:7339
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7346
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I64::Inst_VOP3__V_CMP_NE_I64
Inst_VOP3__V_CMP_NE_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7332
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U16::~Inst_VOP3__V_CMP_NE_U16
~Inst_VOP3__V_CMP_NE_U16()
Definition vop3_cmp.cc:5027
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U16::Inst_VOP3__V_CMP_NE_U16
Inst_VOP3__V_CMP_NE_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5020
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5034
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6350
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U32::~Inst_VOP3__V_CMP_NE_U32
~Inst_VOP3__V_CMP_NE_U32()
Definition vop3_cmp.cc:6343
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U32::Inst_VOP3__V_CMP_NE_U32
Inst_VOP3__V_CMP_NE_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6336
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7666
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U64::Inst_VOP3__V_CMP_NE_U64
Inst_VOP3__V_CMP_NE_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7652
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U64::~Inst_VOP3__V_CMP_NE_U64
~Inst_VOP3__V_CMP_NE_U64()
Definition vop3_cmp.cc:7659
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:781
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F16::Inst_VOP3__V_CMP_NGE_F16
Inst_VOP3__V_CMP_NGE_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:766
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F16::~Inst_VOP3__V_CMP_NGE_F16
~Inst_VOP3__V_CMP_NGE_F16()
Definition vop3_cmp.cc:774
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1795
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F32::~Inst_VOP3__V_CMP_NGE_F32
~Inst_VOP3__V_CMP_NGE_F32()
Definition vop3_cmp.cc:1788
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F32::Inst_VOP3__V_CMP_NGE_F32
Inst_VOP3__V_CMP_NGE_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1780
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3242
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F64::Inst_VOP3__V_CMP_NGE_F64
Inst_VOP3__V_CMP_NGE_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3227
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F64::~Inst_VOP3__V_CMP_NGE_F64
~Inst_VOP3__V_CMP_NGE_F64()
Definition vop3_cmp.cc:3235
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:823
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F16::~Inst_VOP3__V_CMP_NGT_F16
~Inst_VOP3__V_CMP_NGT_F16()
Definition vop3_cmp.cc:816
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F16::Inst_VOP3__V_CMP_NGT_F16
Inst_VOP3__V_CMP_NGT_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:808
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1910
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F32::~Inst_VOP3__V_CMP_NGT_F32
~Inst_VOP3__V_CMP_NGT_F32()
Definition vop3_cmp.cc:1903
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F32::Inst_VOP3__V_CMP_NGT_F32
Inst_VOP3__V_CMP_NGT_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1895
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F64::Inst_VOP3__V_CMP_NGT_F64
Inst_VOP3__V_CMP_NGT_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3342
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F64::~Inst_VOP3__V_CMP_NGT_F64
~Inst_VOP3__V_CMP_NGT_F64()
Definition vop3_cmp.cc:3350
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3357
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F16::Inst_VOP3__V_CMP_NLE_F16
Inst_VOP3__V_CMP_NLE_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:829
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:844
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F16::~Inst_VOP3__V_CMP_NLE_F16
~Inst_VOP3__V_CMP_NLE_F16()
Definition vop3_cmp.cc:837
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F32::Inst_VOP3__V_CMP_NLE_F32
Inst_VOP3__V_CMP_NLE_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1952
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1967
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F32::~Inst_VOP3__V_CMP_NLE_F32
~Inst_VOP3__V_CMP_NLE_F32()
Definition vop3_cmp.cc:1960
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F64::Inst_VOP3__V_CMP_NLE_F64
Inst_VOP3__V_CMP_NLE_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3399
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3414
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F64::~Inst_VOP3__V_CMP_NLE_F64
~Inst_VOP3__V_CMP_NLE_F64()
Definition vop3_cmp.cc:3407
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:802
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F16::~Inst_VOP3__V_CMP_NLG_F16
~Inst_VOP3__V_CMP_NLG_F16()
Definition vop3_cmp.cc:795
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F16::Inst_VOP3__V_CMP_NLG_F16
Inst_VOP3__V_CMP_NLG_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:787
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F32::Inst_VOP3__V_CMP_NLG_F32
Inst_VOP3__V_CMP_NLG_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1837
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F32::~Inst_VOP3__V_CMP_NLG_F32
~Inst_VOP3__V_CMP_NLG_F32()
Definition vop3_cmp.cc:1845
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1852
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F64::Inst_VOP3__V_CMP_NLG_F64
Inst_VOP3__V_CMP_NLG_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3284
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F64::~Inst_VOP3__V_CMP_NLG_F64
~Inst_VOP3__V_CMP_NLG_F64()
Definition vop3_cmp.cc:3292
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3299
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:886
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F16::~Inst_VOP3__V_CMP_NLT_F16
~Inst_VOP3__V_CMP_NLT_F16()
Definition vop3_cmp.cc:879
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F16::Inst_VOP3__V_CMP_NLT_F16
Inst_VOP3__V_CMP_NLT_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:871
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2081
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F32::Inst_VOP3__V_CMP_NLT_F32
Inst_VOP3__V_CMP_NLT_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2066
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F32::~Inst_VOP3__V_CMP_NLT_F32
~Inst_VOP3__V_CMP_NLT_F32()
Definition vop3_cmp.cc:2074
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F64::Inst_VOP3__V_CMP_NLT_F64
Inst_VOP3__V_CMP_NLT_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3513
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F64::~Inst_VOP3__V_CMP_NLT_F64
~Inst_VOP3__V_CMP_NLT_F64()
Definition vop3_cmp.cc:3521
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3528
gem5::VegaISA::Inst_VOP3__V_CMP_O_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:740
gem5::VegaISA::Inst_VOP3__V_CMP_O_F16::~Inst_VOP3__V_CMP_O_F16
~Inst_VOP3__V_CMP_O_F16()
Definition vop3_cmp.cc:733
gem5::VegaISA::Inst_VOP3__V_CMP_O_F16::Inst_VOP3__V_CMP_O_F16
Inst_VOP3__V_CMP_O_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:726
gem5::VegaISA::Inst_VOP3__V_CMP_O_F32::Inst_VOP3__V_CMP_O_F32
Inst_VOP3__V_CMP_O_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1666
gem5::VegaISA::Inst_VOP3__V_CMP_O_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1680
gem5::VegaISA::Inst_VOP3__V_CMP_O_F32::~Inst_VOP3__V_CMP_O_F32
~Inst_VOP3__V_CMP_O_F32()
Definition vop3_cmp.cc:1673
gem5::VegaISA::Inst_VOP3__V_CMP_O_F64::Inst_VOP3__V_CMP_O_F64
Inst_VOP3__V_CMP_O_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3113
gem5::VegaISA::Inst_VOP3__V_CMP_O_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3127
gem5::VegaISA::Inst_VOP3__V_CMP_O_F64::~Inst_VOP3__V_CMP_O_F64
~Inst_VOP3__V_CMP_O_F64()
Definition vop3_cmp.cc:3120
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:907
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F16::Inst_VOP3__V_CMP_TRU_F16
Inst_VOP3__V_CMP_TRU_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:892
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F16::~Inst_VOP3__V_CMP_TRU_F16
~Inst_VOP3__V_CMP_TRU_F16()
Definition vop3_cmp.cc:900
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F32::~Inst_VOP3__V_CMP_TRU_F32
~Inst_VOP3__V_CMP_TRU_F32()
Definition vop3_cmp.cc:2131
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:2138
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F32::Inst_VOP3__V_CMP_TRU_F32
Inst_VOP3__V_CMP_TRU_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:2123
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F64::Inst_VOP3__V_CMP_TRU_F64
Inst_VOP3__V_CMP_TRU_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3570
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3585
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F64::~Inst_VOP3__V_CMP_TRU_F64
~Inst_VOP3__V_CMP_TRU_F64()
Definition vop3_cmp.cc:3578
gem5::VegaISA::Inst_VOP3__V_CMP_T_I16::~Inst_VOP3__V_CMP_T_I16
~Inst_VOP3__V_CMP_T_I16()
Definition vop3_cmp.cc:4794
gem5::VegaISA::Inst_VOP3__V_CMP_T_I16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:4801
gem5::VegaISA::Inst_VOP3__V_CMP_T_I16::Inst_VOP3__V_CMP_T_I16
Inst_VOP3__V_CMP_T_I16(InFmt_VOP3A *)
Definition vop3_cmp.cc:4788
gem5::VegaISA::Inst_VOP3__V_CMP_T_I32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6117
gem5::VegaISA::Inst_VOP3__V_CMP_T_I32::Inst_VOP3__V_CMP_T_I32
Inst_VOP3__V_CMP_T_I32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6104
gem5::VegaISA::Inst_VOP3__V_CMP_T_I32::~Inst_VOP3__V_CMP_T_I32
~Inst_VOP3__V_CMP_T_I32()
Definition vop3_cmp.cc:6110
gem5::VegaISA::Inst_VOP3__V_CMP_T_I64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7433
gem5::VegaISA::Inst_VOP3__V_CMP_T_I64::~Inst_VOP3__V_CMP_T_I64
~Inst_VOP3__V_CMP_T_I64()
Definition vop3_cmp.cc:7426
gem5::VegaISA::Inst_VOP3__V_CMP_T_I64::Inst_VOP3__V_CMP_T_I64
Inst_VOP3__V_CMP_T_I64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7420
gem5::VegaISA::Inst_VOP3__V_CMP_T_U16::~Inst_VOP3__V_CMP_T_U16
~Inst_VOP3__V_CMP_T_U16()
Definition vop3_cmp.cc:5114
gem5::VegaISA::Inst_VOP3__V_CMP_T_U16::Inst_VOP3__V_CMP_T_U16
Inst_VOP3__V_CMP_T_U16(InFmt_VOP3A *)
Definition vop3_cmp.cc:5108
gem5::VegaISA::Inst_VOP3__V_CMP_T_U16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:5121
gem5::VegaISA::Inst_VOP3__V_CMP_T_U32::~Inst_VOP3__V_CMP_T_U32
~Inst_VOP3__V_CMP_T_U32()
Definition vop3_cmp.cc:6430
gem5::VegaISA::Inst_VOP3__V_CMP_T_U32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:6437
gem5::VegaISA::Inst_VOP3__V_CMP_T_U32::Inst_VOP3__V_CMP_T_U32
Inst_VOP3__V_CMP_T_U32(InFmt_VOP3A *)
Definition vop3_cmp.cc:6424
gem5::VegaISA::Inst_VOP3__V_CMP_T_U64::~Inst_VOP3__V_CMP_T_U64
~Inst_VOP3__V_CMP_T_U64()
Definition vop3_cmp.cc:7746
gem5::VegaISA::Inst_VOP3__V_CMP_T_U64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:7753
gem5::VegaISA::Inst_VOP3__V_CMP_T_U64::Inst_VOP3__V_CMP_T_U64
Inst_VOP3__V_CMP_T_U64(InFmt_VOP3A *)
Definition vop3_cmp.cc:7740
gem5::VegaISA::Inst_VOP3__V_CMP_U_F16::~Inst_VOP3__V_CMP_U_F16
~Inst_VOP3__V_CMP_U_F16()
Definition vop3_cmp.cc:753
gem5::VegaISA::Inst_VOP3__V_CMP_U_F16::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:760
gem5::VegaISA::Inst_VOP3__V_CMP_U_F16::Inst_VOP3__V_CMP_U_F16
Inst_VOP3__V_CMP_U_F16(InFmt_VOP3A *)
Definition vop3_cmp.cc:746
gem5::VegaISA::Inst_VOP3__V_CMP_U_F32::~Inst_VOP3__V_CMP_U_F32
~Inst_VOP3__V_CMP_U_F32()
Definition vop3_cmp.cc:1730
gem5::VegaISA::Inst_VOP3__V_CMP_U_F32::Inst_VOP3__V_CMP_U_F32
Inst_VOP3__V_CMP_U_F32(InFmt_VOP3A *)
Definition vop3_cmp.cc:1723
gem5::VegaISA::Inst_VOP3__V_CMP_U_F32::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:1737
gem5::VegaISA::Inst_VOP3__V_CMP_U_F64::Inst_VOP3__V_CMP_U_F64
Inst_VOP3__V_CMP_U_F64(InFmt_VOP3A *)
Definition vop3_cmp.cc:3170
gem5::VegaISA::Inst_VOP3__V_CMP_U_F64::~Inst_VOP3__V_CMP_U_F64
~Inst_VOP3__V_CMP_U_F64()
Definition vop3_cmp.cc:3177
gem5::VegaISA::Inst_VOP3__V_CMP_U_F64::execute
void execute(GPUDynInstPtr) override
Definition vop3_cmp.cc:3184
gem5::VegaISA::ScalarOperand::rawData
std::enable_if< Condition, DataType >::type rawData() const
we store scalar data in a std::array, however if we need the full operand data we use this method to ...
Definition operand.hh:402
gem5::VegaISA::ScalarOperand::setBit
std::enable_if< Condition, void >::type setBit(int bit, int bit_val)
bit access to scalar data.
Definition operand.hh:507
gem5::VegaISA::VecOperand::readSrc
void readSrc()
certain vector operands can read from the vrf/srf or constants.
Definition operand.hh:132
gem5::Wavefront::execMask
VectorMask & execMask()
Definition wavefront.cc:1581
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition bitfield.hh:79
inst_util.hh
gem5::VegaISA
classes that represnt vector/scalar operands in VEGA ISA.
Definition faults.cc:39
gem5::VegaISA::ScalarOperandU64
ScalarOperand< ScalarRegU64, false > ScalarOperandU64
Definition operand.hh:804
gem5::VegaISA::ConstVecOperandF32
VecOperand< VecElemF32, true > ConstVecOperandF32
Definition operand.hh:846
gem5::VegaISA::ConstVecOperandF64
VecOperand< VecElemF64, true > ConstVecOperandF64
Definition operand.hh:849
gem5::VegaISA::ConstVecOperandI32
VecOperand< VecElemI32, true > ConstVecOperandI32
Definition operand.hh:845
gem5::VegaISA::ConstVecOperandU32
VecOperand< VecElemU32, true > ConstVecOperandU32
Definition operand.hh:844
gem5::VegaISA::ConstVecOperandI64
VecOperand< VecElemI64, true > ConstVecOperandI64
Definition operand.hh:848
gem5::VegaISA::ConstVecOperandU16
VecOperand< VecElemU16, true, 1 > ConstVecOperandU16
Definition operand.hh:842
gem5::VegaISA::NumVecElemPerVecReg
const int NumVecElemPerVecReg(64)
gem5::VegaISA::ConstVecOperandI16
VecOperand< VecElemI16, true, 1 > ConstVecOperandI16
Definition operand.hh:843
gem5::VegaISA::ConstVecOperandU64
VecOperand< VecElemU64, true > ConstVecOperandU64
Definition operand.hh:847
gem5
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
gem5::GPUDynInstPtr
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition misc.hh:49
std::isinf
constexpr bool isinf(gem5::AMDGPU::fp16_e5m10_info a)
Definition fp16_e5m10.hh:78
std::isnan
constexpr bool isnan(gem5::AMDGPU::fp16_e5m10_info a)
Definition fp16_e5m10.hh:83
std::isnormal
constexpr bool isnormal(gem5::AMDGPU::fp16_e5m10_info a)
Definition fp16_e5m10.hh:88
gem5::VegaISA::InFmt_VOP3A
Definition gpu_decoder.hh:1980
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