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gem5 [DEVELOP-FOR-25.0]
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#include "arch/generic/interrupts.hh"#include "arch/x86/faults.hh"#include "arch/x86/intmessage.hh"#include "arch/x86/regs/apic.hh"#include "base/bitfield.hh"#include "cpu/thread_context.hh"#include "dev/intpin.hh"#include "dev/io_device.hh"#include "dev/x86/intdev.hh"#include "params/X86LocalApic.hh"#include "sim/eventq.hh"Go to the source code of this file.
Classes | |
| class | gem5::X86ISA::Interrupts |
Namespaces | |
| namespace | gem5 |
| Copyright (c) 2024 Arm Limited All rights reserved. | |
| namespace | gem5::X86ISA |
| This is exposed globally, independent of the ISA. | |
Functions | |
| int | gem5::divideFromConf (uint32_t conf) |
| ApicRegIndex | gem5::X86ISA::decodeAddr (Addr paddr) |