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gem5 [DEVELOP-FOR-25.0]
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#include "arch/x86/x86_traits.hh"#include "base/bitunion.hh"#include "base/logging.hh"#include "cpu/reg_class.hh"#include "debug/IntRegs.hh"Go to the source code of this file.
Classes | |
| class | gem5::X86ISA::FlatIntRegClassOps |
| class | gem5::X86ISA::IntRegClassOps |
Namespaces | |
| namespace | gem5 |
| Copyright (c) 2024 Arm Limited All rights reserved. | |
| namespace | gem5::X86ISA |
| This is exposed globally, independent of the ISA. | |
| namespace | gem5::X86ISA::int_reg |
Functions | |
| gem5::X86ISA::BitUnion64 (X86IntReg) Bitfield< 63 | |
| gem5::X86ISA::EndBitUnion (X86IntReg) namespace int_reg | |
| static constexpr RegId | gem5::X86ISA::intRegMicro (int index) |
| static constexpr RegId | gem5::X86ISA::intRegFolded (RegIndex index, RegIndex foldBit) |