x86_cpu.cc File Reference

#include "arch/x86/kvm/x86_cpu.hh"
#include <linux/kvm.h>
#include <algorithm>
#include <cerrno>
#include <memory>
#include "arch/x86/cpuid.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/interrupts.hh"
#include "arch/x86/isa.hh"
#include "arch/x86/regs/float.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/msr.hh"
#include "arch/x86/utility.hh"
#include "base/bitunion.hh"
#include "base/compiler.hh"
#include "cpu/kvm/base.hh"
#include "debug/Drain.hh"
#include "debug/Kvm.hh"
#include "debug/KvmContext.hh"
#include "debug/KvmIO.hh"
#include "debug/KvmInt.hh"

Go to the source code of this file.

Classes
struct	gem5::FXSave

Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.

Macros
#define	MSR_TSC   0x10
#define	IO_PCI_CONF_ADDR   0xCF8
#define	IO_PCI_CONF_DATA_BASE   0xCFC
#define	SEG_SYS_TYPE_TSS_AVAILABLE   9
#define	SEG_SYS_TYPE_TSS_BUSY   11
#define	SEG_CS_TYPE_ACCESSED   9
#define	SEG_CS_TYPE_READ_ACCESSED   11
#define	SEG_TYPE_BIT_ACCESSED   1
#define	BIT(nr)
#define	FOREACH_IREG()
#define	FOREACH_SREG()
#define	FOREACH_DREG()
#define	FOREACH_SEGMENT()
#define	FOREACH_DTABLE()
#define	APPLY_IREG(kreg, mreg)
#define	APPLY_SREG(kreg, mreg)
#define	APPLY_SEGMENT(kreg, idx)
#define	APPLY_DTABLE(kreg, idx)
#define	APPLY_IREG(kreg, mreg)
#define	APPLY_SREG(kreg, mreg)
#define	APPLY_SEGMENT(kreg, idx)
#define	APPLY_DTABLE(kreg, idx)
#define	APPLY_SEGMENT(kreg, idx)
#define	APPLY_IREG(kreg, mreg)
#define	APPLY_SREG(kreg, mreg)
#define	APPLY_SEGMENT(kreg, idx)
#define	APPLY_DTABLE(kreg, idx)

Functions
	gem5::BitUnion64 (XStateBV) Bitfield< 0 > fpu
	gem5::EndBitUnion (XStateBV) struct XSaveHeader
template<typename Struct, typename Entry>
static auto	gem5::newVarStruct (size_t entries)
static void	gem5::dumpKvm (const struct kvm_regs &regs)
static void	gem5::dumpKvm (const char *reg_name, const struct kvm_segment &seg)
static void	gem5::dumpKvm (const char *reg_name, const struct kvm_dtable &dtable)
static void	gem5::dumpKvm (const struct kvm_sregs &sregs)
static void	gem5::dumpFpuSpec (const struct FXSave &xs)
static void	gem5::dumpFpuSpec (const struct kvm_fpu &fpu)
template<typename T>
static void	gem5::dumpFpuCommon (const T &fpu)
static void	gem5::dumpKvm (const struct kvm_fpu &fpu)
static void	gem5::dumpKvm (const struct kvm_xsave &xsave)
static void	gem5::dumpKvm (const struct kvm_msrs &msrs)
static void	gem5::dumpKvm (const struct kvm_xcrs &regs)
static void	gem5::dumpKvm (const struct kvm_vcpu_events &events)
static bool	gem5::isCanonicalAddress (uint64_t addr)
static void	gem5::checkSeg (const char *name, const int idx, const struct kvm_segment &seg, struct kvm_sregs sregs)
static void	gem5::setKvmSegmentReg (ThreadContext *tc, struct kvm_segment &kvm_seg, const int index)
static void	gem5::setKvmDTableReg (ThreadContext *tc, struct kvm_dtable &kvm_dtable, const int index)
static void	gem5::forceSegAccessed (struct kvm_segment &seg)
template<typename T>
static void	gem5::updateKvmStateFPUCommon (ThreadContext *tc, T &fpu)
void	gem5::setContextSegment (ThreadContext *tc, const struct kvm_segment &kvm_seg, const int index)
void	gem5::setContextSegment (ThreadContext *tc, const struct kvm_dtable &kvm_dtable, const int index)
template<typename T>
static void	gem5::updateThreadContextFPUCommon (ThreadContext *tc, const T &fpu)
static struct kvm_cpuid_entry2	gem5::makeKvmCpuid (uint32_t function, uint32_t index, CpuidResult &result, uint32_t flags=0)

Variables
Bitfield< 1 >	gem5::sse
Bitfield< 2 >	gem5::avx
Bitfield< 4, 3 >	gem5::mpx
Bitfield< 7, 5 >	gem5::avx512
Bitfield< 8 >	gem5::pt
Bitfield< 9 >	gem5::pkru
Bitfield< 10 >	gem5::pasid
Bitfield< 12, 11 >	gem5::cet
Bitfield< 13 >	gem5::hdc
Bitfield< 14 >	gem5::uintr
Bitfield< 15 >	gem5::lbr
Bitfield< 16 >	gem5::hwp
Bitfield< 18, 17 >	gem5::amx
Bitfield< 63, 19 >	gem5::reserved

Macro Definition Documentation

APPLY_DTABLE [1/3]

#define APPLY_DTABLE	(		kreg,
			idx )

Value:

    dumpKvm(# kreg, sregs.kreg);

APPLY_DTABLE [2/3]

#define APPLY_DTABLE	(		kreg,
			idx )

Value:

setKvmDTableReg(tc, sregs.kreg, idx)

APPLY_DTABLE [3/3]

#define APPLY_DTABLE	(		kreg,
			idx )

Value:

setContextSegment(tc, sregs.kreg, idx)

APPLY_IREG [1/3]

#define APPLY_IREG	(		kreg,
			mreg )

Value:

    inform("\t" # kreg ": 0x%llx\n", regs.kreg)

APPLY_IREG [2/3]

#define APPLY_IREG	(		kreg,
			mreg )

Value:

regs.kreg = tc->getReg(mreg)

APPLY_IREG [3/3]

#define APPLY_IREG	(		kreg,
			mreg )

Value:

tc->setReg(mreg, regs.kreg)

APPLY_SEGMENT [1/4]

#define APPLY_SEGMENT	(		kreg,
			idx )

Value:

    dumpKvm(# kreg, sregs.kreg);

APPLY_SEGMENT [2/4]

#define APPLY_SEGMENT	(		kreg,
			idx )

Value:

setKvmSegmentReg(tc, sregs.kreg, idx)

APPLY_SEGMENT [3/4]

#define APPLY_SEGMENT	(		kreg,
			idx )

Value:

        checkSeg(# kreg, idx + misc_reg::SegSelBase, sregs.kreg, sregs)

APPLY_SEGMENT [4/4]

#define APPLY_SEGMENT	(		kreg,
			idx )

Value:

setContextSegment(tc, sregs.kreg, idx)

APPLY_SREG [1/3]

#define APPLY_SREG	(		kreg,
			mreg )

Value:

    inform("\t" # kreg ": 0x%llx\n", sregs.kreg);

APPLY_SREG [2/3]

#define APPLY_SREG	(		kreg,
			mreg )

Value:

sregs.kreg = tc->readMiscRegNoEffect(mreg)

APPLY_SREG [3/3]

#define APPLY_SREG	(		kreg,
			mreg )

Value:

tc->setMiscRegNoEffect(mreg, sregs.kreg)

BIT

#define BIT

(

nr

)

Value:

(1UL << (nr))

Definition at line 81 of file x86_cpu.cc.

FOREACH_DREG

#define FOREACH_DREG

(

)

Value:

    do { \
        APPLY_DREG(db[0], misc_reg::Dr0); \
        APPLY_DREG(db[1], misc_reg::Dr1); \
        APPLY_DREG(db[2], misc_reg::Dr2); \
        APPLY_DREG(db[3], misc_reg::Dr3); \
        APPLY_DREG(dr6, misc_reg::Dr6); \
        APPLY_DREG(dr7, misc_reg::Dr7); \
    } while (0)

Definition at line 178 of file x86_cpu.cc.

FOREACH_DTABLE

#define FOREACH_DTABLE

(

)

Value:

    do { \
        APPLY_DTABLE(gdt, misc_reg::Tsg - misc_reg::SegSelBase); \
        APPLY_DTABLE(idt, misc_reg::Idtr - misc_reg::SegSelBase); \
    } while (0)

Definition at line 200 of file x86_cpu.cc.

Referenced by gem5::dumpKvm(), gem5::X86KvmCPU::updateKvmStateSRegs(), and gem5::X86KvmCPU::updateThreadContextSRegs().

FOREACH_IREG

#define FOREACH_IREG

(

)

Value:

    do { \
        APPLY_IREG(rax, int_reg::Rax); \
        APPLY_IREG(rbx, int_reg::Rbx); \
        APPLY_IREG(rcx, int_reg::Rcx); \
        APPLY_IREG(rdx, int_reg::Rdx); \
        APPLY_IREG(rsi, int_reg::Rsi); \
        APPLY_IREG(rdi, int_reg::Rdi); \
        APPLY_IREG(rsp, int_reg::Rsp); \
        APPLY_IREG(rbp, int_reg::Rbp); \
        APPLY_IREG(r8, int_reg::R8); \
        APPLY_IREG(r9, int_reg::R9); \
        APPLY_IREG(r10, int_reg::R10); \
        APPLY_IREG(r11, int_reg::R11); \
        APPLY_IREG(r12, int_reg::R12); \
        APPLY_IREG(r13, int_reg::R13); \
        APPLY_IREG(r14, int_reg::R14); \
        APPLY_IREG(r15, int_reg::R15); \
    } while (0)

Definition at line 147 of file x86_cpu.cc.

Referenced by gem5::dumpKvm(), gem5::X86KvmCPU::updateKvmStateRegs(), and gem5::X86KvmCPU::updateThreadContextRegs().

FOREACH_SEGMENT

#define FOREACH_SEGMENT

(

)

Value:

    do { \
        APPLY_SEGMENT(cs, misc_reg::Cs - misc_reg::SegSelBase); \
        APPLY_SEGMENT(ds, misc_reg::Ds - misc_reg::SegSelBase); \
        APPLY_SEGMENT(es, misc_reg::Es - misc_reg::SegSelBase); \
        APPLY_SEGMENT(fs, misc_reg::Fs - misc_reg::SegSelBase); \
        APPLY_SEGMENT(gs, misc_reg::Gs - misc_reg::SegSelBase); \
        APPLY_SEGMENT(ss, misc_reg::Ss - misc_reg::SegSelBase); \
        APPLY_SEGMENT(tr, misc_reg::Tr - misc_reg::SegSelBase); \
        APPLY_SEGMENT(ldt, misc_reg::Tsl - misc_reg::SegSelBase); \
    } while (0)

Definition at line 188 of file x86_cpu.cc.

Referenced by gem5::dumpKvm(), gem5::X86KvmCPU::updateKvmStateSRegs(), and gem5::X86KvmCPU::updateThreadContextSRegs().

FOREACH_SREG

#define FOREACH_SREG

(

)

Value:

    do { \
        APPLY_SREG(cr0, misc_reg::Cr0); \
        APPLY_SREG(cr2, misc_reg::Cr2); \
        APPLY_SREG(cr3, misc_reg::Cr3); \
        APPLY_SREG(cr4, misc_reg::Cr4); \
        APPLY_SREG(cr8, misc_reg::Cr8); \
        APPLY_SREG(efer, misc_reg::Efer); \
        APPLY_SREG(apic_base, misc_reg::ApicBase); \
    } while (0)

Definition at line 167 of file x86_cpu.cc.

Referenced by gem5::dumpKvm(), gem5::X86KvmCPU::updateKvmStateSRegs(), and gem5::X86KvmCPU::updateThreadContextSRegs().

IO_PCI_CONF_ADDR

#define IO_PCI_CONF_ADDR   0xCF8

Definition at line 61 of file x86_cpu.cc.

Referenced by gem5::X86KvmCPU::handleKvmExitIO().

IO_PCI_CONF_DATA_BASE

#define IO_PCI_CONF_DATA_BASE   0xCFC

Definition at line 62 of file x86_cpu.cc.

Referenced by gem5::X86KvmCPU::handleKvmExitIO().

MSR_TSC

#define MSR_TSC   0x10

Definition at line 59 of file x86_cpu.cc.

Referenced by gem5::X86KvmCPU::getHostCycles().

SEG_CS_TYPE_ACCESSED

#define SEG_CS_TYPE_ACCESSED   9

Definition at line 70 of file x86_cpu.cc.

Referenced by gem5::X86KvmCPU::updateKvmStateSRegs().

SEG_CS_TYPE_READ_ACCESSED

#define SEG_CS_TYPE_READ_ACCESSED   11

Definition at line 72 of file x86_cpu.cc.

Referenced by gem5::X86KvmCPU::updateKvmStateSRegs().

SEG_SYS_TYPE_TSS_AVAILABLE

#define SEG_SYS_TYPE_TSS_AVAILABLE   9

Definition at line 65 of file x86_cpu.cc.

Referenced by gem5::X86KvmCPU::updateKvmStateSRegs().

SEG_SYS_TYPE_TSS_BUSY

#define SEG_SYS_TYPE_TSS_BUSY   11

Definition at line 67 of file x86_cpu.cc.

Referenced by gem5::X86KvmCPU::updateKvmStateSRegs().

SEG_TYPE_BIT_ACCESSED

#define SEG_TYPE_BIT_ACCESSED   1

Definition at line 76 of file x86_cpu.cc.

Referenced by gem5::forceSegAccessed().