zcmp.cc

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#include "arch/riscv/insts/zcmp.hh"
 
#include <string>
 
#include "arch/riscv/regs/int.hh"
#include "arch/riscv/utility.hh"
 
namespace gem5
{
 
namespace RiscvISA
{
 
CmMacroInst::CmMacroInst(
    const char* mnem, ExtMachInst machInst, OpClass opClass)
    : RiscvMacroInst(mnem, machInst, opClass), rlist(machInst.rlist)
{
}
 
// Ref: https://github.com/riscv-software-src/riscv-isa-sim/blob/f7d0dba60/
//      riscv/decode.h#L168
uint64_t
CmMacroInst::stackAdj() const
{
    uint64_t stack_adj_base = 0;
    switch (machInst.rlist) {
      case 15:
        stack_adj_base += 16;
        [[fallthrough]];
      case 14:
        if (machInst.rv_type == RV64) {
            stack_adj_base += 16;
        }
        [[fallthrough]];
      case 13:
      case 12:
        stack_adj_base += 16;
        [[fallthrough]];
      case 11:
      case 10:
        if (machInst.rv_type == RV64) {
            stack_adj_base += 16;
        }
        [[fallthrough]];
      case 9:
      case 8:
        stack_adj_base += 16;
        [[fallthrough]];
      case 7:
      case 6:
        if (machInst.rv_type == RV64) {
            stack_adj_base += 16;
        }
        [[fallthrough]];
      case 5:
      case 4:
        stack_adj_base += 16;
        break;
    }
 
    return stack_adj_base + machInst.spimm * 16;
}
 
std::string
CmMacroInst::getRlistStr() const
{
    std::string s = "";
    switch (machInst.rlist) {
      case 15:
        s = csprintf("{%s, %s-%s}", registerName(ReturnAddrReg),
                     registerName(int_reg::S0),
                     registerName(PushPopRegList[0]));
        break;
      case 14:
      case 13:
      case 12:
      case 11:
      case 10:
      case 9:
      case 8:
      case 7:
      case 6:
        s = csprintf("{%s, %s-%s}", registerName(ReturnAddrReg),
                     registerName(int_reg::S0),
                     registerName(PushPopRegList[16-machInst.rlist]));
        break;
      case 5:
        s = csprintf("{%s, %s}", registerName(ReturnAddrReg),
                     registerName(int_reg::S0));
        break;
      case 4:
        s = csprintf("{%s}", registerName(ReturnAddrReg));
        break;
      default:
        break;
    }
 
    return s;
}
 
} // namespace RiscvISA
} // namespace gem5