faults.cc File Reference

#include "arch/arm/faults.hh"
#include "arch/arm/insts/static_inst.hh"
#include "arch/arm/interrupts.hh"
#include "arch/arm/isa.hh"
#include "arch/arm/regs/misc_accessors.hh"
#include "arch/arm/self_debug.hh"
#include "arch/arm/system.hh"
#include "arch/arm/utility.hh"
#include "base/compiler.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/Faults.hh"
#include "sim/full_system.hh"

Go to the source code of this file.

Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.
namespace	gem5::ArmISA

Functions
bool	gem5::ArmISA::getFaultVAddr (Fault fault, Addr &va)
	Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise.

Variables
const uint32_t	gem5::ArmISA::HighVecs = 0xFFFF0000
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< Reset >::vals ("Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, ExceptionClass::UNKNOWN)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< UndefinedInstruction >::vals ("Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, ExceptionClass::UNKNOWN)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< SupervisorCall >::vals ("Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 4, 2, 4, 2, true, false, false, ExceptionClass::SVC_TO_HYP)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< SecureMonitorCall >::vals ("Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 4, 4, 4, false, true, true, ExceptionClass::SMC_TO_HYP)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< HypervisorCall >::vals ("Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 4, 4, 4, 4, true, false, false, ExceptionClass::HVC)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< PrefetchAbort >::vals ("Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 4, 4, 0, 0, true, true, false, ExceptionClass::PREFETCH_ABORT_TO_HYP)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< DataAbort >::vals ("Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, ExceptionClass::DATA_ABORT_TO_HYP)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< VirtualDataAbort >::vals ("Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 8, 8, 0, 0, true, true, false, ExceptionClass::INVALID)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< HypervisorTrap >::vals ("Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 0, 0, 0, 0, false, false, false, ExceptionClass::UNKNOWN)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< SecureMonitorTrap >::vals ("Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON, 4, 2, 0, 0, false, false, false, ExceptionClass::UNKNOWN)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< Interrupt >::vals ("IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, ExceptionClass::UNKNOWN)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< VirtualInterrupt >::vals ("Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 4, 4, 0, 0, false, true, false, ExceptionClass::INVALID)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< FastInterrupt >::vals ("FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, ExceptionClass::UNKNOWN)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< VirtualFastInterrupt >::vals ("Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 4, 4, 0, 0, false, true, true, ExceptionClass::INVALID)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< IllegalInstSetStateFault >::vals ("Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 4, 2, 0, 0, true, false, false, ExceptionClass::ILLEGAL_INST)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< SupervisorTrap >::vals ("Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, false, false, false, ExceptionClass::UNKNOWN)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< PCAlignmentFault >::vals ("PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::PC_ALIGNMENT)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< SPAlignmentFault >::vals ("SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::STACK_PTR_ALIGNMENT)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< SystemError >::vals ("SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 0, 0, 0, 0, false, true, true, ExceptionClass::SERROR)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< SoftwareBreakpoint >::vals ("Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::SOFTWARE_BREAKPOINT)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< HardwareBreakpoint >::vals ("Hardware Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::HW_BREAKPOINT)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< Watchpoint >::vals ("Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::WATCHPOINT)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< SoftwareStepFault >::vals ("SoftwareStep", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 0, 0, 0, 0, true, false, false, ExceptionClass::SOFTWARE_STEP)
template<>
ArmFault::FaultVals	gem5::ArmISA::ArmFaultVals< ArmSev >::vals ("ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 0, 0, 0, 0, false, true, true, ExceptionClass::UNKNOWN)