pagetable.hh File Reference

#include <cstdint>
#include "arch/arm/page_size.hh"
#include "arch/arm/types.hh"
#include "arch/arm/utility.hh"
#include "arch/generic/mmu.hh"
#include "enums/TypeTLB.hh"
#include "enums/ArmLookupLevel.hh"
#include "mem/cache/replacement_policies/replaceable_entry.hh"
#include "mem/cache/tags/indexing_policies/base.hh"
#include "params/TLBIndexingPolicy.hh"
#include "params/TLBSetAssociative.hh"
#include "sim/serialize.hh"

Go to the source code of this file.

Classes
struct	gem5::ArmISA::PTE
struct	gem5::ArmISA::PageTableOps
struct	gem5::ArmISA::V7LPageTableOps
struct	gem5::ArmISA::V8PageTableOps4k
struct	gem5::ArmISA::V8PageTableOps16k
struct	gem5::ArmISA::V8PageTableOps64k
class	gem5::ArmISA::TLBTypes
struct	gem5::ArmISA::TLBTypes::KeyType
class	gem5::ArmISA::TLBSetAssociative
struct	gem5::ArmISA::TlbEntry

Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.
namespace	gem5::ArmISA

Typedefs
using	gem5::ArmISA::TLBIndexingPolicy = IndexingPolicyTemplate<TLBTypes>

Enumerations
enum	gem5::ArmISA::GrainSize { gem5::ArmISA::Grain4KB = 12 , gem5::ArmISA::Grain16KB = 14 , gem5::ArmISA::Grain64KB = 16 , gem5::ArmISA::ReservedGrain = 0 }

Functions
const PageTableOps *	gem5::ArmISA::getPageTableOps (GrainSize trans_granule)

Variables
const unsigned	gem5::ArmISA::MaxPhysAddrRange = 52