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gem5
v19.0.0.0
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#include <deque>#include <string>#include <unordered_set>#include <vector>#include "base/callback.hh"#include "base/statistics.hh"#include "enums/AddrMap.hh"#include "enums/MemSched.hh"#include "enums/PageManage.hh"#include "mem/drampower.hh"#include "mem/qos/mem_ctrl.hh"#include "mem/qport.hh"#include "params/DRAMCtrl.hh"#include "sim/eventq.hh"Go to the source code of this file.
Classes | |
| class | DRAMCtrl |
| The DRAM controller is a single-channel memory controller capturing the most important timing constraints associated with a contemporary DRAM. More... | |
| class | DRAMCtrl::MemoryPort |
| struct | DRAMCtrl::Command |
| Simple structure to hold the values needed to keep track of commands for DRAMPower. More... | |
| class | DRAMCtrl::Bank |
| A basic class to track the bank state, i.e. More... | |
| struct | DRAMCtrl::RankStats |
| class | DRAMCtrl::Rank |
| Rank class includes a vector of banks. More... | |
| class | DRAMCtrl::BurstHelper |
| A burst helper helps organize and manage a packet that is larger than the DRAM burst size. More... | |
| class | DRAMCtrl::DRAMPacket |
| A DRAM packet stores packets along with the timestamp of when the packet entered the queue, and also the decoded address. More... | |
| struct | DRAMCtrl::DRAMStats |
| All statistics that the model needs to capture. More... | |
DRAMCtrl declaration.
Definition in file dram_ctrl.hh.