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gem5
v19.0.0.0
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Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2. More...
#include "cpu/minor/buffers.hh"#include "cpu/minor/cpu.hh"#include "cpu/minor/pipe_data.hh"#include "cpu/base.hh"#include "mem/packet.hh"Go to the source code of this file.
Classes | |
| class | Minor::Fetch1 |
| A stage responsible for fetching "lines" from memory and passing them to Fetch2. More... | |
| class | Minor::Fetch1::IcachePort |
| Exposable fetch port. More... | |
| class | Minor::Fetch1::FetchRequest |
| Memory access queuing. More... | |
| struct | Minor::Fetch1::Fetch1ThreadInfo |
| Stage cycle-by-cycle state. More... | |
Namespaces | |
| Minor | |
| Minor contains all the definitions within the MinorCPU apart from the CPU class itself. | |
Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2.
Definition in file fetch1.hh.