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gem5
v19.0.0.0
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#include "arch/generic/vec_pred_reg.hh"#include "arch/generic/vec_reg.hh"#include "arch/power/generated/max_inst_regs.hh"#include "arch/power/miscregs.hh"#include "base/types.hh"Go to the source code of this file.
Namespaces | |
| PowerISA | |
Typedefs | |
| using | PowerISA::VecElem = ::DummyVecElem |
| using | PowerISA::VecReg = ::DummyVecReg |
| using | PowerISA::ConstVecReg = ::DummyConstVecReg |
| using | PowerISA::VecRegContainer = ::DummyVecRegContainer |
| using | PowerISA::VecPredReg = ::DummyVecPredReg |
| using | PowerISA::ConstVecPredReg = ::DummyConstVecPredReg |
| using | PowerISA::VecPredRegContainer = ::DummyVecPredRegContainer |
Enumerations | |
| enum | PowerISA::MiscIntRegNums { PowerISA::INTREG_CR = NumIntArchRegs, PowerISA::INTREG_XER, PowerISA::INTREG_LR, PowerISA::INTREG_CTR, PowerISA::INTREG_FPSCR, PowerISA::INTREG_RSV, PowerISA::INTREG_RSV_LEN, PowerISA::INTREG_RSV_ADDR } |