isa_traits.hh File Reference

#include "arch/riscv/types.hh"
#include "base/types.hh"
#include "cpu/static_inst_fwd.hh"

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Namespaces
	RiscvISA

Variables
const ByteOrder	RiscvISA::GuestByteOrder = LittleEndianByteOrder
const Addr	RiscvISA::PageShift = 12
const Addr	RiscvISA::PageBytes = ULL(1) << PageShift
const bool	RiscvISA::HasUnalignedMemAcc = true
const bool	RiscvISA::CurThreadInfoImplemented = false
const int	RiscvISA::CurThreadInfoReg = -1