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gem5
v20.1.0.5
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#include <list>#include <utility>#include "base/statistics.hh"#include "config/the_isa.hh"#include "cpu/timebuf.hh"#include "sim/probe/probe.hh"Go to the source code of this file.
Classes | |
| class | DefaultRename< Impl > |
| DefaultRename handles both single threaded and SMT rename. More... | |
| struct | DefaultRename< Impl >::RenameHistory |
| Holds the information for each destination register rename. More... | |
| struct | DefaultRename< Impl >::FreeEntries |
| Structures whose free entries impact the amount of instructions that can be renamed. More... | |
| struct | DefaultRename< Impl >::Stalls |
| Source of possible stalls. More... | |
| struct | DefaultRename< Impl >::RenameStats |