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gem5
v20.1.0.5
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#include <string>#include <vector>#include "arch/x86/regs/misc.hh"#include "arch/x86/regs/segment.hh"#include "base/types.hh"#include "cpu/thread_context.hh"#include "params/X86FsWorkload.hh"#include "sim/kernel_workload.hh"Go to the source code of this file.
Classes | |
| class | X86ISA::FsWorkload |
Namespaces | |
| X86ISA | |
| This is exposed globally, independent of the ISA. | |
| X86ISA::SMBios | |
| X86ISA::IntelMP | |
Functions | |
| void | X86ISA::installSegDesc (ThreadContext *tc, SegmentRegIndex seg, SegDescriptor desc, bool longmode) |
Variables | |
| const Addr | X86ISA::syscallCodeVirtAddr = 0xffff800000000000 |
| const Addr | X86ISA::GDTVirtAddr = 0xffff800000001000 |
| const Addr | X86ISA::IDTVirtAddr = 0xffff800000002000 |
| const Addr | X86ISA::TSSVirtAddr = 0xffff800000003000 |
| const Addr | X86ISA::TSSPhysAddr = 0x63000 |
| const Addr | X86ISA::ISTVirtAddr = 0xffff800000004000 |
| const Addr | X86ISA::PFHandlerVirtAddr = 0xffff800000005000 |
| const Addr | X86ISA::MMIORegionVirtAddr = 0xffffc90000000000 |
| const Addr | X86ISA::MMIORegionPhysAddr = 0xffff0000 |