Checker< Impl > Member List

This is the complete list of members for Checker< Impl >, including all inherited members.

_cacheLineSize	BaseCPU	protected
_cpuId	BaseCPU	protected
_dataRequestorId	BaseCPU	protected
_drainManager	Drainable	private
_drainState	Drainable	mutableprivate
_instRequestorId	BaseCPU	protected
_params	SimObject	protected
_pid	BaseCPU	protected
_socketId	BaseCPU	protected
_switchedOut	BaseCPU	protected
_taskId	BaseCPU	protected
activateContext(ThreadID thread_num)	BaseCPU	virtual
addressMonitor	BaseCPU	private
addStat(Stats::Info *info)	Stats::Group
addStatGroup(const char *name, Group *block)	Stats::Group
advancePC(const Fault &fault)	Checker< Impl >
amoMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override	CheckerCPU	inline
ExecContext::amoMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)	ExecContext	inlinevirtual
armMonitor(Addr address) override	CheckerCPU	inlinevirtual
BaseCPU::armMonitor(ThreadID tid, Addr address)	BaseCPU
BaseCPU(const Params &params, bool is_checker=false)	BaseCPU
baseStats	BaseCPU
cacheLineSize() const	BaseCPU	inline
changedPC	CheckerCPU
Checker(const Params &p)	Checker< Impl >	inline
CheckerCPU(const Params &p)	CheckerCPU
checkFlags(const RequestPtr &unverified_req, Addr vAddr, Addr pAddr, int flags)	CheckerCPU
checkInterrupts(ThreadID tid) const	BaseCPU	inline
clearInterrupt(ThreadID tid, int int_num, int index)	BaseCPU	inline
clearInterrupts(ThreadID tid)	BaseCPU	inline
clockDomain	Clocked	private
Clocked(ClockDomain &clk_domain)	Clocked	inlineprotected
Clocked(Clocked &)=delete	Clocked	protected
clockEdge(Cycles cycles=Cycles(0)) const	Clocked	inline
ClockedObject(const ClockedObjectParams &p)	ClockedObject
clockPeriod() const	Clocked	inline
clockPeriodUpdated()	Clocked	inlineprotectedvirtual
contextToThread(ContextID cid)	BaseCPU	inline
copyResult(const DynInstPtr &inst, const InstResult &mismatch_val, int start_idx)	Checker< Impl >
CPU_STATE_ON enum value	BaseCPU	protected
CPU_STATE_SLEEP enum value	BaseCPU	protected
CPU_STATE_WAKEUP enum value	BaseCPU	protected
cpuId() const	BaseCPU	inline
cpuList	BaseCPU	privatestatic
CPUState enum name	BaseCPU	protected
curCycle() const	Clocked	inline
curMacroStaticInst	CheckerCPU	protected
currentFunctionEnd	BaseCPU	private
currentFunctionStart	BaseCPU	private
currentSection()	Serializable	static
curStaticInst	CheckerCPU	protected
cycle	Clocked	mutableprivate
cyclesToTicks(Cycles c) const	Clocked	inline
dataRequestorId() const	BaseCPU	inline
dcachePort	CheckerCPU	protected
demapPage(Addr vaddr, uint64_t asn) override	CheckerCPU	inlinevirtual
deschedule(Event &event)	EventManager	inline
deschedule(Event *event)	EventManager	inline
deschedulePowerGatingEvent()	BaseCPU
dmDrain()	Drainable	private
dmDrainResume()	Drainable	private
drain() override	SimObject	inlinevirtual
Drainable()	Drainable	protected
drainResume()	Drainable	inlineprotectedvirtual
drainState() const	Drainable	inline
dumpAndExit(const DynInstPtr &inst)	Checker< Impl >	private
CheckerCPU::dumpAndExit()	CheckerCPU
dumpInsts()	Checker< Impl >	private
DynInstPtr typedef	Checker< Impl >	private
enableFunctionTrace()	BaseCPU	private
enterPwrGating()	BaseCPU	protected
enterPwrGatingEvent	BaseCPU	protected
EventManager(EventManager &em)	EventManager	inline
EventManager(EventManager *em)	EventManager	inline
EventManager(EventQueue *eq)	EventManager	inline
eventq	EventManager	protected
eventQueue() const	EventManager	inline
exitOnError	CheckerCPU
find(const char *name)	SimObject	static
findContext(ThreadContext *tc)	BaseCPU
flushTLBs()	BaseCPU
frequency() const	Clocked	inline
functionEntryTick	BaseCPU	private
functionTraceStream	BaseCPU	private
functionTracingEnabled	BaseCPU	private
genMemFragmentRequest(Addr frag_addr, int size, Request::Flags flags, const std::vector< bool > &byte_enable, int &frag_size, int &size_left) const	CheckerCPU
getAddrMonitor() override	CheckerCPU	inlinevirtual
getContext(int tn)	BaseCPU	inlinevirtual
getCpuAddrMonitor(ThreadID tid)	BaseCPU	inline
getCurrentInstCount(ThreadID tid)	BaseCPU
getDataPort() override	CheckerCPU	inlinevirtual
getHtmTransactionalDepth() const override	CheckerCPU	inlinevirtual
getHtmTransactionUid() const override	CheckerCPU	inlinevirtual
getInstPort() override	CheckerCPU	inlinevirtual
getInterruptController(ThreadID tid)	BaseCPU	inline
getMMUPtr()	CheckerCPU	inline
getPid() const	BaseCPU	inline
getPort(const std::string &if_name, PortID idx=InvalidPortID) override	BaseCPU	virtual
getProbeManager()	SimObject
getSendFunctional()	BaseCPU	inlinevirtual
getStatGroups() const	Stats::Group
getStats() const	Stats::Group
getTracer()	BaseCPU	inline
getWritableVecPredRegOperand(const StaticInst *si, int idx) override	CheckerCPU	inlinevirtual
getWritableVecRegOperand(const StaticInst *si, int idx) override	CheckerCPU	inlinevirtual
globalStats	BaseCPU	protectedstatic
Group()=delete	Stats::Group
Group(const Group &)=delete	Stats::Group
Group(Group *parent, const char *name=nullptr)	Stats::Group
haltContext(ThreadID thread_num)	BaseCPU	virtual
handleError(const DynInstPtr &inst)	Checker< Impl >	inlineprivate
CheckerCPU::handleError()	CheckerCPU	inline
handlePendingInt()	Checker< Impl >
icachePort	CheckerCPU	protected
inHtmTransactionalState() const override	CheckerCPU	inlinevirtual
init() override	CheckerCPU	virtual
initiateHtmCmd(Request::Flags flags) override	CheckerCPU	inlinevirtual
initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op)	ExecContext	inlinevirtual
initiateMemRead(Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)	ExecContext	inlinevirtual
initState()	SimObject	virtual
instAddr()	CheckerCPU	inline
instCnt	BaseCPU	protected
instCount()	BaseCPU	inline
instList	Checker< Impl >	private
InstListIt typedef	Checker< Impl >	private
instRequestorId() const	BaseCPU	inline
interrupts	BaseCPU	protected
invldPid	BaseCPU	static
loadState(CheckpointIn &cp)	SimObject	virtual
memInvalidate()	SimObject	inlinevirtual
memWriteback()	SimObject	inlinevirtual
mergedParent	Stats::Group	private
mergedStatGroups	Stats::Group	private
mergeStatGroup(Group *block)	Stats::Group
microPC()	CheckerCPU	inline
miscRegIdxs	CheckerCPU	protected
mmu	CheckerCPU	protected
mwait(PacketPtr pkt) override	CheckerCPU	inlinevirtual
BaseCPU::mwait(ThreadID tid, PacketPtr pkt)	BaseCPU
mwaitAtomic(ThreadContext *tc) override	CheckerCPU	inlinevirtual
BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)	BaseCPU
name() const	SimObject	inlinevirtual
newHtmTransactionUid() const override	CheckerCPU	inlinevirtual
newPCState	CheckerCPU
nextCycle() const	Clocked	inline
nextInstAddr()	CheckerCPU	inline
notifyFork()	Drainable	inlinevirtual
numContexts()	BaseCPU	inline
numInst	CheckerCPU	protected
numLoad	CheckerCPU
numSimulatedCPUs()	BaseCPU	inlinestatic
numSimulatedInsts()	BaseCPU	inlinestatic
numSimulatedOps()	BaseCPU	inlinestatic
numThreads	BaseCPU
SimObject::operator=(const Group &)=delete	Stats::Group
Clocked::operator=(Clocked &)=delete	Clocked	protected
PARAMS(CheckerCPU)	CheckerCPU
BaseCPU::PARAMS(BaseCPU)	BaseCPU
Params typedef	ClockedObject
params() const	SimObject	inline
path	Serializable	privatestatic
PCMask	BaseCPU	static
pcState() const override	CheckerCPU	inlinevirtual
pcState(const TheISA::PCState &val) override	CheckerCPU	inlinevirtual
pmuProbePoint(const char *name)	BaseCPU	protected
postInterrupt(ThreadID tid, int int_num, int index)	BaseCPU
powerGatingOnIdle	BaseCPU	protected
powerState	ClockedObject
ppActiveCycles	BaseCPU	protected
ppAllCycles	BaseCPU	protected
ppRetiredBranches	BaseCPU	protected
ppRetiredInsts	BaseCPU	protected
ppRetiredInstsPC	BaseCPU	protected
ppRetiredLoads	BaseCPU	protected
ppRetiredStores	BaseCPU	protected
ppSleeping	BaseCPU	protected
preDumpStats()	Stats::Group	virtual
previousCycle	BaseCPU	protected
previousState	BaseCPU	protected
probeInstCommit(const StaticInstPtr &inst, Addr pc)	BaseCPU	virtual
probeManager	SimObject	private
pwrGatingLatency	BaseCPU	protected
readCCRegOperand(const StaticInst *si, int idx) override	CheckerCPU	inlinevirtual
readFloatRegOperandBits(const StaticInst *si, int idx) override	CheckerCPU	inlinevirtual
readIntRegOperand(const StaticInst *si, int idx) override	CheckerCPU	inlinevirtual
readMem(Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable) override	CheckerCPU
ExecContext::readMem(Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable)	ExecContext	inlinevirtual
readMemAccPredicate() const override	CheckerCPU	inlinevirtual
readMiscReg(int misc_reg) override	CheckerCPU	inlinevirtual
readMiscRegNoEffect(int misc_reg) const	CheckerCPU	inline
readMiscRegOperand(const StaticInst *si, int idx) override	CheckerCPU	inlinevirtual
readPredicate() const override	CheckerCPU	inlinevirtual
readStCondFailures() const override	CheckerCPU	inlinevirtual
readVec16BitLaneOperand(const StaticInst *si, int idx) const override	CheckerCPU	inlinevirtual
readVec32BitLaneOperand(const StaticInst *si, int idx) const override	CheckerCPU	inlinevirtual
readVec64BitLaneOperand(const StaticInst *si, int idx) const override	CheckerCPU	inlinevirtual
readVec8BitLaneOperand(const StaticInst *si, int idx) const override	CheckerCPU	inlinevirtual
readVecElemOperand(const StaticInst *si, int idx) const override	CheckerCPU	inlinevirtual
readVecPredRegOperand(const StaticInst *si, int idx) const override	CheckerCPU	inlinevirtual
readVecRegOperand(const StaticInst *si, int idx) const override	CheckerCPU	inlinevirtual
recordPCChange(const TheISA::PCState &val)	CheckerCPU	inline
registerThreadContexts()	BaseCPU
regProbeListeners()	SimObject	virtual
regProbePoints() override	BaseCPU	virtual
regStats() override	BaseCPU	virtual
requestorId	CheckerCPU	protected
reschedule(Event &event, Tick when, bool always=false)	EventManager	inline
reschedule(Event *event, Tick when, bool always=false)	EventManager	inline
resetClock() const	Clocked	inlineprotected
resetStats()	Stats::Group	virtual
resolveStat(std::string name) const	Stats::Group
result	CheckerCPU	protected
schedule(Event &event, Tick when)	EventManager	inline
schedule(Event *event, Tick when)	EventManager	inline
scheduleInstStop(ThreadID tid, Counter insts, const char *cause)	BaseCPU
schedulePowerGatingEvent()	BaseCPU
Serializable()	Serializable
serialize(CheckpointOut &cp) const override	CheckerCPU	virtual
serializeAll(CheckpointOut &cp)	SimObject	static
Serializable::serializeAll(const std::string &cpt_dir)	Serializable	static
serializeSection(CheckpointOut &cp, const char *name) const	Serializable
serializeSection(CheckpointOut &cp, const std::string &name) const	Serializable	inline
serializeThread(CheckpointOut &cp, ThreadID tid) const	BaseCPU	inlinevirtual
setCCRegOperand(const StaticInst *si, int idx, RegVal val) override	CheckerCPU	inlinevirtual
setCurTick(Tick newVal)	EventManager	inline
setDcachePort(RequestPort *dcache_port)	CheckerCPU
setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override	CheckerCPU	inlinevirtual
setIcachePort(RequestPort *icache_port)	CheckerCPU
setIntRegOperand(const StaticInst *si, int idx, RegVal val) override	CheckerCPU	inlinevirtual
setMemAccPredicate(bool val) override	CheckerCPU	inlinevirtual
setMiscReg(int misc_reg, RegVal val) override	CheckerCPU	inlinevirtual
setMiscRegNoEffect(int misc_reg, RegVal val)	CheckerCPU	inline
setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override	CheckerCPU	inlinevirtual
setPid(uint32_t pid)	BaseCPU	inline
setPredicate(bool val) override	CheckerCPU	inlinevirtual
setScalarResult(T &&t)	CheckerCPU	inline
setStCondFailures(unsigned int sc_failures) override	CheckerCPU	inlinevirtual
setSystem(System *system)	CheckerCPU
setVecElemOperand(const StaticInst *si, int idx, const TheISA::VecElem val) override	CheckerCPU	inlinevirtual
setVecElemResult(T &&t)	CheckerCPU	inline
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val) override	CheckerCPU	inlinevirtual
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val) override	CheckerCPU	inlinevirtual
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val) override	CheckerCPU	inlinevirtual
setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val) override	CheckerCPU	inlinevirtual
setVecLaneOperandT(const StaticInst *si, int idx, const LD &val)	CheckerCPU	inline
setVecPredRegOperand(const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override	CheckerCPU	inlinevirtual
setVecPredResult(T &&t)	CheckerCPU	inline
setVecRegOperand(const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override	CheckerCPU	inlinevirtual
setVecResult(T &&t)	CheckerCPU	inline
signalDrainDone() const	Drainable	inlineprotected
SimObject(const Params &p)	SimObject
SimObjectList typedef	SimObject	private
simObjectList	SimObject	privatestatic
socketId() const	BaseCPU	inline
startNumInst	CheckerCPU	protected
startNumLoad	CheckerCPU
startup() override	BaseCPU	virtual
statGroups	Stats::Group	private
stats	Stats::Group	private
suspendContext(ThreadID thread_num)	BaseCPU	virtual
switchedOut() const	BaseCPU	inline
switchOut()	Checker< Impl >	virtual
syscallRetryLatency	BaseCPU
system	BaseCPU
systemPtr	CheckerCPU	protected
takeOverFrom(BaseCPU *oldCPU)	Checker< Impl >	virtual
taskId() const	BaseCPU	inline
taskId(uint32_t id)	BaseCPU	inline
tc	CheckerCPU	protected
tcBase() const override	CheckerCPU	inlinevirtual
thread	CheckerCPU
threadBase()	CheckerCPU	inline
threadContexts	BaseCPU	protected
tick	Clocked	mutableprivate
ticksToCycles(Tick t) const	Clocked	inline
totalInsts() const override	CheckerCPU	inlinevirtual
totalOps() const override	CheckerCPU	inlinevirtual
traceFunctions(Addr pc)	BaseCPU	inline
traceFunctionsInternal(Addr pc)	BaseCPU	private
tracer	BaseCPU	protected
unserialize(CheckpointIn &cp) override	CheckerCPU	virtual
unserializeGlobals(CheckpointIn &cp)	Serializable	static
unserializeSection(CheckpointIn &cp, const char *name)	Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)	Serializable	inline
unserializeThread(CheckpointIn &cp, ThreadID tid)	BaseCPU	inlinevirtual
unverifiedInst	Checker< Impl >	private
unverifiedMemData	CheckerCPU
unverifiedReq	CheckerCPU
unverifiedResult	CheckerCPU
update() const	Clocked	inlineprivate
updateClockPeriod()	Clocked	inline
updateCycleCounters(CPUState state)	BaseCPU	inlineprotected
updateOnError	CheckerCPU
updateThisCycle	Checker< Impl >	private
validateExecution(const DynInstPtr &inst)	Checker< Impl >
validateInst(const DynInstPtr &inst)	Checker< Impl >
validateState()	Checker< Impl >
verify(const DynInstPtr &inst)	Checker< Impl >
verifyMemoryMode() const	BaseCPU	inlinevirtual
voltage() const	Clocked	inline
waitForRemoteGDB() const	BaseCPU
wakeup(ThreadID tid) override	CheckerCPU	inlinevirtual
wakeupEventQueue(Tick when=(Tick) -1)	EventManager	inline
warnOnlyOnLoadError	CheckerCPU
willChangePC	CheckerCPU
workItemBegin()	BaseCPU	inline
workItemEnd()	BaseCPU	inline
workload	CheckerCPU	protected
writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override	CheckerCPU
ExecContext::writeMem(uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable)=0	ExecContext	pure virtual
youngestSN	CheckerCPU
~BaseCPU()	BaseCPU	virtual
~CheckerCPU()	CheckerCPU	virtual
~Clocked()	Clocked	inlineprotectedvirtual
~Drainable()	Drainable	protectedvirtual
~Group()	Stats::Group	virtual
~Serializable()	Serializable	virtual
~SimObject()	SimObject	virtual