gem5  v21.0.1.0
Uart8250 Member List

This is the complete list of members for Uart8250, including all inherited members.

_drainManagerDrainableprivate
_drainStateDrainablemutableprivate
_paramsSimObjectprotected
addStat(Stats::Info *info)Stats::Group
addStatGroup(const char *name, Group *block)Stats::Group
BasicPioDevice(const Params &p, Addr size)BasicPioDevice
BitUnion8(Ier) Bitfield< 0 > rdiUart8250protected
breakCondUart8250protected
breakContUart8250protected
clockDomainClockedprivate
Clocked(ClockDomain &clk_domain)Clockedinlineprotected
Clocked(Clocked &)=deleteClockedprotected
clockEdge(Cycles cycles=Cycles(0)) constClockedinline
ClockedObject(const ClockedObjectParams &p)ClockedObject
clockPeriod() constClockedinline
clockPeriodUpdated()Clockedinlineprotectedvirtual
curCycle() constClockedinline
currentSection()Serializablestatic
cycleClockedmutableprivate
cyclesToTicks(Cycles c) constClockedinline
dataAvailable() overrideUart8250virtual
deschedule(Event &event)EventManagerinline
deschedule(Event *event)EventManagerinline
deviceUartprotected
dlabUart8250protected
dmDrain()Drainableprivate
dmDrainResume()Drainableprivate
drain() overrideSimObjectinlinevirtual
Drainable()Drainableprotected
drainResume()Drainableinlineprotectedvirtual
drainState() constDrainableinline
EndBitUnion(Ier) BitUnion8(Iir) Bitfield< 0 > pendingUart8250protected
EndBitUnion(Iir) BitUnion8(Lcr) Bitfield< 1Uart8250protected
EndBitUnion(Lcr) BitUnion8(Lsr) Bitfield< 0 > rdrUart8250protected
EndBitUnion(Lsr) enum class InterruptIdsUart8250inlineprotected
EventManager(EventManager &em)EventManagerinline
EventManager(EventManager *em)EventManagerinline
EventManager(EventQueue *eq)EventManagerinline
eventqEventManagerprotected
eventQueue() constEventManagerinline
find(const char *name)SimObjectstatic
framingErrorUart8250protected
frequency() constClockedinline
getAddrRanges() const overrideUart8250virtual
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridePioDevicevirtual
getProbeManager()SimObject
getStatGroups() constStats::Group
getStats() constStats::Group
Group()=deleteStats::Group
Group(const Group &)=deleteStats::Group
Group(Group *parent, const char *name=nullptr)Stats::Group
idUart8250protected
init() overridePioDevicevirtual
initState()SimObjectvirtual
intStatus()Uart8250inlinevirtual
lastTxIntUart8250protected
loadState(CheckpointIn &cp)SimObjectvirtual
memInvalidate()SimObjectinlinevirtual
memWriteback()SimObjectinlinevirtual
mergedParentStats::Groupprivate
mergedStatGroupsStats::Groupprivate
mergeStatGroup(Group *block)Stats::Group
msiUart8250protected
name() constSimObjectinlinevirtual
nextCycle() constClockedinline
notifyFork()Drainableinlinevirtual
SimObject::operator=(const Group &)=deleteStats::Group
Clocked::operator=(Clocked &)=deleteClockedprotected
overrunErrorUart8250protected
PARAMS(BasicPioDevice)BasicPioDevice
Params typedefUart8250
params() constSimObjectinline
parityUart8250protected
parityErrorUart8250protected
pathSerializableprivatestatic
pioAddrBasicPioDeviceprotected
pioDelayBasicPioDeviceprotected
PioDevice(const Params &p)PioDevice
pioPortPioDeviceprotected
pioSizeBasicPioDeviceprotected
platformUartprotected
powerStateClockedObject
preDumpStats()Stats::Groupvirtual
probeManagerSimObjectprivate
processIntrEvent(int intrBit)Uart8250protected
read(PacketPtr pkt) overrideUart8250virtual
readIir(Register< Iir > &reg)Uart8250protected
readRbr(Register8 &reg)Uart8250protected
Register typedefUart8250protected
Register8 typedefUart8250protected
registersUart8250protected
regProbeListeners()SimObjectvirtual
regProbePoints()SimObjectvirtual
regStats()Stats::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)EventManagerinline
reschedule(Event *event, Tick when, bool always=false)EventManagerinline
resetClock() constClockedinlineprotected
resetStats()Stats::Groupvirtual
resolveStat(std::string name) constStats::Group
rlsiUart8250protected
rxIntrEventUart8250protected
schedule(Event &event, Tick when)EventManagerinline
schedule(Event *event, Tick when)EventManagerinline
scheduleIntr(Event *event)Uart8250protected
Serializable()Serializable
serialize(CheckpointOut &cp) const overrideUart8250virtual
serializeAll(CheckpointOut &cp)SimObjectstatic
Serializable::serializeAll(const std::string &cpt_dir)Serializablestatic
serializeSection(CheckpointOut &cp, const char *name) constSerializable
serializeSection(CheckpointOut &cp, const std::string &name) constSerializableinline
setCurTick(Tick newVal)EventManagerinline
signalDrainDone() constDrainableinlineprotected
SimObject(const Params &p)SimObject
SimObjectList typedefSimObjectprivate
simObjectListSimObjectprivatestatic
startup()SimObjectvirtual
statGroupsStats::Groupprivate
statsStats::Groupprivate
statusUartprotected
stopBitsUart8250protected
sysPioDeviceprotected
tbeUart8250protected
thriUart8250protected
tickClockedmutableprivate
ticksToCycles(Tick t) constClockedinline
txEmptyUart8250protected
txIntrEventUart8250protected
Uart(const Params &p, Addr pio_size)Uart
Uart8250(const Params &p)Uart8250
unserialize(CheckpointIn &cp) overrideUart8250virtual
unserializeGlobals(CheckpointIn &cp)Serializablestatic
unserializeSection(CheckpointIn &cp, const char *name)Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)Serializableinline
unusedUart8250protected
update() constClockedinlineprivate
updateClockPeriod()Clockedinline
voltage() constClockedinline
wakeupEventQueue(Tick when=(Tick) -1)EventManagerinline
wordSizeUart8250protected
write(PacketPtr pkt) overrideUart8250virtual
writeIer(Register< Ier > &reg, const Ier &ier)Uart8250protected
writeThr(Register8 &reg, const uint8_t &data)Uart8250protected
zeroesUart8250protected
~Clocked()Clockedinlineprotectedvirtual
~Drainable()Drainableprotectedvirtual
~Group()Stats::Groupvirtual
~PioDevice()PioDevicevirtual
~Serializable()Serializablevirtual
~SimObject()SimObjectvirtual
Generated on Tue Jun 22 2021 15:28:45 for gem5 by doxygen 1.8.17