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gem5
v21.0.1.0
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#include "arch/decoder.hh"#include "arch/utility.hh"#include "base/statistics.hh"#include "config/the_isa.hh"#include "cpu/pc_event.hh"#include "cpu/pred/bpred_unit.hh"#include "cpu/timebuf.hh"#include "cpu/translation.hh"#include "enums/SMTFetchPolicy.hh"#include "mem/packet.hh"#include "mem/port.hh"#include "sim/eventq.hh"#include "sim/probe/probe.hh"Go to the source code of this file.
Classes | |
| class | FullO3CPU< Impl > |
| FullO3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages. More... | |
| class | DefaultFetch< Impl > |
| DefaultFetch class handles both single threaded and SMT fetch. More... | |
| class | DefaultFetch< Impl >::IcachePort |
| IcachePort class for instruction fetch. More... | |
| class | DefaultFetch< Impl >::FetchTranslation |
| class | DefaultFetch< Impl >::FinishTranslationEvent |
| struct | DefaultFetch< Impl >::Stalls |
| Source of possible stalls. More... | |
| struct | DefaultFetch< Impl >::FetchStatGroup |