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gem5
v21.0.1.0
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#include "arch/mips/interrupts.hh"#include "arch/mips/pra_constants.hh"#include "base/trace.hh"#include "cpu/thread_context.hh"#include "debug/Interrupt.hh"Go to the source code of this file.
Namespaces | |
| MipsISA | |
Enumerations | |
| enum | MipsISA::InterruptLevels { MipsISA::INTLEVEL_SOFTWARE_MIN = 4, MipsISA::INTLEVEL_SOFTWARE_MAX = 19, MipsISA::INTLEVEL_EXTERNAL_MIN = 20, MipsISA::INTLEVEL_EXTERNAL_MAX = 34, MipsISA::INTLEVEL_IRQ0 = 20, MipsISA::INTLEVEL_IRQ1 = 21, MipsISA::INTINDEX_ETHERNET = 0, MipsISA::INTINDEX_SCSI = 1, MipsISA::INTLEVEL_IRQ2 = 22, MipsISA::INTLEVEL_IRQ3 = 23, MipsISA::INTLEVEL_SERIAL = 33, MipsISA::NumInterruptLevels = INTLEVEL_EXTERNAL_MAX } |
Functions | |
| static uint8_t | MipsISA::getCauseIP (ThreadContext *tc) |
| static void | MipsISA::setCauseIP (ThreadContext *tc, uint8_t val) |