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gem5
v21.0.1.0
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#include <bitset>#include <map>#include "arch/riscv/interrupts.hh"#include "cpu/intr_control.hh"#include "dev/io_device.hh"#include "dev/reg_bank.hh"#include "mem/packet.hh"#include "mem/packet_access.hh"#include "params/Plic.hh"#include "sim/system.hh"Go to the source code of this file.
Classes | |
| struct | PlicOutput |
| NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive.cdn.prismic.io/sifive/fab000f6- 0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_ full_20G1.03.00_manual.pdf. More... | |
| class | Plic |
| class | Plic::PlicRegisters |
| MMIO Registers. More... | |