#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
#include "arch/power/miscregs.hh"
#include "base/types.hh"

Typedefs
using	PowerISA::VecElem = ::DummyVecElem

using	PowerISA::VecReg = ::DummyVecReg

using	PowerISA::ConstVecReg = ::DummyConstVecReg

using	PowerISA::VecRegContainer = ::DummyVecRegContainer

using	PowerISA::VecPredReg = ::DummyVecPredReg

using	PowerISA::ConstVecPredReg = ::DummyConstVecPredReg

using	PowerISA::VecPredRegContainer = ::DummyVecPredRegContainer

Enumerations
enum	PowerISA::MiscIntRegNums { PowerISA::INTREG_CR = NumIntArchRegs, PowerISA::INTREG_XER, PowerISA::INTREG_LR, PowerISA::INTREG_CTR, PowerISA::INTREG_FPSCR, PowerISA::INTREG_RSV, PowerISA::INTREG_RSV_LEN, PowerISA::INTREG_RSV_ADDR }

Variables
constexpr unsigned	PowerISA::NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg

constexpr size_t	PowerISA::VecRegSizeBytes = ::DummyVecRegSizeBytes

constexpr size_t	PowerISA::VecPredRegSizeBits = ::DummyVecPredRegSizeBits

constexpr bool	PowerISA::VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr

const int	PowerISA::NumIntArchRegs = 32

const int	PowerISA::NumIntSpecialRegs = 9

const int	PowerISA::NumFloatArchRegs = 32

const int	PowerISA::NumIntRegs = NumIntArchRegs + NumIntSpecialRegs

const int	PowerISA::NumFloatRegs = NumFloatArchRegs

const int	PowerISA::NumVecRegs = 1

const int	PowerISA::NumVecPredRegs = 1

const int	PowerISA::NumCCRegs = 0

const int	PowerISA::NumMiscRegs = NUM_MISCREGS

const int	PowerISA::ReturnValueReg = 3

const int	PowerISA::StackPointerReg = 1

const int	PowerISA::ZeroReg = NumIntRegs - 1

Namespaces

Typedefs