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gem5
v21.0.1.0
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#include <map>#include <string>#include "arch/generic/isa.hh"#include "arch/riscv/registers.hh"#include "arch/riscv/types.hh"#include "base/bitfield.hh"#include "base/logging.hh"#include "cpu/reg_class.hh"#include "sim/sim_object.hh"Go to the source code of this file.
Classes | |
| class | RiscvISA::ISA |
Namespaces | |
| RiscvISA | |
Enumerations | |
| enum | RiscvISA::PrivilegeMode { RiscvISA::PRV_U = 0, RiscvISA::PRV_S = 1, RiscvISA::PRV_M = 3 } |
| enum | RiscvISA::FPUStatus { RiscvISA::OFF = 0, RiscvISA::INITIAL = 1, RiscvISA::CLEAN = 2, RiscvISA::DIRTY = 3 } |