gem5  v21.1.0.2
remote_gdb.cc
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1 /*
2  * Copyright 2015 LabWare
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4  * Copyright (c) 2010 ARM Limited
5  * Copyright (c) 2021 IBM Corporation
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43 
44 /*
45  * Copyright (c) 1990, 1993 The Regents of the University of California
46  * All rights reserved
47  *
48  * This software was developed by the Computer Systems Engineering group
49  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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52  * All advertising materials mentioning features or use of this software
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54  * This product includes software developed by the University of
55  * California, Lawrence Berkeley Laboratories.
56  *
57  * Redistribution and use in source and binary forms, with or without
58  * modification, are permitted provided that the following conditions
59  * are met:
60  * 1. Redistributions of source code must retain the above copyright
61  * notice, this list of conditions and the following disclaimer.
62  * 2. Redistributions in binary form must reproduce the above copyright
63  * notice, this list of conditions and the following disclaimer in the
64  * documentation and/or other materials provided with the distribution.
65  * 3. All advertising materials mentioning features or use of this software
66  * must display the following acknowledgement:
67  * This product includes software developed by the University of
68  * California, Berkeley and its contributors.
69  * 4. Neither the name of the University nor the names of its contributors
70  * may be used to endorse or promote products derived from this software
71  * without specific prior written permission.
72  *
73  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
74  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
77  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
83  * SUCH DAMAGE.
84  *
85  * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
86  */
87 
88 /*-
89  * Copyright (c) 2001 The NetBSD Foundation, Inc.
90  * All rights reserved.
91  *
92  * This code is derived from software contributed to The NetBSD Foundation
93  * by Jason R. Thorpe.
94  *
95  * Redistribution and use in source and binary forms, with or without
96  * modification, are permitted provided that the following conditions
97  * are met:
98  * 1. Redistributions of source code must retain the above copyright
99  * notice, this list of conditions and the following disclaimer.
100  * 2. Redistributions in binary form must reproduce the above copyright
101  * notice, this list of conditions and the following disclaimer in the
102  * documentation and/or other materials provided with the distribution.
103  * 3. All advertising materials mentioning features or use of this software
104  * must display the following acknowledgement:
105  * This product includes software developed by the NetBSD
106  * Foundation, Inc. and its contributors.
107  * 4. Neither the name of The NetBSD Foundation nor the names of its
108  * contributors may be used to endorse or promote products derived
109  * from this software without specific prior written permission.
110  *
111  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
112  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
113  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
114  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
115  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
116  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
117  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
118  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
119  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
120  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
121  * POSSIBILITY OF SUCH DAMAGE.
122  */
123 
124 /*
125  * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
126  *
127  * Taken from NetBSD
128  *
129  * "Stub" to allow remote cpu to debug over a serial line using gdb.
130  */
131 
132 
133 #include "arch/power/remote_gdb.hh"
134 
135 #include <sys/signal.h>
136 #include <unistd.h>
137 
138 #include <string>
139 
140 #include "arch/power/regs/misc.hh"
141 #include "blobs/gdb_xml_power64_core.hh"
142 #include "blobs/gdb_xml_power_core.hh"
143 #include "blobs/gdb_xml_power_fpu.hh"
144 #include "blobs/gdb_xml_powerpc_32.hh"
145 #include "blobs/gdb_xml_powerpc_64.hh"
146 #include "cpu/thread_state.hh"
147 #include "debug/GDBAcc.hh"
148 #include "debug/GDBMisc.hh"
149 #include "mem/page_table.hh"
150 #include "sim/byteswap.hh"
151 
152 namespace gem5
153 {
154 
155 using namespace PowerISA;
156 
157 RemoteGDB::RemoteGDB(System *_system, int _port)
158  : BaseRemoteGDB(_system, _port), regCache32(this), regCache64(this)
159 {
160 }
161 
162 /*
163  * Determine if the mapping at va..(va+len) is valid.
164  */
165 bool
166 RemoteGDB::acc(Addr va, size_t len)
167 {
168  // Check to make sure the first byte is mapped into the processes address
169  // space. At the time of this writing, the acc() check is used when
170  // processing the MemR/MemW packets before actually asking the translating
171  // port proxy to read/writeBlob. I (bgs) am not convinced the first byte
172  // check is enough.
173  panic_if(FullSystem, "acc not implemented for POWER FS!");
174  return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
175 }
176 
177 void
178 RemoteGDB::PowerGdbRegCache::getRegs(ThreadContext *context)
179 {
180  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
181 
182  Msr msr = context->readIntReg(INTREG_MSR);
183  ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
184 
185  // Default order on 32-bit PowerPC:
186  // R0-R31 (32-bit each), F0-F31 (64-bit IEEE754 double),
187  // PC, MSR, CR, LR, CTR, XER, FPSCR (32-bit each)
188 
189  for (int i = 0; i < NumIntArchRegs; i++)
190  r.gpr[i] = htog((uint32_t)context->readIntReg(i), order);
191 
192  for (int i = 0; i < NumFloatArchRegs; i++)
193  r.fpr[i] = context->readFloatReg(i);
194 
195  r.pc = htog((uint32_t)context->pcState().pc(), order);
196  r.msr = 0; // MSR is privileged, hence not exposed here
197  r.cr = htog((uint32_t)context->readIntReg(INTREG_CR), order);
198  r.lr = htog((uint32_t)context->readIntReg(INTREG_LR), order);
199  r.ctr = htog((uint32_t)context->readIntReg(INTREG_CTR), order);
200  r.xer = htog((uint32_t)context->readIntReg(INTREG_XER), order);
201  r.fpscr = htog((uint32_t)context->readIntReg(INTREG_FPSCR), order);
202 }
203 
204 void
205 RemoteGDB::PowerGdbRegCache::setRegs(ThreadContext *context) const
206 {
207  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
208 
209  Msr msr = context->readIntReg(INTREG_MSR);
210  ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
211 
212  for (int i = 0; i < NumIntArchRegs; i++)
213  context->setIntReg(i, gtoh(r.gpr[i], order));
214 
215  for (int i = 0; i < NumFloatArchRegs; i++)
216  context->setFloatReg(i, r.fpr[i]);
217 
218  auto pc = context->pcState();
219  pc.byteOrder(order);
220  pc.set(gtoh(r.pc, order));
221  context->pcState(pc);
222  // MSR is privileged, hence not modified here
223  context->setIntReg(INTREG_CR, gtoh(r.cr, order));
224  context->setIntReg(INTREG_LR, gtoh(r.lr, order));
225  context->setIntReg(INTREG_CTR, gtoh(r.ctr, order));
226  context->setIntReg(INTREG_XER, gtoh(r.xer, order));
227  context->setIntReg(INTREG_FPSCR, gtoh(r.fpscr, order));
228 }
229 
230 void
231 RemoteGDB::Power64GdbRegCache::getRegs(ThreadContext *context)
232 {
233  DPRINTF(GDBAcc, "getRegs in remotegdb \n");
234 
235  Msr msr = context->readIntReg(INTREG_MSR);
236  ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
237 
238  // Default order on 64-bit PowerPC:
239  // GPRR0-GPRR31 (64-bit each), FPR0-FPR31 (64-bit IEEE754 double),
240  // CIA, MSR, CR, LR, CTR, XER, FPSCR (only CR, XER, FPSCR are 32-bit
241  // each and the rest are 64-bit)
242 
243  for (int i = 0; i < NumIntArchRegs; i++)
244  r.gpr[i] = htog(context->readIntReg(i), order);
245 
246  for (int i = 0; i < NumFloatArchRegs; i++)
247  r.fpr[i] = context->readFloatReg(i);
248 
249  r.pc = htog(context->pcState().pc(), order);
250  r.msr = 0; // MSR is privileged, hence not exposed here
251  r.cr = htog((uint32_t)context->readIntReg(INTREG_CR), order);
252  r.lr = htog(context->readIntReg(INTREG_LR), order);
253  r.ctr = htog(context->readIntReg(INTREG_CTR), order);
254  r.xer = htog((uint32_t)context->readIntReg(INTREG_XER), order);
255  r.fpscr = htog((uint32_t)context->readIntReg(INTREG_FPSCR), order);
256 }
257 
258 void
259 RemoteGDB::Power64GdbRegCache::setRegs(ThreadContext *context) const
260 {
261  DPRINTF(GDBAcc, "setRegs in remotegdb \n");
262 
263  Msr msr = context->readIntReg(INTREG_MSR);
264  ByteOrder order = (msr.le ? ByteOrder::little : ByteOrder::big);
265 
266  for (int i = 0; i < NumIntArchRegs; i++)
267  context->setIntReg(i, gtoh(r.gpr[i], order));
268 
269  for (int i = 0; i < NumFloatArchRegs; i++)
270  context->setFloatReg(i, r.fpr[i]);
271 
272  auto pc = context->pcState();
273  pc.byteOrder(order);
274  pc.set(gtoh(r.pc, order));
275  context->pcState(pc);
276  // MSR is privileged, hence not modified here
277  context->setIntReg(INTREG_CR, gtoh(r.cr, order));
278  context->setIntReg(INTREG_LR, gtoh(r.lr, order));
279  context->setIntReg(INTREG_CTR, gtoh(r.ctr, order));
280  context->setIntReg(INTREG_XER, gtoh(r.xer, order));
281  context->setIntReg(INTREG_FPSCR, gtoh(r.fpscr, order));
282 }
283 
284 BaseGdbRegCache*
285 RemoteGDB::gdbRegs()
286 {
287  Msr msr = context()->readIntReg(INTREG_MSR);
288  if (msr.sf)
289  return &regCache64;
290  else
291  return &regCache32;
292 }
293 
294 bool
295 RemoteGDB::getXferFeaturesRead(const std::string &annex, std::string &output)
296 {
297 #define GDB_XML(x, s) \
298  { x, std::string(reinterpret_cast<const char *>(Blobs::s), \
299  Blobs::s ## _len) }
300  static const std::map<std::string, std::string> annexMap32{
301  GDB_XML("target.xml", gdb_xml_powerpc_32),
302  GDB_XML("power-core.xml", gdb_xml_power_core),
303  GDB_XML("power-fpu.xml", gdb_xml_power_fpu)
304  };
305  static const std::map<std::string, std::string> annexMap64{
306  GDB_XML("target.xml", gdb_xml_powerpc_64),
307  GDB_XML("power64-core.xml", gdb_xml_power64_core),
308  GDB_XML("power-fpu.xml", gdb_xml_power_fpu)
309  };
310 #undef GDB_XML
311 
312  Msr msr = context()->readIntReg(INTREG_MSR);
313  auto& annexMap = msr.sf ? annexMap64 : annexMap32;
314  auto it = annexMap.find(annex);
315  if (it == annexMap.end())
316  return false;
317  output = it->second;
318  return true;
319 }
320 
321 } // namespace gem5
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
remote_gdb.hh
thread_state.hh
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:444
gem5::PowerISA::INTREG_FPSCR
@ INTREG_FPSCR
Definition: int.hh:67
gem5::MipsISA::NumFloatArchRegs
const int NumFloatArchRegs
Definition: float.hh:42
gem5::MipsISA::NumIntArchRegs
const int NumIntArchRegs
Definition: int.hh:40
gem5::ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
gem5::output
static void output(const char *filename)
Definition: debug.cc:66
GDB_XML
#define GDB_XML(x, s)
gem5::EmulationPageTable::lookup
const Entry * lookup(Addr vaddr)
Lookup function.
Definition: page_table.cc:133
gem5::BaseGdbRegCache
Concrete subclasses of this abstract class represent how the register values are transmitted on the w...
Definition: remote_gdb.hh:85
gem5::MipsISA::RemoteGDB::getXferFeaturesRead
bool getXferFeaturesRead(const std::string &annex, std::string &output)
Get an XML target description.
gem5::MipsISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:279
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::PowerISA::INTREG_XER
@ INTREG_XER
Definition: int.hh:63
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Process::pTable
EmulationPageTable * pTable
Definition: process.hh:171
gem5::gtoh
T gtoh(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:194
gem5::PowerISA::RemoteGDB::RemoteGDB
RemoteGDB(System *_system, int _port)
gem5::htog
T htog(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:187
gem5::PowerISA::INTREG_MSR
@ INTREG_MSR
Definition: int.hh:68
gem5::ThreadContext::setFloatReg
virtual void setFloatReg(RegIndex reg_idx, RegVal val)=0
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
misc.hh
gem5::PowerISA::INTREG_LR
@ INTREG_LR
Definition: int.hh:64
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::PowerISA::INTREG_CR
@ INTREG_CR
Definition: int.hh:62
gem5::ArmISA::va
Bitfield< 8 > va
Definition: misc_types.hh:275
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::MipsISA::RemoteGDB::gdbRegs
BaseGdbRegCache * gdbRegs()
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::PowerISA::INTREG_CTR
@ INTREG_CTR
Definition: int.hh:65
gem5::BaseRemoteGDB::context
ThreadContext * context()
Definition: remote_gdb.hh:372
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::MipsISA::RemoteGDB::acc
bool acc(Addr addr, size_t len)
page_table.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
byteswap.hh
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