gem5::Gicv3CPUInterface Member List

This is the complete list of members for gem5::Gicv3CPUInterface, including all inherited members.

A3V	gem5::Gicv3CPUInterface	protected
A3V	gem5::Gicv3CPUInterface	protected
assertWakeRequest(void)	gem5::Gicv3CPUInterface	protected
BaseISADevice()	gem5::ArmISA::BaseISADevice
BitUnion32(ICH_LRC) Bitfield< 31	gem5::Gicv3CPUInterface	protected
BitUnion64(ICC_CTLR_EL1) Bitfield< 63	gem5::Gicv3CPUInterface	protected
BitUnion64(ICH_HCR_EL2) Bitfield< 63	gem5::Gicv3CPUInterface	protected
bpr1(Gicv3::GroupId group)	gem5::Gicv3CPUInterface	protected
CBPR	gem5::Gicv3CPUInterface	protected
CBPR_EL1NS	gem5::Gicv3CPUInterface	protected
CBPR_EL1S	gem5::Gicv3CPUInterface	protected
clearPendingInterrupts(void)	gem5::Gicv3CPUInterface	protected
cpuId	gem5::Gicv3CPUInterface	protected
currEL() const	gem5::Gicv3CPUInterface	protected
currentSection()	gem5::Serializable	static
deactivateIRQ(uint32_t intid, Gicv3::GroupId group)	gem5::Gicv3CPUInterface	protected
deassertWakeRequest(void)	gem5::Gicv3CPUInterface	protected
DFB	gem5::Gicv3CPUInterface	protected
DIB	gem5::Gicv3CPUInterface	protected
distributor	gem5::Gicv3CPUInterface	protected
dropPriority(Gicv3::GroupId group)	gem5::Gicv3CPUInterface	protected
En	gem5::Gicv3CPUInterface	protected
Enable	gem5::Gicv3CPUInterface	protected
Enable	gem5::Gicv3CPUInterface	protected
EnableGrp1NS	gem5::Gicv3CPUInterface	protected
EnableGrp1S	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICC_CTLR_EL1) BitUnion64(ICC_CTLR_EL3) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICC_CTLR_EL3) BitUnion64(ICC_IGRPEN0_EL1) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICC_IGRPEN0_EL1) BitUnion64(ICC_IGRPEN1_EL1) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICC_IGRPEN1_EL1) BitUnion64(ICC_IGRPEN1_EL3) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICC_IGRPEN1_EL3) BitUnion64(ICC_SRE_EL1) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICC_SRE_EL1) BitUnion64(ICC_SRE_EL2) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICC_SRE_EL2) BitUnion64(ICC_SRE_EL3) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICC_SRE_EL3) static const uint8_t PRIORITY_BITS	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICH_HCR_EL2) BitUnion64(ICH_LR_EL2) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICH_LR_EL2) static const uint64_t ICH_LR_EL2_STATE_INVALID=0	gem5::Gicv3CPUInterface	protectedpure virtual
EndBitUnion(ICH_LRC) BitUnion64(ICH_MISR_EL2) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICH_MISR_EL2) BitUnion64(ICH_VMCR_EL2) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICH_VMCR_EL2) BitUnion64(ICH_VTR_EL2) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EndBitUnion(ICH_VTR_EL2) BitUnion64(ICV_CTLR_EL1) Bitfield< 63	gem5::Gicv3CPUInterface	protected
EOI	gem5::Gicv3CPUInterface	protected
EOI	gem5::Gicv3CPUInterface	protected
EOI	gem5::Gicv3CPUInterface	protected
EOIcount	gem5::Gicv3CPUInterface	protected
eoiMaintenanceInterruptStatus() const	gem5::Gicv3CPUInterface	protected
EOImode	gem5::Gicv3CPUInterface	protected
EOImode_EL1NS	gem5::Gicv3CPUInterface	protected
EOImode_EL1S	gem5::Gicv3CPUInterface	protected
EOImode_EL3	gem5::Gicv3CPUInterface	protected
ExtRange	gem5::Gicv3CPUInterface	protected
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)	gem5::Serializable	static
generateSGI(RegVal val, Gicv3::GroupId group)	gem5::Gicv3CPUInterface	protected
getHCREL2FMO() const	gem5::Gicv3CPUInterface	protected
getHCREL2IMO() const	gem5::Gicv3CPUInterface	protected
getHPPIR0() const	gem5::Gicv3CPUInterface	protected
getHPPIR1() const	gem5::Gicv3CPUInterface	protected
getHPPVILR() const	gem5::Gicv3CPUInterface	protected
gic	gem5::Gicv3CPUInterface	protected
GIC_MIN_BPR	gem5::Gicv3CPUInterface	protectedstatic
GIC_MIN_BPR_NS	gem5::Gicv3CPUInterface	protectedstatic
GIC_MIN_VBPR	gem5::Gicv3CPUInterface	protectedstatic
GICC_ABPR enum value	gem5::Gicv3CPUInterface	protected
GICC_AEOIR enum value	gem5::Gicv3CPUInterface	protected
GICC_AHPPIR enum value	gem5::Gicv3CPUInterface	protected
GICC_AIAR enum value	gem5::Gicv3CPUInterface	protected
GICC_APR	gem5::Gicv3CPUInterface	protectedstatic
GICC_BPR enum value	gem5::Gicv3CPUInterface	protected
GICC_CTLR enum value	gem5::Gicv3CPUInterface	protected
GICC_EOIR enum value	gem5::Gicv3CPUInterface	protected
GICC_HPPI enum value	gem5::Gicv3CPUInterface	protected
GICC_IAR enum value	gem5::Gicv3CPUInterface	protected
GICC_IIDR enum value	gem5::Gicv3CPUInterface	protected
GICC_NSAPR	gem5::Gicv3CPUInterface	protectedstatic
GICC_PMR enum value	gem5::Gicv3CPUInterface	protected
GICC_RPR enum value	gem5::Gicv3CPUInterface	protected
GICC_STATUSR enum value	gem5::Gicv3CPUInterface	protected
GICH_APR	gem5::Gicv3CPUInterface	protectedstatic
GICH_EISR enum value	gem5::Gicv3CPUInterface	protected
GICH_ELRSR enum value	gem5::Gicv3CPUInterface	protected
GICH_HCR enum value	gem5::Gicv3CPUInterface	protected
GICH_LR	gem5::Gicv3CPUInterface	protectedstatic
GICH_MISR enum value	gem5::Gicv3CPUInterface	protected
GICH_VMCR enum value	gem5::Gicv3CPUInterface	protected
GICH_VTR enum value	gem5::Gicv3CPUInterface	protected
Gicv3CPUInterface(Gicv3 *gic, uint32_t cpu_id)	gem5::Gicv3CPUInterface
Gicv3Distributor class	gem5::Gicv3CPUInterface	friend
Gicv3Redistributor class	gem5::Gicv3CPUInterface	friend
Group	gem5::Gicv3CPUInterface	protected
Group	gem5::Gicv3CPUInterface	protected
groupEnabled(Gicv3::GroupId group) const	gem5::Gicv3CPUInterface	protected
groupPriorityMask(Gicv3::GroupId group)	gem5::Gicv3CPUInterface	protected
haveEL(ArmISA::ExceptionLevel el) const	gem5::Gicv3CPUInterface	protected
havePendingInterrupts(void) const	gem5::Gicv3CPUInterface	protected
highestActiveGroup() const	gem5::Gicv3CPUInterface	protected
highestActivePriority() const	gem5::Gicv3CPUInterface	protected
hppi	gem5::Gicv3CPUInterface	protected
hppiCanPreempt()	gem5::Gicv3CPUInterface	protected
hppviCanPreempt(int lrIdx) const	gem5::Gicv3CPUInterface	protected
HW	gem5::Gicv3CPUInterface	protected
HW	gem5::Gicv3CPUInterface	protected
ICH_LR_EL2_STATE_ACTIVE	gem5::Gicv3CPUInterface	protectedstatic
ICH_LR_EL2_STATE_ACTIVE_PENDING	gem5::Gicv3CPUInterface	protectedstatic
ICH_LR_EL2_STATE_PENDING	gem5::Gicv3CPUInterface	protectedstatic
IDbits	gem5::Gicv3CPUInterface	protected
IDbits	gem5::Gicv3CPUInterface	protected
init()	gem5::Gicv3CPUInterface
inSecureState() const	gem5::Gicv3CPUInterface	protected
intSignalType(Gicv3::GroupId group) const	gem5::Gicv3CPUInterface	protected
isa	gem5::ArmISA::BaseISADevice	protected
isAA64() const	gem5::Gicv3CPUInterface	protected
isEL3OrMon() const	gem5::Gicv3CPUInterface	protected
isEOISplitMode() const	gem5::Gicv3CPUInterface	protected
isSecureBelowEL3() const	gem5::Gicv3CPUInterface	protected
ListRegs	gem5::Gicv3CPUInterface	protected
LRENP	gem5::Gicv3CPUInterface	protected
LRENPIE	gem5::Gicv3CPUInterface	protected
maintenanceInterrupt	gem5::Gicv3CPUInterface	protected
maintenanceInterruptStatus() const	gem5::Gicv3CPUInterface	protected
nDS	gem5::Gicv3CPUInterface	protected
NP	gem5::Gicv3CPUInterface	protected
NPIE	gem5::Gicv3CPUInterface	protected
path	gem5::Serializable	privatestatic
pINTID	gem5::Gicv3CPUInterface	protected
pINTID	gem5::Gicv3CPUInterface	protected
PMHE	gem5::Gicv3CPUInterface	protected
PREbits	gem5::Gicv3CPUInterface	protected
PRIbits	gem5::Gicv3CPUInterface	protected
PRIbits	gem5::Gicv3CPUInterface	protected
Priority	gem5::Gicv3CPUInterface	protected
Priority	gem5::Gicv3CPUInterface	protected
readBankedMiscReg(ArmISA::MiscRegIndex misc_reg) const	gem5::Gicv3CPUInterface	protected
readMiscReg(int misc_reg) override	gem5::Gicv3CPUInterface	virtual
redistributor	gem5::Gicv3CPUInterface	protected
res0	gem5::Gicv3CPUInterface	protected
res0_0	gem5::Gicv3CPUInterface	protected
res0_0	gem5::Gicv3CPUInterface	protected
res0_0	gem5::Gicv3CPUInterface	protected
res0_0	gem5::Gicv3CPUInterface	protected
res0_0	gem5::Gicv3CPUInterface	protected
res0_0	gem5::Gicv3CPUInterface	protected
res0_0	gem5::Gicv3CPUInterface	protected
res0_0	gem5::Gicv3CPUInterface	protected
res0_1	gem5::Gicv3CPUInterface	protected
res0_1	gem5::Gicv3CPUInterface	protected
res0_1	gem5::Gicv3CPUInterface	protected
res0_1	gem5::Gicv3CPUInterface	protected
res0_1	gem5::Gicv3CPUInterface	protected
res0_1	gem5::Gicv3CPUInterface	protected
res0_1	gem5::Gicv3CPUInterface	protected
res0_1	gem5::Gicv3CPUInterface	protected
res0_2	gem5::Gicv3CPUInterface	protected
res0_2	gem5::Gicv3CPUInterface	protected
res0_3	gem5::Gicv3CPUInterface	protected
res1	gem5::Gicv3CPUInterface	protected
resetHppi(uint32_t intid)	gem5::Gicv3CPUInterface	protected
RM	gem5::Gicv3CPUInterface	protected
RSS	gem5::Gicv3CPUInterface	protected
SEIS	gem5::Gicv3CPUInterface	protected
SEIS	gem5::Gicv3CPUInterface	protected
Serializable()	gem5::Serializable
serialize(CheckpointOut &cp) const override	gem5::Gicv3CPUInterface	protectedvirtual
serializeSection(CheckpointOut &cp, const char *name) const	gem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) const	gem5::Serializable	inline
setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const	gem5::Gicv3CPUInterface	protected
setISA(ISA *isa)	gem5::ArmISA::BaseISADevice	virtual
setMiscReg(int misc_reg, RegVal val) override	gem5::Gicv3CPUInterface	virtual
setThreadContext(ThreadContext *tc) override	gem5::Gicv3CPUInterface	virtual
SRE	gem5::Gicv3CPUInterface	protected
State	gem5::Gicv3CPUInterface	protected
TALL0	gem5::Gicv3CPUInterface	protected
TALL1	gem5::Gicv3CPUInterface	protected
TC	gem5::Gicv3CPUInterface	protected
TDIR	gem5::Gicv3CPUInterface	protected
TDS	gem5::Gicv3CPUInterface	protected
TSEI	gem5::Gicv3CPUInterface	protected
U	gem5::Gicv3CPUInterface	protected
UIE	gem5::Gicv3CPUInterface	protected
unserialize(CheckpointIn &cp) override	gem5::Gicv3CPUInterface	protectedvirtual
unserializeSection(CheckpointIn &cp, const char *name)	gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)	gem5::Serializable	inline
update()	gem5::Gicv3CPUInterface	protected
updateDistributor()	gem5::Gicv3CPUInterface	protected
VAckCtl	gem5::Gicv3CPUInterface	protected
VBPR0	gem5::Gicv3CPUInterface	protected
VBPR1	gem5::Gicv3CPUInterface	protected
VCBPR	gem5::Gicv3CPUInterface	protected
VENG0	gem5::Gicv3CPUInterface	protected
VENG1	gem5::Gicv3CPUInterface	protected
VEOIM	gem5::Gicv3CPUInterface	protected
VFIQEn	gem5::Gicv3CPUInterface	protected
VGrp0D	gem5::Gicv3CPUInterface	protected
VGrp0DIE	gem5::Gicv3CPUInterface	protected
VGrp0E	gem5::Gicv3CPUInterface	protected
VGrp0EIE	gem5::Gicv3CPUInterface	protected
VGrp1D	gem5::Gicv3CPUInterface	protected
VGrp1DIE	gem5::Gicv3CPUInterface	protected
VGrp1E	gem5::Gicv3CPUInterface	protected
VGrp1EIE	gem5::Gicv3CPUInterface	protected
vINTID	gem5::Gicv3CPUInterface	protected
VIRTUAL_NUM_LIST_REGS	gem5::Gicv3CPUInterface	protectedstatic
VIRTUAL_PREEMPTION_BITS	gem5::Gicv3CPUInterface	protectedstatic
VIRTUAL_PRIORITY_BITS	gem5::Gicv3CPUInterface	protectedstatic
virtualActivateIRQ(uint32_t lrIdx)	gem5::Gicv3CPUInterface	protected
virtualDeactivateIRQ(int lrIdx)	gem5::Gicv3CPUInterface	protected
virtualDropPriority()	gem5::Gicv3CPUInterface	protected
virtualFindActive(uint32_t intid) const	gem5::Gicv3CPUInterface	protected
virtualGroupPriorityMask(Gicv3::GroupId group) const	gem5::Gicv3CPUInterface	protected
virtualHighestActivePriority() const	gem5::Gicv3CPUInterface	protected
virtualIncrementEOICount()	gem5::Gicv3CPUInterface	protected
virtualIsEOISplitMode() const	gem5::Gicv3CPUInterface	protected
virtualUpdate()	gem5::Gicv3CPUInterface	protected
VPMR	gem5::Gicv3CPUInterface	protected
~BaseISADevice()	gem5::ArmISA::BaseISADevice	inlinevirtual
~Serializable()	gem5::Serializable	virtual