| _destRegIdxPtr | gem5::StaticInst | private |
| _numCCDestRegs | gem5::StaticInst | protected |
| _numDestRegs | gem5::StaticInst | protected |
| _numFPDestRegs | gem5::StaticInst | protected |
| _numIntDestRegs | gem5::StaticInst | protected |
| _numSrcRegs | gem5::StaticInst | protected |
| _numVecDestRegs | gem5::StaticInst | protected |
| _numVecElemDestRegs | gem5::StaticInst | protected |
| _numVecPredDestRegs | gem5::StaticInst | protected |
| _opClass | gem5::StaticInst | protected |
| _srcRegIdxPtr | gem5::StaticInst | private |
| aa | gem5::PowerISA::BranchOp | protected |
| advancePC(PowerISA::PCState &pcState) const override | gem5::PowerISA::PowerStaticInst | inlineprotected |
| gem5::StaticInst::advancePC(TheISA::PCState &pc_state) const =0 | gem5::StaticInst | pure virtual |
| asBytes(void *buf, size_t max_size) override | gem5::PowerISA::PowerStaticInst | inlineprotectedvirtual |
| BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass) | gem5::PowerISA::BranchOp | inlineprotected |
| branchTarget(ThreadContext *tc) const override | gem5::PowerISA::BranchOp | protectedvirtual |
| branchTarget(const TheISA::PCState &pc) const | gem5::PowerISA::BranchOp | protected |
| branchTarget(ThreadContext *tc) const | gem5::PowerISA::BranchOp | protected |
| gem5::PowerISA::PCDependentDisassembly::branchTarget(const TheISA::PCState &pc) const | gem5::StaticInst | virtual |
| buildRetPC(const PCState &curPC, const PCState &callPC) const override | gem5::PowerISA::PowerStaticInst | inlineprotected |
| gem5::StaticInst::buildRetPC(const TheISA::PCState &cur_pc, const TheISA::PCState &call_pc) const | gem5::StaticInst | inlinevirtual |
| cachedDisassembly | gem5::StaticInst | mutableprotected |
| cachedPC | gem5::PowerISA::PCDependentDisassembly | mutableprotected |
| cachedSymtab | gem5::PowerISA::PCDependentDisassembly | mutableprotected |
| completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *trace_data) const | gem5::StaticInst | inlinevirtual |
| count | gem5::RefCounted | mutableprivate |
| decref() const | gem5::RefCounted | inline |
| destRegIdx(int i) const | gem5::StaticInst | inline |
| disassemble(Addr pc, const loader::SymbolTable *symtab) const | gem5::PowerISA::PCDependentDisassembly | protectedvirtual |
| execute(ExecContext *xc, Trace::InstRecord *traceData) const =0 | gem5::StaticInst | pure virtual |
| fetchMicroop(MicroPC upc) const | gem5::StaticInst | virtual |
| flags | gem5::StaticInst | protected |
| generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override | gem5::PowerISA::BranchOp | protectedvirtual |
| getEMI() const | gem5::StaticInst | inlinevirtual |
| getName() | gem5::StaticInst | inline |
| hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const | gem5::StaticInst | |
| incref() const | gem5::RefCounted | inline |
| initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const | gem5::StaticInst | inlinevirtual |
| insertCRField(uint32_t cr, uint32_t bf, uint32_t value) const | gem5::PowerISA::PowerStaticInst | inlineprotected |
| isAtomic() const | gem5::StaticInst | inline |
| isCall() const | gem5::StaticInst | inline |
| isCondCtrl() const | gem5::StaticInst | inline |
| isControl() const | gem5::StaticInst | inline |
| isDataPrefetch() const | gem5::StaticInst | inline |
| isDelayedCommit() const | gem5::StaticInst | inline |
| isDirectCtrl() const | gem5::StaticInst | inline |
| isFirstMicroop() const | gem5::StaticInst | inline |
| isFloating() const | gem5::StaticInst | inline |
| isFullMemBarrier() const | gem5::StaticInst | inline |
| isHtmCancel() const | gem5::StaticInst | inline |
| isHtmCmd() const | gem5::StaticInst | inline |
| isHtmStart() const | gem5::StaticInst | inline |
| isHtmStop() const | gem5::StaticInst | inline |
| isIndirectCtrl() const | gem5::StaticInst | inline |
| isInstPrefetch() const | gem5::StaticInst | inline |
| isInteger() const | gem5::StaticInst | inline |
| isLastMicroop() const | gem5::StaticInst | inline |
| isLoad() const | gem5::StaticInst | inline |
| isMacroop() const | gem5::StaticInst | inline |
| isMemRef() const | gem5::StaticInst | inline |
| isMicroop() const | gem5::StaticInst | inline |
| isNonSpeculative() const | gem5::StaticInst | inline |
| isNop() const | gem5::StaticInst | inline |
| isPrefetch() const | gem5::StaticInst | inline |
| isQuiesce() const | gem5::StaticInst | inline |
| isReadBarrier() const | gem5::StaticInst | inline |
| isReturn() const | gem5::StaticInst | inline |
| isSerializeAfter() const | gem5::StaticInst | inline |
| isSerializeBefore() const | gem5::StaticInst | inline |
| isSerializing() const | gem5::StaticInst | inline |
| isSquashAfter() const | gem5::StaticInst | inline |
| isStore() const | gem5::StaticInst | inline |
| isStoreConditional() const | gem5::StaticInst | inline |
| isSyscall() const | gem5::StaticInst | inline |
| isUncondCtrl() const | gem5::StaticInst | inline |
| isUnverifiable() const | gem5::StaticInst | inline |
| isVector() const | gem5::StaticInst | inline |
| isWriteBarrier() const | gem5::StaticInst | inline |
| li | gem5::PowerISA::BranchOp | protected |
| lk | gem5::PowerISA::BranchOp | protected |
| machInst | gem5::PowerISA::PowerStaticInst | protected |
| mnemonic | gem5::StaticInst | protected |
| nullStaticInstPtr | gem5::StaticInst | static |
| numCCDestRegs() const | gem5::StaticInst | inline |
| numDestRegs() const | gem5::StaticInst | inline |
| numFPDestRegs() const | gem5::StaticInst | inline |
| numIntDestRegs() const | gem5::StaticInst | inline |
| numSrcRegs() const | gem5::StaticInst | inline |
| numVecDestRegs() const | gem5::StaticInst | inline |
| numVecElemDestRegs() const | gem5::StaticInst | inline |
| numVecPredDestRegs() const | gem5::StaticInst | inline |
| opClass() const | gem5::StaticInst | inline |
| operator=(const RefCounted &) | gem5::RefCounted | private |
| PCDependentDisassembly(const char *mnem, ExtMachInst _machInst, OpClass __opClass) | gem5::PowerISA::PCDependentDisassembly | inlineprotected |
| PowerStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) | gem5::PowerISA::PowerStaticInst | inlineprotected |
| printFlags(std::ostream &outs, const std::string &separator) const | gem5::StaticInst | |
| printReg(std::ostream &os, RegId reg) const | gem5::PowerISA::PowerStaticInst | protected |
| RefCounted(const RefCounted &) | gem5::RefCounted | private |
| RefCounted() | gem5::RefCounted | inline |
| RegIdArrayPtr typedef | gem5::StaticInst | |
| setDelayedCommit() | gem5::StaticInst | inline |
| setDestRegIdx(int i, const RegId &val) | gem5::StaticInst | inline |
| setFirstMicroop() | gem5::StaticInst | inline |
| setFlag(Flags f) | gem5::StaticInst | inline |
| setLastMicroop() | gem5::StaticInst | inline |
| setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest) | gem5::StaticInst | inlineprotected |
| setSrcRegIdx(int i, const RegId &val) | gem5::StaticInst | inline |
| simpleAsBytes(void *buf, size_t max_size, const T &t) | gem5::StaticInst | inlineprotected |
| srcRegIdx(int i) const | gem5::StaticInst | inline |
| StaticInst(const char *_mnemonic, OpClass op_class) | gem5::StaticInst | inlineprotected |
| ~RefCounted() | gem5::RefCounted | inlinevirtual |
| ~StaticInst() | gem5::StaticInst | inlinevirtual |