gem5::o3::CPU Member List

This is the complete list of members for gem5::o3::CPU, including all inherited members.

_cacheLineSize	gem5::BaseCPU	protected
_cpuId	gem5::BaseCPU	protected
_dataRequestorId	gem5::BaseCPU	protected
_drainManager	gem5::Drainable	private
_drainState	gem5::Drainable	mutableprivate
_instRequestorId	gem5::BaseCPU	protected
_name	gem5::Named	private
_objNameResolver	gem5::SimObject	privatestatic
_params	gem5::SimObject	protected
_pid	gem5::BaseCPU	protected
_socketId	gem5::BaseCPU	protected
_status	gem5::o3::CPU
_switchedOut	gem5::BaseCPU	protected
_taskId	gem5::BaseCPU	protected
activateContext(ThreadID tid) override	gem5::o3::CPU	virtual
activateStage(const StageIdx idx)	gem5::o3::CPU	inline
activateThread(ThreadID tid)	gem5::o3::CPU
activeThreads	gem5::o3::CPU	protected
activityRec	gem5::o3::CPU	private
activityThisCycle()	gem5::o3::CPU	inline
addInst(const DynInstPtr &inst)	gem5::o3::CPU
addressMonitor	gem5::BaseCPU	private
addStat(statistics::Info *info)	gem5::statistics::Group
addStatGroup(const char *name, Group *block)	gem5::statistics::Group
addThreadToExitingList(ThreadID tid)	gem5::o3::CPU
armMonitor(ThreadID tid, Addr address)	gem5::BaseCPU
BaseCPU(const Params &params, bool is_checker=false)	gem5::BaseCPU
baseStats	gem5::BaseCPU
Blocked enum value	gem5::o3::CPU
cacheLineSize() const	gem5::BaseCPU	inline
checker	gem5::o3::CPU
checkInterrupts(ThreadID tid) const	gem5::BaseCPU	inline
cleanUpRemovedInsts()	gem5::o3::CPU
clearInterrupt(ThreadID tid, int int_num, int index)	gem5::BaseCPU	inline
clearInterrupts(ThreadID tid)	gem5::BaseCPU	inline
clockDomain	gem5::Clocked	private
Clocked(ClockDomain &clk_domain)	gem5::Clocked	inlineprotected
Clocked(Clocked &)=delete	gem5::Clocked	protected
clockEdge(Cycles cycles=Cycles(0)) const	gem5::Clocked	inline
ClockedObject(const ClockedObjectParams &p)	gem5::ClockedObject
clockPeriod() const	gem5::Clocked	inline
clockPeriodUpdated()	gem5::Clocked	inlineprotectedvirtual
commit	gem5::o3::CPU	protected
commitDrained(ThreadID tid)	gem5::o3::CPU
CommitIdx enum value	gem5::o3::CPU
commitRenameMap	gem5::o3::CPU	protected
contextToThread(ContextID cid)	gem5::BaseCPU	inline
CPU(const O3CPUParams &params)	gem5::o3::CPU
CPU_STATE_ON enum value	gem5::BaseCPU	protected
CPU_STATE_SLEEP enum value	gem5::BaseCPU	protected
CPU_STATE_WAKEUP enum value	gem5::BaseCPU	protected
cpuId() const	gem5::BaseCPU	inline
cpuList	gem5::BaseCPU	privatestatic
CPUState enum name	gem5::BaseCPU	protected
cpuStats	gem5::o3::CPU
cpuWaitList	gem5::o3::CPU
curCycle() const	gem5::Clocked	inline
currentFunctionEnd	gem5::BaseCPU	private
currentFunctionStart	gem5::BaseCPU	private
currentSection()	gem5::Serializable	static
cycle	gem5::Clocked	mutableprivate
cyclesToTicks(Cycles c) const	gem5::Clocked	inline
dataRequestorId() const	gem5::BaseCPU	inline
deactivateStage(const StageIdx idx)	gem5::o3::CPU	inline
deactivateThread(ThreadID tid)	gem5::o3::CPU
decode	gem5::o3::CPU	protected
DecodeIdx enum value	gem5::o3::CPU
decodeQueue	gem5::o3::CPU
demapPage(Addr vaddr, uint64_t asn)	gem5::o3::CPU	inline
deschedule(Event &event)	gem5::EventManager	inline
deschedule(Event *event)	gem5::EventManager	inline
deschedulePowerGatingEvent()	gem5::BaseCPU
dmDrain()	gem5::Drainable	private
dmDrainResume()	gem5::Drainable	private
drain() override	gem5::o3::CPU	virtual
Drainable()	gem5::Drainable	protected
drainResume() override	gem5::o3::CPU	virtual
drainSanityCheck() const	gem5::o3::CPU	private
drainState() const	gem5::Drainable	inline
dumpInsts()	gem5::o3::CPU
enableFunctionTrace()	gem5::BaseCPU	private
enterPwrGating()	gem5::BaseCPU	protected
enterPwrGatingEvent	gem5::BaseCPU	protected
EventManager(EventManager &em)	gem5::EventManager	inline
EventManager(EventManager *em)	gem5::EventManager	inline
EventManager(EventQueue *eq)	gem5::EventManager	inline
eventq	gem5::EventManager	protected
eventQueue() const	gem5::EventManager	inline
exitingThreads	gem5::o3::CPU	protected
exitThreads()	gem5::o3::CPU
fetch	gem5::o3::CPU	protected
FetchIdx enum value	gem5::o3::CPU
fetchQueue	gem5::o3::CPU
find(const char *name)	gem5::SimObject	static
findContext(ThreadContext *tc)	gem5::BaseCPU
flushTLBs()	gem5::BaseCPU
freeList	gem5::o3::CPU	protected
frequency() const	gem5::Clocked	inline
functionEntryTick	gem5::BaseCPU	private
functionTraceStream	gem5::BaseCPU	private
functionTracingEnabled	gem5::BaseCPU	private
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)	gem5::Serializable	static
getAndIncrementInstSeq()	gem5::o3::CPU	inline
getContext(int tn)	gem5::BaseCPU	inlinevirtual
getCpuAddrMonitor(ThreadID tid)	gem5::BaseCPU	inline
getCurrentInstCount(ThreadID tid)	gem5::BaseCPU
getDataPort() override	gem5::o3::CPU	inlinevirtual
getFreeTid()	gem5::o3::CPU
getInstPort() override	gem5::o3::CPU	inlinevirtual
getInterruptController(ThreadID tid)	gem5::BaseCPU	inline
getInterrupts()	gem5::o3::CPU
getPid() const	gem5::BaseCPU	inline
getPort(const std::string &if_name, PortID idx=InvalidPortID) override	gem5::BaseCPU	virtual
getProbeManager()	gem5::SimObject
getSimObjectResolver()	gem5::SimObject	static
getStatGroups() const	gem5::statistics::Group
getStats() const	gem5::statistics::Group
getTracer()	gem5::BaseCPU	inline
getWritableArchVecPredReg(int reg_idx, ThreadID tid)	gem5::o3::CPU
getWritableArchVecReg(int reg_idx, ThreadID tid)	gem5::o3::CPU
getWritableVecPredReg(PhysRegIdPtr reg_idx)	gem5::o3::CPU
getWritableVecReg(PhysRegIdPtr reg_idx)	gem5::o3::CPU
globalSeqNum	gem5::o3::CPU
globalStats	gem5::BaseCPU	protectedstatic
Group()=delete	gem5::statistics::Group
Group(const Group &)=delete	gem5::statistics::Group
Group(Group *parent, const char *name=nullptr)	gem5::statistics::Group
halt()	gem5::o3::CPU	inline
haltContext(ThreadID tid) override	gem5::o3::CPU	virtual
Halted enum value	gem5::o3::CPU
htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)	gem5::o3::CPU
Idle enum value	gem5::o3::CPU
iew	gem5::o3::CPU	protected
IEWIdx enum value	gem5::o3::CPU
iewQueue	gem5::o3::CPU
init() override	gem5::o3::CPU	virtual
initState()	gem5::SimObject	virtual
insertThread(ThreadID tid)	gem5::o3::CPU
instAddr(ThreadID tid)	gem5::o3::CPU
instCnt	gem5::BaseCPU	protected
instCount()	gem5::BaseCPU	inline
instcount	gem5::o3::CPU
instDone(ThreadID tid, const DynInstPtr &inst)	gem5::o3::CPU
instList	gem5::o3::CPU
instRequestorId() const	gem5::BaseCPU	inline
interrupts	gem5::BaseCPU	protected
invldPid	gem5::BaseCPU	static
isa	gem5::o3::CPU	protected
isCpuDrained() const	gem5::o3::CPU	private
isDraining() const	gem5::o3::CPU	inline
isThreadExiting(ThreadID tid) const	gem5::o3::CPU
lastActivatedCycle	gem5::o3::CPU
lastRunningCycle	gem5::o3::CPU
ListIt typedef	gem5::o3::CPU
loadState(CheckpointIn &cp)	gem5::SimObject	virtual
LSQRequest typedef	gem5::o3::CPU
memInvalidate()	gem5::SimObject	inlinevirtual
memWriteback()	gem5::SimObject	inlinevirtual
mergedParent	gem5::statistics::Group	private
mergedStatGroups	gem5::statistics::Group	private
mergeStatGroup(Group *block)	gem5::statistics::Group
microPC(ThreadID tid)	gem5::o3::CPU
mmu	gem5::o3::CPU
mwait(ThreadID tid, PacketPtr pkt)	gem5::BaseCPU
mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)	gem5::BaseCPU
name() const	gem5::Named	inlinevirtual
Named(const std::string &name_)	gem5::Named	inline
nextCycle() const	gem5::Clocked	inline
nextInstAddr(ThreadID tid)	gem5::o3::CPU
notifyFork()	gem5::Drainable	inlinevirtual
numActiveThreads()	gem5::o3::CPU	inline
numContexts()	gem5::BaseCPU	inline
numSimulatedCPUs()	gem5::BaseCPU	inlinestatic
numSimulatedInsts()	gem5::BaseCPU	inlinestatic
numSimulatedOps()	gem5::BaseCPU	inlinestatic
NumStages enum value	gem5::o3::CPU
numThreads	gem5::BaseCPU
gem5::operator=(const Group &)=delete	gem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=delete	gem5::Clocked	protected
params() const	gem5::SimObject	inline
PARAMS(BaseCPU)	gem5::BaseCPU
Params typedef	gem5::ClockedObject
path	gem5::Serializable	privatestatic
pcState(const TheISA::PCState &newPCState, ThreadID tid)	gem5::o3::CPU
pcState(ThreadID tid)	gem5::o3::CPU
pmuProbePoint(const char *name)	gem5::BaseCPU	protected
postInterrupt(ThreadID tid, int int_num, int index)	gem5::BaseCPU
powerGatingOnIdle	gem5::BaseCPU	protected
powerState	gem5::ClockedObject
ppActiveCycles	gem5::BaseCPU	protected
ppAllCycles	gem5::BaseCPU	protected
ppDataAccessComplete	gem5::o3::CPU
ppInstAccessComplete	gem5::o3::CPU
ppRetiredBranches	gem5::BaseCPU	protected
ppRetiredInsts	gem5::BaseCPU	protected
ppRetiredInstsPC	gem5::BaseCPU	protected
ppRetiredLoads	gem5::BaseCPU	protected
ppRetiredStores	gem5::BaseCPU	protected
ppSleeping	gem5::BaseCPU	protected
preDumpStats()	gem5::statistics::Group	virtual
previousCycle	gem5::BaseCPU	protected
previousState	gem5::BaseCPU	protected
probeInstCommit(const StaticInstPtr &inst, Addr pc)	gem5::BaseCPU	virtual
probeManager	gem5::SimObject	private
processInterrupts(const Fault &interrupt)	gem5::o3::CPU
pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())	gem5::o3::CPU	inline
pwrGatingLatency	gem5::BaseCPU	protected
read(LSQRequest *req, int load_idx)	gem5::o3::CPU	inline
readArchCCReg(int reg_idx, ThreadID tid)	gem5::o3::CPU
readArchFloatReg(int reg_idx, ThreadID tid)	gem5::o3::CPU
readArchIntReg(int reg_idx, ThreadID tid)	gem5::o3::CPU
readArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, ThreadID tid) const	gem5::o3::CPU
readArchVecPredReg(int reg_idx, ThreadID tid) const	gem5::o3::CPU
readArchVecReg(int reg_idx, ThreadID tid) const	gem5::o3::CPU
readCCReg(PhysRegIdPtr phys_reg)	gem5::o3::CPU
readFloatReg(PhysRegIdPtr phys_reg)	gem5::o3::CPU
readIntReg(PhysRegIdPtr phys_reg)	gem5::o3::CPU
readMiscReg(int misc_reg, ThreadID tid)	gem5::o3::CPU
readMiscRegNoEffect(int misc_reg, ThreadID tid) const	gem5::o3::CPU
readVecElem(PhysRegIdPtr reg_idx) const	gem5::o3::CPU
readVecPredReg(PhysRegIdPtr reg_idx) const	gem5::o3::CPU
readVecReg(PhysRegIdPtr reg_idx) const	gem5::o3::CPU
regFile	gem5::o3::CPU	protected
registerThreadContexts()	gem5::BaseCPU
regProbeListeners()	gem5::SimObject	virtual
regProbePoints() override	gem5::o3::CPU	virtual
regStats() override	gem5::BaseCPU	virtual
removeFrontInst(const DynInstPtr &inst)	gem5::o3::CPU
removeInstsNotInROB(ThreadID tid)	gem5::o3::CPU
removeInstsThisCycle	gem5::o3::CPU
removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)	gem5::o3::CPU
removeList	gem5::o3::CPU
removeThread(ThreadID tid)	gem5::o3::CPU
rename	gem5::o3::CPU	protected
RenameIdx enum value	gem5::o3::CPU
renameMap	gem5::o3::CPU	protected
renameQueue	gem5::o3::CPU
reschedule(Event &event, Tick when, bool always=false)	gem5::EventManager	inline
reschedule(Event *event, Tick when, bool always=false)	gem5::EventManager	inline
resetClock() const	gem5::Clocked	inlineprotected
resetStats()	gem5::statistics::Group	virtual
resolveStat(std::string name) const	gem5::statistics::Group
rob	gem5::o3::CPU	protected
Running enum value	gem5::o3::CPU
schedule(Event &event, Tick when)	gem5::EventManager	inline
schedule(Event *event, Tick when)	gem5::EventManager	inline
scheduleInstStop(ThreadID tid, Counter insts, const char *cause)	gem5::BaseCPU
schedulePowerGatingEvent()	gem5::BaseCPU
scheduleThreadExitEvent(ThreadID tid)	gem5::o3::CPU
scheduleTickEvent(Cycles delay)	gem5::o3::CPU	inlineprivate
scoreboard	gem5::o3::CPU	protected
Serializable()	gem5::Serializable
serialize(CheckpointOut &cp) const override	gem5::BaseCPU	virtual
serializeAll(const std::string &cpt_dir)	gem5::SimObject	static
serializeSection(CheckpointOut &cp, const char *name) const	gem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) const	gem5::Serializable	inline
serializeThread(CheckpointOut &cp, ThreadID tid) const override	gem5::o3::CPU	virtual
setArchCCReg(int reg_idx, RegVal val, ThreadID tid)	gem5::o3::CPU
setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)	gem5::o3::CPU
setArchIntReg(int reg_idx, RegVal val, ThreadID tid)	gem5::o3::CPU
setArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, const TheISA::VecElem &val, ThreadID tid)	gem5::o3::CPU
setArchVecPredReg(int reg_idx, const TheISA::VecPredRegContainer &val, ThreadID tid)	gem5::o3::CPU
setArchVecReg(int reg_idx, const TheISA::VecRegContainer &val, ThreadID tid)	gem5::o3::CPU
setCCReg(PhysRegIdPtr phys_reg, RegVal val)	gem5::o3::CPU
setCurTick(Tick newVal)	gem5::EventManager	inline
setFloatReg(PhysRegIdPtr phys_reg, RegVal val)	gem5::o3::CPU
setIntReg(PhysRegIdPtr phys_reg, RegVal val)	gem5::o3::CPU
setMiscReg(int misc_reg, RegVal val, ThreadID tid)	gem5::o3::CPU
setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)	gem5::o3::CPU
setPid(uint32_t pid)	gem5::BaseCPU	inline
setSimObjectResolver(SimObjectResolver *resolver)	gem5::SimObject	static
setVecElem(PhysRegIdPtr reg_idx, const TheISA::VecElem &val)	gem5::o3::CPU
setVecPredReg(PhysRegIdPtr reg_idx, const TheISA::VecPredRegContainer &val)	gem5::o3::CPU
setVecReg(PhysRegIdPtr reg_idx, const TheISA::VecRegContainer &val)	gem5::o3::CPU
setVectorsAsReady(ThreadID tid)	gem5::o3::CPU
signalDrainDone() const	gem5::Drainable	inlineprotected
SimObject(const Params &p)	gem5::SimObject
simObjectList	gem5::SimObject	privatestatic
SimObjectList typedef	gem5::SimObject	private
socketId() const	gem5::BaseCPU	inline
squashFromTC(ThreadID tid)	gem5::o3::CPU
squashInstIt(const ListIt &instIt, ThreadID tid)	gem5::o3::CPU
StageIdx enum name	gem5::o3::CPU
startup() override	gem5::o3::CPU	virtual
statGroups	gem5::statistics::Group	private
stats	gem5::statistics::Group	private
Status enum name	gem5::o3::CPU
suspendContext(ThreadID tid) override	gem5::o3::CPU	virtual
SwitchedOut enum value	gem5::o3::CPU
switchedOut() const	gem5::BaseCPU	inline
switchOut() override	gem5::o3::CPU	virtual
switchRenameMode(ThreadID tid, UnifiedFreeList *freelist)	gem5::o3::CPU
syscallRetryLatency	gem5::BaseCPU
system	gem5::o3::CPU
takeOverFrom(BaseCPU *oldCPU) override	gem5::o3::CPU	virtual
taskId() const	gem5::BaseCPU	inline
taskId(uint32_t id)	gem5::BaseCPU	inline
tcBase(ThreadID tid)	gem5::o3::CPU	inline
thread	gem5::o3::CPU
ThreadContext class	gem5::o3::CPU	friend
threadContexts	gem5::BaseCPU	protected
threadExitEvent	gem5::o3::CPU	private
threadMap	gem5::o3::CPU
tick()	gem5::o3::CPU
tickEvent	gem5::o3::CPU	private
ticksToCycles(Tick t) const	gem5::Clocked	inline
tids	gem5::o3::CPU
timeBuffer	gem5::o3::CPU
totalInsts() const override	gem5::o3::CPU	virtual
totalOps() const override	gem5::o3::CPU	virtual
traceFunctions(Addr pc)	gem5::BaseCPU	inline
traceFunctionsInternal(Addr pc)	gem5::BaseCPU	private
tracer	gem5::BaseCPU	protected
trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)	gem5::o3::CPU
tryDrain()	gem5::o3::CPU	private
unscheduleTickEvent()	gem5::o3::CPU	inlineprivate
unserialize(CheckpointIn &cp) override	gem5::BaseCPU	virtual
unserializeSection(CheckpointIn &cp, const char *name)	gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)	gem5::Serializable	inline
unserializeThread(CheckpointIn &cp, ThreadID tid) override	gem5::o3::CPU	virtual
update() const	gem5::Clocked	inlineprivate
updateClockPeriod()	gem5::Clocked	inline
updateCycleCounters(CPUState state)	gem5::BaseCPU	inlineprotected
updateThreadPriority()	gem5::o3::CPU
vecMode	gem5::o3::CPU	protected
vecRenameMode() const	gem5::o3::CPU	inline
vecRenameMode(enums::VecRegRenameMode vec_mode)	gem5::o3::CPU	inline
verifyMemoryMode() const override	gem5::o3::CPU	virtual
voltage() const	gem5::Clocked	inline
wakeCPU()	gem5::o3::CPU
wakeup(ThreadID tid) override	gem5::o3::CPU	virtual
wakeupEventQueue(Tick when=(Tick) -1)	gem5::EventManager	inline
workItemBegin()	gem5::BaseCPU	inline
workItemEnd()	gem5::BaseCPU	inline
write(LSQRequest *req, uint8_t *data, int store_idx)	gem5::o3::CPU	inline
~BaseCPU()	gem5::BaseCPU	virtual
~Clocked()	gem5::Clocked	inlineprotectedvirtual
~Drainable()	gem5::Drainable	protectedvirtual
~Group()	gem5::statistics::Group	virtual
~Named()=default	gem5::Named	virtual
~Serializable()	gem5::Serializable	virtual
~SimObject()	gem5::SimObject	virtual